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drm/nv50-/disp: audit and version SOR_PWR method

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The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-08-10 04:10:26 +10:00
parent c4abd3178e
commit d55b4af909
10 changed files with 45 additions and 26 deletions
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3
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
View File

@ -903,6 +903,8 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
return priv->dac.power(object, priv, data, size, head, outp);
case NV50_DISP_MTHD_V1_DAC_LOAD:
return priv->dac.sense(object, priv, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_PWR:
return priv->sor.power(object, priv, data, size, head, outp);
default:
break;
}
@ -1031,7 +1033,6 @@ nv50_disp_base_ofuncs = {
static struct nouveau_omthds
nv50_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },

4
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
View File

@ -46,7 +46,7 @@ struct nv50_disp_priv {
} dac;
struct {
int nr;
int (*power)(struct nv50_disp_priv *, int sor, u32 data);
int (*power)(NV50_DISP_MTHD_V1);
int (*hda_eld)(struct nv50_disp_priv *, int sor, u8 *, u32);
int (*hdmi)(struct nv50_disp_priv *, int head, int sor, u32);
u32 lvdsconf;
@ -78,7 +78,7 @@ int nva3_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);
int nvd0_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);
int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);
int nv50_sor_power(struct nv50_disp_priv *, int, u32);
int nv50_sor_power(NV50_DISP_MTHD_V1);
int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,
u32, struct dcb_output *);

1
drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
View File

@ -215,7 +215,6 @@ nv84_disp_sclass[] = {
struct nouveau_omthds
nv84_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },

1
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
View File

@ -74,7 +74,6 @@ nv94_disp_sclass[] = {
static struct nouveau_omthds
nv94_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
{ SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },

1
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
View File

@ -46,7 +46,6 @@ nva3_disp_sclass[] = {
static struct nouveau_omthds
nva3_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },

1
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
View File

@ -712,7 +712,6 @@ nvd0_disp_base_ofuncs = {
struct nouveau_omthds
nvd0_disp_base_omthds[] = {
{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nvd0_disp_base_scanoutpos },
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },

26
drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
View File

@ -22,8 +22,10 @@
* Authors: Ben Skeggs
*/
#include <core/os.h>
#include <core/client.h>
#include <core/class.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
@ -32,10 +34,23 @@
#include "nv50.h"
int
nv50_sor_power(struct nv50_disp_priv *priv, int or, u32 data)
nv50_sor_power(NV50_DISP_MTHD_V1)
{
const u32 stat = data & NV50_DISP_SOR_PWR_STATE;
const u32 soff = (or * 0x800);
union {
struct nv50_disp_sor_pwr_v0 v0;
} *args = data;
const u32 soff = outp->or * 0x800;
u32 stat;
int ret;
nv_ioctl(object, "disp sor pwr size %d\n", size);
if (nvif_unpack(args->v0, 0, 0, false)) {
nv_ioctl(object, "disp sor pwr vers %d state %d\n",
args->v0.version, args->v0.state);
stat = !!args->v0.state;
} else
return ret;
nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
@ -69,9 +84,6 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
}
switch (mthd & ~0x3f) {
case NV50_DISP_SOR_PWR:
ret = priv->sor.power(priv, or, data);
break;
case NVA3_DISP_SOR_HDA_ELD:
ret = priv->sor.hda_eld(priv, or, args, size);
break;

4
drivers/gpu/drm/nouveau/core/include/core/class.h
View File

@ -59,10 +59,6 @@ struct nv04_display_scanoutpos {
#define NV50_DISP_SOR_MTHD_LINK 0x00000004
#define NV50_DISP_SOR_MTHD_OR 0x00000003
#define NV50_DISP_SOR_PWR 0x00010000
#define NV50_DISP_SOR_PWR_STATE 0x00000001
#define NV50_DISP_SOR_PWR_STATE_ON 0x00000001
#define NV50_DISP_SOR_PWR_STATE_OFF 0x00000000
#define NVA3_DISP_SOR_HDA_ELD 0x00010100
#define NV84_DISP_SOR_HDMI_PWR 0x00012000
#define NV84_DISP_SOR_HDMI_PWR_STATE 0x40000000

26
drivers/gpu/drm/nouveau/nv50_display.c
View File

@ -1482,7 +1482,6 @@ nv50_dac_dpms(struct drm_encoder *encoder, int mode)
mode != DRM_MODE_DPMS_OFF),
};
nvif_mthd(disp->disp, 0, &args, sizeof(args));
}
@ -1742,8 +1741,18 @@ static void
nv50_sor_dpms(struct drm_encoder *encoder, int mode)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct nv50_disp *disp = nv50_disp(encoder->dev);
struct {
struct nv50_disp_mthd_v1 base;
struct nv50_disp_sor_pwr_v0 pwr;
} args = {
.base.version = 1,
.base.method = NV50_DISP_MTHD_V1_SOR_PWR,
.base.hasht = nv_encoder->dcb->hasht,
.base.hashm = nv_encoder->dcb->hashm,
.pwr.state = mode == DRM_MODE_DPMS_ON,
};
struct drm_device *dev = encoder->dev;
struct nv50_disp *disp = nv50_disp(dev);
struct drm_encoder *partner;
u32 mthd, data;
@ -1768,15 +1777,14 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
mthd |= nv_encoder->or;
if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
data = 1;
nvif_exec(disp->disp, NV50_DISP_SOR_PWR | mthd, &data, sizeof(data));
mthd |= NV94_DISP_SOR_DP_PWR;
} else {
mthd |= NV50_DISP_SOR_PWR;
}
args.pwr.state = 1;
nvif_mthd(disp->disp, 0, &args, sizeof(args));
data = (mode == DRM_MODE_DPMS_ON);
mthd |= NV94_DISP_SOR_DP_PWR;
nvif_exec(disp->disp, mthd, &data, sizeof(data));
} else {
nvif_mthd(disp->disp, 0, &args, sizeof(args));
}
}
static bool

6
drivers/gpu/drm/nouveau/nvif/class.h
View File

@ -340,4 +340,10 @@ struct nv50_disp_dac_load_v0 {
__u8 pad04[4];
};
struct nv50_disp_sor_pwr_v0 {
__u8 version;
__u8 state;
__u8 pad02[6];
};
#endif