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drm/i915: reject modes the LPT FDI receiver can't handle
More specifically, the LPT FDI RX only supports 8bpc and a maximum of 2 lanes, so anything above that won't work and should be rejected. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -198,6 +198,11 @@ static int intel_crt_mode_valid(struct drm_connector *connector,
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if (mode->clock > max_clock)
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return MODE_CLOCK_HIGH;
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/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
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if (HAS_PCH_LPT(dev) &&
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(ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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}
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@ -5228,6 +5228,17 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
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}
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}
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int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
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{
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/*
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* Account for spread spectrum to avoid
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* oversubscribing the link. Max center spread
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* is 2.5%; use 5% for safety's sake.
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*/
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u32 bps = target_clock * bpp * 21 / 20;
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return bps / (link_bw * 8) + 1;
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}
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static void ironlake_set_m_n(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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@ -5281,15 +5292,9 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
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else
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target_clock = adjusted_mode->clock;
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if (!lane) {
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/*
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* Account for spread spectrum to avoid
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* oversubscribing the link. Max center spread
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* is 2.5%; use 5% for safety's sake.
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*/
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u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
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lane = bps / (link_bw * 8) + 1;
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}
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if (!lane)
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lane = ironlake_get_lanes_required(target_clock, link_bw,
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intel_crtc->bpp);
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intel_crtc->fdi_lanes = lane;
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@ -559,6 +559,7 @@ intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
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enum pipe pipe);
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extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
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extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
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extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
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struct intel_load_detect_pipe {
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struct drm_framebuffer *release_fb;
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