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MIPS: c-r4k: Drop bc_wback_inv() from icache flush

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The EVA conditional bc_wback_inv() at the end of flush_icache_range() to
flush the modified code all the way back to RAM was apparently there for
debug purposes and to accommodate the Malta EVA configuration which
makes use of a physical alias, and didn't use the CP0_EBase.WG (Write
Gate) bit to put the exception vector in the same physical alias where
the exception vector code is written and is being flushed.

Now that CP0_EBase.WG is used, lets drop this flush.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14151/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan 2016-09-01 17:30:10 +01:00 committed by Ralf Baechle
parent 4b22c693e3
commit d260d97e64
1 changed files with 0 additions and 11 deletions
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11
arch/mips/mm/c-r4k.c
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@ -752,17 +752,6 @@ static inline void __local_r4k_flush_icache_range(unsigned long start,
break;
}
}
#ifdef CONFIG_EVA
/*
* Due to all possible segment mappings, there might cache aliases
* caused by the bootloader being in non-EVA mode, and the CPU switching
* to EVA during early kernel init. It's best to flush the scache
* to avoid having secondary cores fetching stale data and lead to
* kernel crashes.
*/
bc_wback_inv(start, (end - start));
__sync();
#endif
}
static inline void local_r4k_flush_icache_range(unsigned long start,