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https://github.com/edk2-porting/linux-next.git
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amd64_edac: Remove "amd64" prefix from static functions
No need for the namespace tagging there. Cleanup setup_pci_device while at it. Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Borislav Petkov
parent
df781d0386
commit
d1ea71cdc9
@ -1,7 +1,7 @@
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#include "amd64_edac.h"
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#include <asm/amd_nb.h>
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static struct edac_pci_ctl_info *amd64_ctl_pci;
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static struct edac_pci_ctl_info *pci_ctl;
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static int report_gart_errors;
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module_param(report_gart_errors, int, 0644);
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@ -162,7 +162,7 @@ static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
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* scan the scrub rate mapping table for a close or matching bandwidth value to
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* issue. If requested is too big, then use last maximum value found.
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*/
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static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
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static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
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{
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u32 scrubval;
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int i;
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@ -198,7 +198,7 @@ static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
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return 0;
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}
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static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 min_scrubrate = 0x5;
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@ -210,10 +210,10 @@ static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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if (pvt->fam == 0x15 && pvt->model < 0x10)
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f15h_select_dct(pvt, 0);
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return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
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return __set_scrub_rate(pvt->F3, bw, min_scrubrate);
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}
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static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
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static int get_scrub_rate(struct mem_ctl_info *mci)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 scrubval = 0;
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@ -240,8 +240,7 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
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* returns true if the SysAddr given by sys_addr matches the
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* DRAM base/limit associated with node_id
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*/
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static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr,
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u8 nid)
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static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
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{
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u64 addr;
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@ -285,7 +284,7 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
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if (intlv_en == 0) {
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for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
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if (amd64_base_limit_match(pvt, sys_addr, node_id))
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if (base_limit_match(pvt, sys_addr, node_id))
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goto found;
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}
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goto err_no_match;
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@ -309,7 +308,7 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
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}
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/* sanity test for sys_addr */
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if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) {
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if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
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amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
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"range for node %d with node interleaving enabled.\n",
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__func__, sys_addr, node_id);
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@ -660,7 +659,7 @@ static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
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* Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
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* are ECC capable.
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*/
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static unsigned long amd64_determine_edac_cap(struct amd64_pvt *pvt)
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static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
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{
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u8 bit;
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unsigned long edac_cap = EDAC_FLAG_NONE;
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@ -675,9 +674,9 @@ static unsigned long amd64_determine_edac_cap(struct amd64_pvt *pvt)
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return edac_cap;
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}
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static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8);
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static void debug_display_dimm_sizes(struct amd64_pvt *, u8);
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static void amd64_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
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static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
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{
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edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
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@ -711,7 +710,7 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
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(pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
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(pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
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amd64_dump_dramcfg_low(pvt, pvt->dclr0, 0);
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debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
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edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
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@ -722,19 +721,19 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
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edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
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amd64_debug_display_dimm_sizes(pvt, 0);
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debug_display_dimm_sizes(pvt, 0);
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/* everything below this point is Fam10h and above */
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if (pvt->fam == 0xf)
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return;
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amd64_debug_display_dimm_sizes(pvt, 1);
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debug_display_dimm_sizes(pvt, 1);
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amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
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/* Only if NOT ganged does dclr1 have valid info */
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if (!dct_ganging_enabled(pvt))
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amd64_dump_dramcfg_low(pvt, pvt->dclr1, 1);
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debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
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}
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/*
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@ -800,7 +799,7 @@ static void read_dct_base_mask(struct amd64_pvt *pvt)
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}
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}
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static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs)
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static enum mem_type determine_memory_type(struct amd64_pvt *pvt, int cs)
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{
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enum mem_type type;
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@ -1702,7 +1701,7 @@ static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
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* debug routine to display the memory sizes of all logical DIMMs and its
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* CSROWs
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*/
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static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
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static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
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{
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int dimm, size0, size1;
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u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
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@ -1744,7 +1743,7 @@ static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
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}
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}
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static struct amd64_family_type amd64_family_types[] = {
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static struct amd64_family_type family_types[] = {
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[K8_CPUS] = {
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.ctl_name = "K8",
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.f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
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@ -2191,7 +2190,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
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* encompasses
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*
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*/
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static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
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static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
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{
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u32 cs_mode, nr_pages;
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u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
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@ -2258,19 +2257,19 @@ static int init_csrows(struct mem_ctl_info *mci)
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pvt->mc_node_id, i);
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if (row_dct0) {
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nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
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nr_pages = get_csrow_nr_pages(pvt, 0, i);
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csrow->channels[0]->dimm->nr_pages = nr_pages;
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}
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/* K8 has only one DCT */
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if (pvt->fam != 0xf && row_dct1) {
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int row_dct1_pages = amd64_csrow_nr_pages(pvt, 1, i);
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int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i);
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csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
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nr_pages += row_dct1_pages;
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}
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mtype = amd64_determine_memory_type(pvt, i);
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mtype = determine_memory_type(pvt, i);
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edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
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@ -2304,7 +2303,7 @@ static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
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}
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/* check MCG_CTL on all the cpus on this node */
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static bool amd64_nb_mce_bank_enabled_on_node(u16 nid)
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static bool nb_mce_bank_enabled_on_node(u16 nid)
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{
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cpumask_var_t mask;
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int cpu, nbe;
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@ -2477,7 +2476,7 @@ static bool ecc_enabled(struct pci_dev *F3, u16 nid)
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ecc_en = !!(value & NBCFG_ECC_ENABLE);
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amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled"));
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nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid);
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nb_mce_en = nb_mce_bank_enabled_on_node(nid);
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if (!nb_mce_en)
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amd64_notice("NB MCE bank disabled, set MSR "
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"0x%08x[4] on node %d to enable.\n",
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@ -2532,7 +2531,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci,
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if (pvt->nbcap & NBCAP_CHIPKILL)
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mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
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mci->edac_cap = amd64_determine_edac_cap(pvt);
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mci->edac_cap = determine_edac_cap(pvt);
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = EDAC_AMD64_VERSION;
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mci->ctl_name = fam->ctl_name;
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@ -2540,14 +2539,14 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci,
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mci->ctl_page_to_phys = NULL;
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/* memory scrubber interface */
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mci->set_sdram_scrub_rate = amd64_set_scrub_rate;
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mci->get_sdram_scrub_rate = amd64_get_scrub_rate;
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mci->set_sdram_scrub_rate = set_scrub_rate;
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mci->get_sdram_scrub_rate = get_scrub_rate;
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}
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/*
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* returns a pointer to the family descriptor on success, NULL otherwise.
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*/
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static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
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static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
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{
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struct amd64_family_type *fam_type = NULL;
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@ -2558,29 +2557,29 @@ static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
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switch (pvt->fam) {
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case 0xf:
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fam_type = &amd64_family_types[K8_CPUS];
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pvt->ops = &amd64_family_types[K8_CPUS].ops;
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fam_type = &family_types[K8_CPUS];
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pvt->ops = &family_types[K8_CPUS].ops;
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break;
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case 0x10:
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fam_type = &amd64_family_types[F10_CPUS];
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pvt->ops = &amd64_family_types[F10_CPUS].ops;
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fam_type = &family_types[F10_CPUS];
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pvt->ops = &family_types[F10_CPUS].ops;
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break;
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case 0x15:
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if (pvt->model == 0x30) {
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fam_type = &amd64_family_types[F15_M30H_CPUS];
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pvt->ops = &amd64_family_types[F15_M30H_CPUS].ops;
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fam_type = &family_types[F15_M30H_CPUS];
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pvt->ops = &family_types[F15_M30H_CPUS].ops;
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break;
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}
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fam_type = &amd64_family_types[F15_CPUS];
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pvt->ops = &amd64_family_types[F15_CPUS].ops;
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fam_type = &family_types[F15_CPUS];
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pvt->ops = &family_types[F15_CPUS].ops;
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break;
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case 0x16:
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fam_type = &amd64_family_types[F16_CPUS];
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pvt->ops = &amd64_family_types[F16_CPUS].ops;
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fam_type = &family_types[F16_CPUS];
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pvt->ops = &family_types[F16_CPUS].ops;
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break;
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default:
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@ -2596,7 +2595,7 @@ static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
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return fam_type;
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}
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static int amd64_init_one_instance(struct pci_dev *F2)
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static int init_one_instance(struct pci_dev *F2)
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{
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struct amd64_pvt *pvt = NULL;
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struct amd64_family_type *fam_type = NULL;
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@ -2614,7 +2613,7 @@ static int amd64_init_one_instance(struct pci_dev *F2)
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pvt->F2 = F2;
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ret = -EINVAL;
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fam_type = amd64_per_family_init(pvt);
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fam_type = per_family_init(pvt);
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if (!fam_type)
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goto err_free;
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@ -2698,8 +2697,8 @@ err_ret:
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return ret;
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}
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static int amd64_probe_one_instance(struct pci_dev *pdev,
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const struct pci_device_id *mc_type)
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static int probe_one_instance(struct pci_dev *pdev,
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const struct pci_device_id *mc_type)
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{
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u16 nid = amd_get_node_id(pdev);
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struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
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@ -2731,7 +2730,7 @@ static int amd64_probe_one_instance(struct pci_dev *pdev,
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goto err_enable;
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}
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ret = amd64_init_one_instance(pdev);
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ret = init_one_instance(pdev);
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if (ret < 0) {
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amd64_err("Error probing instance: %d\n", nid);
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restore_ecc_error_reporting(s, nid, F3);
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@ -2747,7 +2746,7 @@ err_out:
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return ret;
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}
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static void amd64_remove_one_instance(struct pci_dev *pdev)
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static void remove_one_instance(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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@ -2838,8 +2837,8 @@ MODULE_DEVICE_TABLE(pci, amd64_pci_table);
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static struct pci_driver amd64_pci_driver = {
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.name = EDAC_MOD_STR,
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.probe = amd64_probe_one_instance,
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.remove = amd64_remove_one_instance,
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.probe = probe_one_instance,
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.remove = remove_one_instance,
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.id_table = amd64_pci_table,
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};
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@ -2848,23 +2847,18 @@ static void setup_pci_device(void)
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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if (amd64_ctl_pci)
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if (pci_ctl)
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return;
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mci = mcis[0];
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if (mci) {
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if (!mci)
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return;
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pvt = mci->pvt_info;
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amd64_ctl_pci =
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edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
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if (!amd64_ctl_pci) {
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pr_warning("%s(): Unable to create PCI control\n",
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__func__);
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pr_warning("%s(): PCI error report via EDAC not set\n",
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__func__);
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}
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pvt = mci->pvt_info;
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pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
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if (!pci_ctl) {
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pr_warn("%s(): Unable to create PCI control\n", __func__);
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pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
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}
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}
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@ -2920,8 +2914,8 @@ err_ret:
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static void __exit amd64_edac_exit(void)
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{
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if (amd64_ctl_pci)
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edac_pci_release_generic_ctl(amd64_ctl_pci);
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if (pci_ctl)
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edac_pci_release_generic_ctl(pci_ctl);
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pci_unregister_driver(&amd64_pci_driver);
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