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mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning
hardware has 16bit to record the tuning count, so fix it to 16384. at the same time, tuned_phases[SIRF_TUNING_COUNT] is useless as the array is never used, so move it to a variant. Signed-off-by: Weijun Yang <Weijun.Yang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -17,7 +17,7 @@
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#define SDHCI_CLK_DELAY_SETTING 0x4C
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#define SDHCI_SIRF_8BITBUS BIT(3)
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#define SIRF_TUNING_COUNT 128
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#define SIRF_TUNING_COUNT 16384
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struct sdhci_sirf_priv {
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int gpio_cd;
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@ -46,7 +46,7 @@ static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
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static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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int tuning_seq_cnt = 3;
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u8 phase, tuned_phases[SIRF_TUNING_COUNT];
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int phase;
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u8 tuned_phase_cnt = 0;
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int rc = 0, longest_range = 0;
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int start = -1, end = 0, tuning_value = -1, range = 0;
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@ -58,6 +58,7 @@ static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
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retry:
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phase = 0;
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tuned_phase_cnt = 0;
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do {
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sdhci_writel(host,
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clock_setting | phase,
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@ -65,7 +66,7 @@ retry:
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if (!mmc_send_tuning(mmc)) {
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/* Tuning is successful at this tuning point */
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tuned_phases[tuned_phase_cnt++] = phase;
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tuned_phase_cnt++;
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dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
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mmc_hostname(mmc), phase);
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if (start == -1)
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@ -85,7 +86,7 @@ retry:
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start = -1;
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end = range = 0;
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}
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} while (++phase < ARRAY_SIZE(tuned_phases));
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} while (++phase < SIRF_TUNING_COUNT);
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if (tuned_phase_cnt && tuning_value > 0) {
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/*
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