mirror of
https://github.com/edk2-porting/linux-next.git
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Merge branch 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
* 'at91-fixes' of git://github.com/at91linux/linux-at91: ARM: at91: Fix at91sam9g45 and at91cap9 reset ARM: at91: make rstc soc independent ARM: at91: introduce AT91_SAM9_ALT_RESET to select the at91sam9 alternative reset ARM: at91: merge at91cap9_ddrsdr.h in at91sam9_ddrsdr.h ARM: at91: fix cap9 ddrsdr register ARM/USB: at91/ohci-at91: rename vbus_pin_inverted to vbus_pin_active_low USB: at91: fix clk_get error handling ARM: at91: removal of CAP9 SoC family ARM: at91: fix at91rm9200 soc subtype handling
This commit is contained in:
Olof Johansson
commit
d1a8c54b70
@ -510,3 +510,17 @@ Why: The pci_scan_bus_parented() interface creates a new root bus. The
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convert to using pci_scan_root_bus() so they can supply a list of
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bus resources when the bus is created.
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Who: Bjorn Helgaas <bhelgaas@google.com>
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----------------------------
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What: The CAP9 SoC family will be removed
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When: 3.4
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Files: arch/arm/mach-at91/at91cap9.c
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arch/arm/mach-at91/at91cap9_devices.c
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arch/arm/mach-at91/include/mach/at91cap9.h
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arch/arm/mach-at91/include/mach/at91cap9_matrix.h
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arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
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arch/arm/mach-at91/board-cap9adk.c
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Why: The code is not actively maintained and platforms are now hard to find.
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Who: Nicolas Ferre <nicolas.ferre@atmel.com>
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Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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@ -18,6 +18,12 @@ config HAVE_AT91_USART4
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config HAVE_AT91_USART5
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bool
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config AT91_SAM9_ALT_RESET
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bool
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config AT91_SAM9G45_RESET
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bool
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menu "Atmel AT91 System-on-Chip"
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choice
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@ -39,6 +45,7 @@ config ARCH_AT91SAM9260
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select HAVE_AT91_USART4
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select HAVE_AT91_USART5
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select HAVE_NET_MACB
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select AT91_SAM9_ALT_RESET
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config ARCH_AT91SAM9261
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bool "AT91SAM9261"
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@ -46,6 +53,7 @@ config ARCH_AT91SAM9261
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select GENERIC_CLOCKEVENTS
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select HAVE_FB_ATMEL
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select HAVE_AT91_DBGU0
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select AT91_SAM9_ALT_RESET
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config ARCH_AT91SAM9G10
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bool "AT91SAM9G10"
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@ -53,6 +61,7 @@ config ARCH_AT91SAM9G10
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select GENERIC_CLOCKEVENTS
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select HAVE_AT91_DBGU0
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select HAVE_FB_ATMEL
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select AT91_SAM9_ALT_RESET
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config ARCH_AT91SAM9263
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bool "AT91SAM9263"
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@ -61,6 +70,7 @@ config ARCH_AT91SAM9263
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select HAVE_FB_ATMEL
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select HAVE_NET_MACB
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select HAVE_AT91_DBGU1
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select AT91_SAM9_ALT_RESET
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config ARCH_AT91SAM9RL
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bool "AT91SAM9RL"
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@ -69,6 +79,7 @@ config ARCH_AT91SAM9RL
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select HAVE_AT91_USART3
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select HAVE_FB_ATMEL
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select HAVE_AT91_DBGU0
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select AT91_SAM9_ALT_RESET
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config ARCH_AT91SAM9G20
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bool "AT91SAM9G20"
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@ -79,6 +90,7 @@ config ARCH_AT91SAM9G20
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select HAVE_AT91_USART4
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select HAVE_AT91_USART5
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select HAVE_NET_MACB
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select AT91_SAM9_ALT_RESET
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config ARCH_AT91SAM9G45
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bool "AT91SAM9G45"
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@ -88,6 +100,7 @@ config ARCH_AT91SAM9G45
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select HAVE_FB_ATMEL
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select HAVE_NET_MACB
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select HAVE_AT91_DBGU1
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select AT91_SAM9G45_RESET
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config ARCH_AT91CAP9
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bool "AT91CAP9"
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@ -96,6 +109,7 @@ config ARCH_AT91CAP9
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select HAVE_FB_ATMEL
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select HAVE_NET_MACB
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select HAVE_AT91_DBGU1
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select AT91_SAM9G45_RESET
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config ARCH_AT91X40
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bool "AT91x40"
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@ -8,15 +8,17 @@ obj-n :=
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obj- :=
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obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
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obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
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obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
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# CPU-specific support
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obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
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obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
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obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
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obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o
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obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o
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obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
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obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
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obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
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obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
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obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
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obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
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obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
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obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
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obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
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obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
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@ -21,7 +21,6 @@
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#include <mach/cpu.h>
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#include <mach/at91cap9.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_rstc.h>
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#include "soc.h"
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#include "generic.h"
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@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
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}
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};
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static void at91cap9_restart(char mode, const char *cmd)
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{
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
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}
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/* --------------------------------------------------------------------
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* AT91CAP9 processor initialization
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* -------------------------------------------------------------------- */
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@ -331,13 +325,14 @@ static void __init at91cap9_map_io(void)
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static void __init at91cap9_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
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at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
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at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
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}
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static void __init at91cap9_initialize(void)
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{
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arm_pm_restart = at91cap9_restart;
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arm_pm_restart = at91sam9g45_restart;
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at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
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/* Register GPIO subsystem */
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@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void)
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static void __init at91sam9260_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
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at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
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}
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@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void)
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static void __init at91sam9261_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
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at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
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}
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@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void)
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static void __init at91sam9263_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
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at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
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at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
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@ -23,7 +23,8 @@
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.globl at91sam9_alt_restart
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at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
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ldr r1, .at91_va_base_rstc_cr
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ldr r1, =at91_rstc_base
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ldr r1, [r1]
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mov r2, #1
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mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
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@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
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str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
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str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
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str r4, [r1] @ reset processor
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str r4, [r1, #AT91_RSTC_CR] @ reset processor
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b .
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.at91_va_base_sdramc:
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.word AT91_VA_BASE_SYS + AT91_SDRAMC0
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.at91_va_base_rstc_cr:
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.word AT91_VA_BASE_SYS + AT91_RSTC_CR
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@ -18,7 +18,6 @@
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#include <asm/mach/map.h>
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#include <mach/at91sam9g45.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_rstc.h>
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#include <mach/cpu.h>
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#include "soc.h"
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@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
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}
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};
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static void at91sam9g45_restart(char mode, const char *cmd)
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{
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9G45 processor initialization
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* -------------------------------------------------------------------- */
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@ -336,6 +330,7 @@ static void __init at91sam9g45_map_io(void)
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static void __init at91sam9g45_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
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at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
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}
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40
arch/arm/mach-at91/at91sam9g45_reset.S
Normal file
40
arch/arm/mach-at91/at91sam9g45_reset.S
Normal file
@ -0,0 +1,40 @@
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/*
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* reset AT91SAM9G45 as per errata
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*
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
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*
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* unless the SDRAM is cleanly shutdown before we hit the
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* reset register it can be left driving the data bus and
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* killing the chance of a subsequent boot from NAND
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*
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* GPLv2 Only
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*/
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#include <linux/linkage.h>
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#include <mach/hardware.h>
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#include <mach/at91sam9_ddrsdr.h>
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#include <mach/at91_rstc.h>
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.arm
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.globl at91sam9g45_restart
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at91sam9g45_restart:
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ldr r0, .at91_va_base_sdramc0 @ preload constants
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ldr r1, =at91_rstc_base
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ldr r1, [r1]
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mov r2, #1
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mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
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ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
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.balign 32 @ align to cache line
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str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
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str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
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str r4, [r1, #AT91_RSTC_CR] @ reset processor
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b .
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.at91_va_base_sdramc0:
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.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
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@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void)
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static void __init at91sam9rl_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
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at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
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}
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@ -58,7 +58,9 @@ extern void at91_irq_suspend(void);
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extern void at91_irq_resume(void);
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/* reset */
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extern void at91_ioremap_rstc(u32 base_addr);
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extern void at91sam9_alt_restart(char, const char *);
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extern void at91sam9g45_restart(char, const char *);
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/* shutdown */
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extern void at91_ioremap_shdwc(u32 base_addr);
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@ -16,13 +16,25 @@
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#ifndef AT91_RSTC_H
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#define AT91_RSTC_H
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#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
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#ifndef __ASSEMBLY__
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extern void __iomem *at91_rstc_base;
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#define at91_rstc_read(field) \
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__raw_readl(at91_rstc_base + field)
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#define at91_rstc_write(field, value) \
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__raw_writel(value, at91_rstc_base + field);
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#else
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.extern at91_rstc_base
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#endif
|
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|
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#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
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#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
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#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
|
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#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
|
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#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
|
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|
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#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
|
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#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
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#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
|
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#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
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#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
|
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@ -33,7 +45,7 @@
|
||||
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
|
||||
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
|
||||
|
||||
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
|
||||
#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
|
||||
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
|
||||
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
|
||||
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
|
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|
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@ -83,7 +83,6 @@
|
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#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
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#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
|
||||
(0xfffffd50 - AT91_BASE_SYS) : \
|
||||
(0xfffffd60 - AT91_BASE_SYS))
|
||||
@ -96,6 +95,7 @@
|
||||
#define AT91CAP9_BASE_PIOB 0xfffff400
|
||||
#define AT91CAP9_BASE_PIOC 0xfffff600
|
||||
#define AT91CAP9_BASE_PIOD 0xfffff800
|
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#define AT91CAP9_BASE_RSTC 0xfffffd00
|
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#define AT91CAP9_BASE_SHDWC 0xfffffd10
|
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#define AT91CAP9_BASE_RTT 0xfffffd20
|
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#define AT91CAP9_BASE_PIT 0xfffffd30
|
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|
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@ -1,108 +0,0 @@
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||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
|
||||
*
|
||||
* (C) 2008 Andrew Victor
|
||||
*
|
||||
* DDR/SDR Controller (DDRSDRC) - System peripherals registers.
|
||||
* Based on AT91CAP9 datasheet revision B.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91CAP9_DDRSDR_H
|
||||
#define AT91CAP9_DDRSDR_H
|
||||
|
||||
#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
|
||||
#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
|
||||
#define AT91_DDRSDRC_MODE_NORMAL 0
|
||||
#define AT91_DDRSDRC_MODE_NOP 1
|
||||
#define AT91_DDRSDRC_MODE_PRECHARGE 2
|
||||
#define AT91_DDRSDRC_MODE_LMR 3
|
||||
#define AT91_DDRSDRC_MODE_REFRESH 4
|
||||
#define AT91_DDRSDRC_MODE_EXT_LMR 5
|
||||
#define AT91_DDRSDRC_MODE_DEEP 6
|
||||
|
||||
#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
|
||||
#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
|
||||
|
||||
#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
|
||||
#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
|
||||
#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
|
||||
#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
|
||||
#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
|
||||
#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
|
||||
#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
|
||||
#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
|
||||
#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
|
||||
#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
|
||||
#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
|
||||
#define AT91_DDRSDRC_NR_11 (0 << 2)
|
||||
#define AT91_DDRSDRC_NR_12 (1 << 2)
|
||||
#define AT91_DDRSDRC_NR_13 (2 << 2)
|
||||
#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
|
||||
#define AT91_DDRSDRC_CAS_2 (2 << 4)
|
||||
#define AT91_DDRSDRC_CAS_3 (3 << 4)
|
||||
#define AT91_DDRSDRC_CAS_25 (6 << 4)
|
||||
#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
|
||||
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
|
||||
|
||||
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
|
||||
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
|
||||
#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
|
||||
#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
|
||||
#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
|
||||
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
|
||||
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
|
||||
#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
|
||||
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
|
||||
|
||||
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
|
||||
#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
|
||||
#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
|
||||
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
|
||||
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
|
||||
|
||||
#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
|
||||
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
|
||||
#define AT91_DDRSDRC_LPCB_DISABLE 0
|
||||
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
|
||||
#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
|
||||
#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
|
||||
#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
|
||||
#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
|
||||
#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
|
||||
#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
|
||||
#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
|
||||
#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
|
||||
#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
|
||||
#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
|
||||
|
||||
#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
|
||||
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
||||
#define AT91_DDRSDRC_MD_SDR 0
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
||||
#define AT91_DDRSDRC_MD_DDR 2
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
||||
|
||||
#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
|
||||
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
|
||||
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
|
||||
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
|
||||
#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
|
||||
#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
|
||||
#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
|
||||
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
|
||||
#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
|
||||
#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
|
||||
|
||||
/* Register access macros */
|
||||
#define at91_ramc_read(num, reg) \
|
||||
at91_sys_read(AT91_DDRSDRC##num + reg)
|
||||
#define at91_ramc_write(num, reg, value) \
|
||||
at91_sys_write(AT91_DDRSDRC##num + reg, value)
|
||||
|
||||
|
||||
#endif
|
||||
@ -83,7 +83,6 @@
|
||||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9260_BASE_ECC 0xffffe800
|
||||
@ -92,6 +91,7 @@
|
||||
#define AT91SAM9260_BASE_PIOA 0xfffff400
|
||||
#define AT91SAM9260_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9260_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9260_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9260_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9260_BASE_PIT 0xfffffd30
|
||||
|
||||
@ -68,7 +68,6 @@
|
||||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9261_BASE_SMC 0xffffec00
|
||||
@ -76,6 +75,7 @@
|
||||
#define AT91SAM9261_BASE_PIOA 0xfffff400
|
||||
#define AT91SAM9261_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9261_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9261_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9261_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9261_BASE_PIT 0xfffffd30
|
||||
|
||||
@ -78,7 +78,6 @@
|
||||
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9263_BASE_ECC0 0xffffe000
|
||||
@ -91,6 +90,7 @@
|
||||
#define AT91SAM9263_BASE_PIOC 0xfffff600
|
||||
#define AT91SAM9263_BASE_PIOD 0xfffff800
|
||||
#define AT91SAM9263_BASE_PIOE 0xfffffa00
|
||||
#define AT91SAM9263_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9263_BASE_RTT0 0xfffffd20
|
||||
#define AT91SAM9263_BASE_PIT 0xfffffd30
|
||||
|
||||
@ -46,10 +46,10 @@
|
||||
#define AT91_DDRSDRC_CAS_25 (6 << 4)
|
||||
#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
|
||||
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
|
||||
#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
|
||||
#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
|
||||
#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
|
||||
#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
|
||||
#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
|
||||
|
||||
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
|
||||
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
|
||||
@ -59,7 +59,8 @@
|
||||
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
|
||||
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
|
||||
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
|
||||
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
|
||||
#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
|
||||
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
|
||||
|
||||
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
|
||||
@ -68,13 +69,14 @@
|
||||
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
|
||||
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
|
||||
|
||||
#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
|
||||
#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
|
||||
#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
|
||||
#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
|
||||
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
|
||||
|
||||
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
|
||||
#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
|
||||
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
|
||||
#define AT91_DDRSDRC_LPCB_DISABLE 0
|
||||
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
|
||||
@ -92,32 +94,40 @@
|
||||
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
|
||||
|
||||
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
|
||||
#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
|
||||
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
||||
#define AT91_DDRSDRC_MD_SDR 0
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
||||
#define AT91CAP9_DDRSDRC_MD_DDR 2
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
||||
#define AT91_DDRSDRC_MD_DDR2 6
|
||||
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
|
||||
#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
|
||||
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
|
||||
|
||||
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
|
||||
#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
|
||||
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
|
||||
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
|
||||
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
|
||||
#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
|
||||
#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
|
||||
#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
|
||||
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
|
||||
#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
|
||||
#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
|
||||
|
||||
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
|
||||
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
|
||||
|
||||
#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
|
||||
|
||||
#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
|
||||
#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
|
||||
#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
|
||||
#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
|
||||
|
||||
#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
|
||||
#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
|
||||
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
|
||||
|
||||
|
||||
@ -90,7 +90,6 @@
|
||||
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9G45_BASE_ECC 0xffffe200
|
||||
@ -102,6 +101,7 @@
|
||||
#define AT91SAM9G45_BASE_PIOC 0xfffff600
|
||||
#define AT91SAM9G45_BASE_PIOD 0xfffff800
|
||||
#define AT91SAM9G45_BASE_PIOE 0xfffffa00
|
||||
#define AT91SAM9G45_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9G45_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9G45_BASE_PIT 0xfffffd30
|
||||
|
||||
@ -72,7 +72,6 @@
|
||||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
@ -84,6 +83,7 @@
|
||||
#define AT91SAM9RL_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9RL_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9RL_BASE_PIOD 0xfffffa00
|
||||
#define AT91SAM9RL_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9RL_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9RL_BASE_PIT 0xfffffd30
|
||||
|
||||
@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data);
|
||||
struct at91_usbh_data {
|
||||
u8 ports; /* number of ports on root hub */
|
||||
int vbus_pin[2]; /* port power-control pin */
|
||||
u8 vbus_pin_inverted;
|
||||
u8 vbus_pin_active_low[2];
|
||||
u8 overcurrent_supported;
|
||||
int overcurrent_pin[2];
|
||||
u8 overcurrent_status[2];
|
||||
|
||||
@ -34,7 +34,6 @@
|
||||
/*
|
||||
* Show the reason for the previous system reset.
|
||||
*/
|
||||
#if defined(AT91_RSTC)
|
||||
|
||||
#include <mach/at91_rstc.h>
|
||||
#include <mach/at91_shdwc.h>
|
||||
@ -58,10 +57,10 @@ static void __init show_reset_status(void)
|
||||
char *reason, *r2 = reset;
|
||||
u32 reset_type, wake_type;
|
||||
|
||||
if (!at91_shdwc_base)
|
||||
if (!at91_shdwc_base || !at91_rstc_base)
|
||||
return;
|
||||
|
||||
reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
|
||||
reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
|
||||
wake_type = at91_shdwc_read(AT91_SHDW_SR);
|
||||
|
||||
switch (reset_type) {
|
||||
@ -102,10 +101,6 @@ static void __init show_reset_status(void)
|
||||
}
|
||||
pr_info("AT91: Starting after %s %s\n", reason, r2);
|
||||
}
|
||||
#else
|
||||
static void __init show_reset_status(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
static int at91_pm_valid_state(suspend_state_t state)
|
||||
{
|
||||
|
||||
@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void)
|
||||
: : "r" (0))
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
#include <mach/at91cap9_ddrsdr.h>
|
||||
#include <mach/at91sam9_ddrsdr.h>
|
||||
|
||||
|
||||
static inline u32 sdram_selfrefresh_enable(void)
|
||||
{
|
||||
u32 saved_lpr, lpr;
|
||||
|
||||
saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
|
||||
saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
|
||||
|
||||
lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
|
||||
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
|
||||
at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
|
||||
return saved_lpr;
|
||||
}
|
||||
|
||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
|
||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
|
||||
#define wait_for_interrupt_enable() cpu_do_idle()
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
|
||||
@ -18,9 +18,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_AT91RM9200)
|
||||
#include <mach/at91rm9200_mc.h>
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
#include <mach/at91cap9_ddrsdr.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#include <mach/at91sam9_ddrsdr.h>
|
||||
#else
|
||||
#include <mach/at91sam9_sdramc.h>
|
||||
|
||||
@ -29,9 +29,12 @@ EXPORT_SYMBOL(at91_soc_initdata);
|
||||
void __init at91rm9200_set_type(int type)
|
||||
{
|
||||
if (type == ARCH_REVISON_9200_PQFP)
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
|
||||
else
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
|
||||
else
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
|
||||
|
||||
pr_info("AT91: filled in soc subtype: %s\n",
|
||||
at91_get_soc_subtype(&at91_soc_initdata));
|
||||
}
|
||||
|
||||
void __init at91_init_irq_default(void)
|
||||
@ -281,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr)
|
||||
pm_power_off = at91sam9_poweroff;
|
||||
}
|
||||
|
||||
void __iomem *at91_rstc_base;
|
||||
|
||||
void __init at91_ioremap_rstc(u32 base_addr)
|
||||
{
|
||||
at91_rstc_base = ioremap(base_addr, 16);
|
||||
if (!at91_rstc_base)
|
||||
panic("Impossible to ioremap at91_rstc_base\n");
|
||||
}
|
||||
|
||||
void __init at91_initialize(unsigned long main_clock)
|
||||
{
|
||||
at91_boot_soc.ioremap_registers();
|
||||
|
||||
@ -139,8 +139,23 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
|
||||
}
|
||||
|
||||
iclk = clk_get(&pdev->dev, "ohci_clk");
|
||||
if (IS_ERR(iclk)) {
|
||||
dev_err(&pdev->dev, "failed to get ohci_clk\n");
|
||||
retval = PTR_ERR(iclk);
|
||||
goto err3;
|
||||
}
|
||||
fclk = clk_get(&pdev->dev, "uhpck");
|
||||
if (IS_ERR(fclk)) {
|
||||
dev_err(&pdev->dev, "failed to get uhpck\n");
|
||||
retval = PTR_ERR(fclk);
|
||||
goto err4;
|
||||
}
|
||||
hclk = clk_get(&pdev->dev, "hclk");
|
||||
if (IS_ERR(hclk)) {
|
||||
dev_err(&pdev->dev, "failed to get hclk\n");
|
||||
retval = PTR_ERR(hclk);
|
||||
goto err5;
|
||||
}
|
||||
|
||||
at91_start_hc(pdev);
|
||||
ohci_hcd_init(hcd_to_ohci(hcd));
|
||||
@ -153,9 +168,12 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
|
||||
at91_stop_hc(pdev);
|
||||
|
||||
clk_put(hclk);
|
||||
err5:
|
||||
clk_put(fclk);
|
||||
err4:
|
||||
clk_put(iclk);
|
||||
|
||||
err3:
|
||||
iounmap(hcd->regs);
|
||||
|
||||
err2:
|
||||
@ -226,7 +244,8 @@ static void ohci_at91_usb_set_power(struct at91_usbh_data *pdata, int port, int
|
||||
if (!gpio_is_valid(pdata->vbus_pin[port]))
|
||||
return;
|
||||
|
||||
gpio_set_value(pdata->vbus_pin[port], !pdata->vbus_pin_inverted ^ enable);
|
||||
gpio_set_value(pdata->vbus_pin[port],
|
||||
!pdata->vbus_pin_active_low[port] ^ enable);
|
||||
}
|
||||
|
||||
static int ohci_at91_usb_get_power(struct at91_usbh_data *pdata, int port)
|
||||
@ -237,7 +256,8 @@ static int ohci_at91_usb_get_power(struct at91_usbh_data *pdata, int port)
|
||||
if (!gpio_is_valid(pdata->vbus_pin[port]))
|
||||
return -EINVAL;
|
||||
|
||||
return gpio_get_value(pdata->vbus_pin[port]) ^ !pdata->vbus_pin_inverted;
|
||||
return gpio_get_value(pdata->vbus_pin[port]) ^
|
||||
!pdata->vbus_pin_active_low[port];
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user