mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 15:43:59 +08:00
drm/radeon/kms: add PLL flag to prefer frequencies <= the target freq
This is needed when using fractional feedback dividers on some IGP chips. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
b995e4330d
commit
d0e275a90a
@ -491,7 +491,11 @@ void radeon_compute_pll(struct radeon_pll *pll,
|
||||
tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
|
||||
current_freq = radeon_div(tmp, ref_div * post_div);
|
||||
|
||||
error = abs(current_freq - freq);
|
||||
if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
|
||||
error = freq - current_freq;
|
||||
error = error < 0 ? 0xffffffff : error;
|
||||
} else
|
||||
error = abs(current_freq - freq);
|
||||
vco_diff = abs(vco - best_vco);
|
||||
|
||||
if ((best_vco == 0 && error < best_error) ||
|
||||
|
@ -124,6 +124,7 @@ struct radeon_tmds_pll {
|
||||
#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
|
||||
#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
|
||||
#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
|
||||
#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
|
||||
|
||||
struct radeon_pll {
|
||||
uint16_t reference_freq;
|
||||
|
Loading…
Reference in New Issue
Block a user