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ARM: EXYNOS: Fixup endian in pm/pmu
Fix the PMU code endian access code to deal with kernels built for big endian operation. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
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@ -174,12 +174,12 @@ extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
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static inline void pmu_raw_writel(u32 val, u32 offset)
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{
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__raw_writel(val, pmu_base_addr + offset);
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writel_relaxed(val, pmu_base_addr + offset);
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}
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static inline u32 pmu_raw_readl(u32 offset)
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{
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return __raw_readl(pmu_base_addr + offset);
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return readl_relaxed(pmu_base_addr + offset);
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}
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#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
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@ -132,9 +132,9 @@ static void exynos_set_wakeupmask(long mask)
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static void exynos_cpu_set_boot_vector(long flags)
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{
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__raw_writel(virt_to_phys(exynos_cpu_resume),
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exynos_boot_vector_addr());
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__raw_writel(flags, exynos_boot_vector_flag());
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writel_relaxed(virt_to_phys(exynos_cpu_resume),
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exynos_boot_vector_addr());
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writel_relaxed(flags, exynos_boot_vector_flag());
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}
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static int exynos_aftr_finisher(unsigned long flags)
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@ -70,12 +70,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
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}
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pwr = power_on ? INT_LOCAL_PWR_EN : 0;
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__raw_writel(pwr, base);
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writel_relaxed(pwr, base);
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/* Wait max 1ms */
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timeout = 10;
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while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
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while ((readl_relaxed(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
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if (!timeout) {
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op = (power_on) ? "enable" : "disable";
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pr_err("Power domain %s %s failed\n", domain->name, op);
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@ -185,7 +185,7 @@ static __init int exynos4_pm_init_power_domain(void)
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clk_put(pd->oscclk);
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no_clk:
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on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
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on = readl_relaxed(pd->base + 0x4) & INT_LOCAL_PWR_EN;
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pm_genpd_init(&pd->pd, NULL, !on);
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of_genpd_add_provider_simple(np, &pd->pd);
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