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ath9k: Configure pll control for AR9485

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Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan 2010-12-06 04:27:44 -08:00 committed by John W. Linville
parent 47c80de62e
commit d09b17f73f
2 changed files with 8 additions and 1 deletions
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7
drivers/net/wireless/ath/ath9k/hw.c
View File

@ -667,7 +667,12 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
static void ath9k_hw_init_pll(struct ath_hw *ah,
struct ath9k_channel *chan)
{
u32 pll = ath9k_hw_compute_pll_control(ah, chan);
u32 pll;
if (AR_SREV_9485(ah))
REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
pll = ath9k_hw_compute_pll_control(ah, chan);
REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);

2
drivers/net/wireless/ath/ath9k/reg.h
View File

@ -1114,6 +1114,8 @@ enum {
#define AR_RTC_PLL_CONTROL \
((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
#define AR_RTC_PLL_CONTROL2 0x703c
#define AR_RTC_PLL_DIV 0x0000001f
#define AR_RTC_PLL_DIV_S 0
#define AR_RTC_PLL_DIV2 0x00000020