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Samsung cleanup for v3.20
- remove i2c sys configuration from mach-exynos/ : all related codes moved into i2c driver - remove Samsung specific DMA : every Samsung stuff uses dmaengine APIs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJUyXM3AAoJEA0Cl+kVi2xqn8MP/jDl9Jgx94dvLoj+jZxrN/QL qm4ZbhWnQ+DCv6B8GSgkwljWTpQazqUztft1FXpjKUW3p2VoQHugb0a62jySx6vG VKCxLsZh95Zj7ZL1q18v1HO7zrAm/TdWl7H+j55jATfQVQGmHeiFTkyHBYVmicHU /HMwT3C42oJEiz58BPs0uoM5Pfm+2cV8J4yj2VMIQXLx5y52+Ic0s228yJxqWYuO Nm7RGMW5oJwkgAli2ug0VqMUYGVg4otiNqoXIl9DP1B+yhdvEsXrkPcDNvTqgJBU nq+ho3X2qFM+ETMi80QA4YNq/MM5Ns3cqwMprVTeAvMe8xJqjL3FpSc3eDQRRhHq LHn0eUhwOj4xWa5d/dku6Onp1UOBSqvuURj30Vg2OXMwwBa/DD5g3sihmvBXUdVa Bd8QEWl9gcVTXqjRb3V2X9UdID3EZMongAohzAqi/ailb8kFmdGPOt7EZsPGa4ZA YkxR/KvcLMEjClwGVDH9x7vJq8rONSi+zWhE3MbBMjyj4quUv4tzMUb2Bl2dkrma lrpberjceQ2gLIRFC8fy5JoL4sNfIT3JcCpLCRMZXK9SbWx7UjdV3Ni8m04ldwJt +Jjoh2qiZ/wsFH++RyJ2K3yrntcGhzqe/wfm1ZB6dGe0W/XRIOb/dq9vBODbX/9W yl99BuYWxUZw9aHPfRp2 =2/ZU -----END PGP SIGNATURE----- Merge tag 'samsung-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup Merge "Samsung cleanup for v3.20" from Kukjin Kim: - remove i2c sys configuration from mach-exynos/ : all related codes moved into i2c driver - remove Samsung specific DMA : every Samsung stuff uses dmaengine APIs * tag 'samsung-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: SAMSUNG: remove unused DMA infrastructure ARM: EXYNOS: Remove i2c sys configuration related code Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
d073d7a146
@ -1,46 +0,0 @@
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S3C2410 DMA
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===========
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Introduction
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------------
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The kernel provides an interface to manage DMA transfers
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using the DMA channels in the CPU, so that the central
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duty of managing channel mappings, and programming the
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channel generators is in one place.
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DMA Channel Ordering
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--------------------
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Many of the range do not have connections for the DMA
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channels to all sources, which means that some devices
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have a restricted number of channels that can be used.
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To allow flexibility for each CPU type and board, the
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DMA code can be given a DMA ordering structure which
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allows the order of channel search to be specified, as
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well as allowing the prohibition of certain claims.
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struct s3c24xx_dma_order has a list of channels, and
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each channel within has a slot for a list of DMA
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channel numbers. The slots are searched in order for
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the presence of a DMA channel number with DMA_CH_VALID
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or-ed in.
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If the order has the flag DMA_CH_NEVER set, then after
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checking the channel list, the system will return no
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found channel, thus denying the request.
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A board support file can call s3c24xx_dma_order_set()
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to register a complete ordering set. The routine will
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copy the data, so the original can be discarded with
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__initdata.
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Authour
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-------
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Ben Dooks,
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Copyright (c) 2007 Ben Dooks, Simtec Electronics
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Licensed under the GPL v2
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@ -27,20 +27,16 @@
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#include <asm/mach/map.h>
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#include <asm/memory.h>
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#include <mach/map.h>
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#include "common.h"
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#include "mfc.h"
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#include "regs-pmu.h"
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#include "regs-sys.h"
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void __iomem *pmu_base_addr;
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
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.length = SZ_4K,
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@ -70,11 +66,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
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static struct map_desc exynos5_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
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.length = SZ_4K,
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@ -213,32 +204,6 @@ static void __init exynos_init_irq(void)
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static void __init exynos_dt_machine_init(void)
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{
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struct device_node *i2c_np;
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const char *i2c_compat = "samsung,s3c2440-i2c";
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unsigned int tmp;
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int id;
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/*
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* Exynos5's legacy i2c controller and new high speed i2c
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* controller have muxed interrupt sources. By default the
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* interrupts for 4-channel HS-I2C controller are enabled.
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* If node for first four channels of legacy i2c controller
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* are available then re-configure the interrupts via the
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* system register.
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*/
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if (soc_is_exynos5()) {
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for_each_compatible_node(i2c_np, NULL, i2c_compat) {
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if (of_device_is_available(i2c_np)) {
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id = of_alias_get_id(i2c_np, "i2c");
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if (id < 4) {
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tmp = readl(EXYNOS5_SYS_I2C_CFG);
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writel(tmp & ~(0x1 << id),
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EXYNOS5_SYS_I2C_CFG);
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}
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}
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}
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}
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/*
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* This is called from smp_prepare_cpus if we've built for SMP, but
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* we still need to set it up for PM and firmware ops if not.
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@ -1,26 +0,0 @@
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/*
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* Copyright (C) 2010 Samsung Electronics Co. Ltd.
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* Jaswinder Singh <jassi.brar@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __MACH_DMA_H
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#define __MACH_DMA_H
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/* This platform uses the common DMA API driver for PL330 */
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#include <plat/dma-pl330.h>
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#endif /* __MACH_DMA_H */
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@ -24,9 +24,6 @@
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS4_PA_SYSCON 0x10010000
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#define EXYNOS5_PA_SYSCON 0x10050100
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#define EXYNOS4_PA_CMU 0x10030000
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#define EXYNOS5_PA_CMU 0x10010000
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@ -23,12 +23,13 @@
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <mach/map.h>
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#include <plat/pm-common.h>
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#include "common.h"
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#include "exynos-pmu.h"
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#include "regs-pmu.h"
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#include "regs-sys.h"
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static inline void __iomem *exynos_boot_vector_addr(void)
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{
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@ -1,22 +0,0 @@
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - system register definition
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_SYS_H
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#define __ASM_ARCH_REGS_SYS_H __FILE__
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#include <mach/map.h>
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#define S5P_SYSREG(x) (S3C_VA_SYS + (x))
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/* For EXYNOS5 */
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#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234)
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#endif /* __ASM_ARCH_REGS_SYS_H */
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@ -34,7 +34,6 @@
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#include "common.h"
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#include "regs-pmu.h"
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#include "regs-sys.h"
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#include "exynos-pmu.h"
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#define S5P_CHECK_SLEEP 0x00000BAD
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@ -53,10 +52,6 @@ struct exynos_wkup_irq {
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u32 mask;
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};
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static struct sleep_save exynos5_sys_save[] = {
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SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
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};
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static struct sleep_save exynos_core_save[] = {
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/* SROM side */
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SAVE_ITEM(S5P_SROM_BW),
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@ -497,8 +492,6 @@ static const struct exynos_pm_data exynos5250_pm_data = {
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.wkup_irq = exynos5250_wkup_irq,
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.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
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.release_ret_regs = exynos_release_ret_regs,
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.extra_save = exynos5_sys_save,
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.num_extra_save = ARRAY_SIZE(exynos5_sys_save),
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.pm_suspend = exynos_pm_suspend,
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.pm_resume = exynos_pm_resume,
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.pm_prepare = exynos_pm_prepare,
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@ -29,7 +29,6 @@ config CPU_S3C2410
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default y
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select CPU_ARM920T
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select S3C2410_COMMON_CLK
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select S3C2410_DMA if S3C24XX_DMA
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select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
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select S3C2410_PM if PM
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help
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@ -40,7 +39,6 @@ config CPU_S3C2412
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bool "SAMSUNG S3C2412"
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select CPU_ARM926T
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select S3C2412_COMMON_CLK
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select S3C2412_DMA if S3C24XX_DMA
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select S3C2412_PM if PM
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help
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Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
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@ -50,7 +48,6 @@ config CPU_S3C2416
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select CPU_ARM926T
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select S3C2416_PM if PM
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select S3C2443_COMMON_CLK
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select S3C2443_DMA if S3C24XX_DMA
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help
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Support for the S3C2416 SoC from the S3C24XX line
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@ -59,7 +56,6 @@ config CPU_S3C2440
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select CPU_ARM920T
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select S3C2410_COMMON_CLK
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select S3C2410_PM if PM
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select S3C2440_DMA if S3C24XX_DMA
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help
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Support for S3C2440 Samsung Mobile CPU based systems.
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@ -67,7 +63,6 @@ config CPU_S3C2442
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bool "SAMSUNG S3C2442"
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select CPU_ARM920T
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select S3C2410_COMMON_CLK
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select S3C2410_DMA if S3C24XX_DMA
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select S3C2410_PM if PM
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help
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Support for S3C2442 Samsung Mobile CPU based systems.
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@ -80,7 +75,6 @@ config CPU_S3C2443
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bool "SAMSUNG S3C2443"
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select CPU_ARM920T
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select S3C2443_COMMON_CLK
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select S3C2443_DMA if S3C24XX_DMA
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help
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Support for the S3C2443 SoC from the S3C24XX line
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@ -114,27 +108,6 @@ config S3C24XX_SETUP_TS
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help
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Compile in platform device definition for Samsung TouchScreen.
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config S3C24XX_DMA
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bool "S3C2410 DMA support (deprecated)"
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select S3C_DMA
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help
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S3C2410 DMA support. This is needed for drivers like sound which
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use the S3C2410's DMA system to move data to and from the
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peripheral blocks.
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config S3C2410_DMA_DEBUG
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bool "S3C2410 DMA support debug"
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depends on S3C2410_DMA
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help
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Enable debugging output for the DMA code. This option sends info
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to the kernel log, at priority KERN_DEBUG.
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config S3C2410_DMA
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bool
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depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
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help
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DMA device selection for S3C2410 and compatible CPUs
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config S3C2410_PM
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bool
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help
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@ -325,11 +298,6 @@ config CPU_S3C2412_ONLY
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!CPU_S3C2442 && !CPU_S3C2443
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default y
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config S3C2412_DMA
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bool
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help
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Internal config node for S3C2412 DMA support
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config S3C2412_PM
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bool
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select S3C2412_PM_SLEEP
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@ -438,11 +406,6 @@ endif # CPU_S3C2416
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if CPU_S3C2440
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config S3C2440_DMA
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bool
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help
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Support for S3C2440 specific DMA code5A
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config S3C2440_XTAL_12000000
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bool
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help
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@ -601,11 +564,6 @@ endif # CPU_S3C2442
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if CPU_S3C2443 || CPU_S3C2416
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config S3C2443_DMA
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bool
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help
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Internal config node for S3C2443 DMA support
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config S3C2443_SETUP_SPI
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bool
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help
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@ -12,12 +12,10 @@
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obj-y += common.o
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obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
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obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o
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obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
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obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
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obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
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obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
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obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
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obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
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@ -27,7 +25,6 @@ obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
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obj-$(CONFIG_CPU_S3C2440) += s3c2440.o
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obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
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obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
|
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obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o
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obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
|
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obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
|
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|
||||
@ -39,15 +36,11 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
|
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|
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# common code
|
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|
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obj-$(CONFIG_S3C24XX_DMA) += dma.o
|
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|
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obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
|
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|
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obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
|
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obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
|
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|
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obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
|
||||
|
||||
#
|
||||
# machine support
|
||||
# following is ordered alphabetically by option text.
|
||||
|
||||
@ -1,182 +0,0 @@
|
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/* linux/arch/arm/mach-s3c2410/dma.c
|
||||
*
|
||||
* Copyright (c) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2410 DMA selection
|
||||
*
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/serial_s3c.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/dma-s3c24xx.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
|
||||
[DMACH_XD0] = {
|
||||
.name = "xdreq0",
|
||||
.channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_XD1] = {
|
||||
.name = "xdreq1",
|
||||
.channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_SDI] = {
|
||||
.name = "sdi",
|
||||
.channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
|
||||
.channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_SPI0] = {
|
||||
.name = "spi0",
|
||||
.channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_SPI1] = {
|
||||
.name = "spi1",
|
||||
.channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_UART0] = {
|
||||
.name = "uart0",
|
||||
.channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_UART1] = {
|
||||
.name = "uart1",
|
||||
.channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_UART2] = {
|
||||
.name = "uart2",
|
||||
.channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_TIMER] = {
|
||||
.name = "timer",
|
||||
.channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
|
||||
.channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_I2S_IN] = {
|
||||
.name = "i2s-sdi",
|
||||
.channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_I2S_OUT] = {
|
||||
.name = "i2s-sdo",
|
||||
.channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_USB_EP1] = {
|
||||
.name = "usb-ep1",
|
||||
.channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_USB_EP2] = {
|
||||
.name = "usb-ep2",
|
||||
.channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_USB_EP3] = {
|
||||
.name = "usb-ep3",
|
||||
.channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_USB_EP4] = {
|
||||
.name = "usb-ep4",
|
||||
.channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
|
||||
},
|
||||
};
|
||||
|
||||
static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
|
||||
struct s3c24xx_dma_map *map)
|
||||
{
|
||||
chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
|
||||
}
|
||||
|
||||
static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
|
||||
.select = s3c2410_dma_select,
|
||||
.dcon_mask = 7 << 24,
|
||||
.map = s3c2410_dma_mappings,
|
||||
.map_size = ARRAY_SIZE(s3c2410_dma_mappings),
|
||||
};
|
||||
|
||||
static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
|
||||
.channels = {
|
||||
[DMACH_SDI] = {
|
||||
.list = {
|
||||
[0] = 3 | DMA_CH_VALID,
|
||||
[1] = 2 | DMA_CH_VALID,
|
||||
[2] = 0 | DMA_CH_VALID,
|
||||
},
|
||||
},
|
||||
[DMACH_I2S_IN] = {
|
||||
.list = {
|
||||
[0] = 1 | DMA_CH_VALID,
|
||||
[1] = 2 | DMA_CH_VALID,
|
||||
},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static int __init s3c2410_dma_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
s3c2410_dma_init();
|
||||
s3c24xx_dma_order_set(&s3c2410_dma_order);
|
||||
return s3c24xx_dma_init_map(&s3c2410_dma_sel);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2410)
|
||||
static struct subsys_interface s3c2410_dma_interface = {
|
||||
.name = "s3c2410_dma",
|
||||
.subsys = &s3c2410_subsys,
|
||||
.add_dev = s3c2410_dma_add,
|
||||
};
|
||||
|
||||
static int __init s3c2410_dma_drvinit(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2410_dma_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410_dma_drvinit);
|
||||
|
||||
static struct subsys_interface s3c2410a_dma_interface = {
|
||||
.name = "s3c2410a_dma",
|
||||
.subsys = &s3c2410a_subsys,
|
||||
.add_dev = s3c2410_dma_add,
|
||||
};
|
||||
|
||||
static int __init s3c2410a_dma_drvinit(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2410a_dma_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410a_dma_drvinit);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2442)
|
||||
/* S3C2442 DMA contains the same selection table as the S3C2410 */
|
||||
static struct subsys_interface s3c2442_dma_interface = {
|
||||
.name = "s3c2442_dma",
|
||||
.subsys = &s3c2442_subsys,
|
||||
.add_dev = s3c2410_dma_add,
|
||||
};
|
||||
|
||||
static int __init s3c2442_dma_drvinit(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2442_dma_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2442_dma_drvinit);
|
||||
#endif
|
||||
|
||||
@ -1,150 +0,0 @@
|
||||
/* linux/arch/arm/mach-s3c2412/dma.c
|
||||
*
|
||||
* Copyright (c) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2412 DMA selection
|
||||
*
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/serial_s3c.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <plat/dma-s3c24xx.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
|
||||
|
||||
static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
|
||||
[DMACH_XD0] = {
|
||||
.name = "xdreq0",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
|
||||
},
|
||||
[DMACH_XD1] = {
|
||||
.name = "xdreq1",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
|
||||
},
|
||||
[DMACH_SDI] = {
|
||||
.name = "sdi",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_SDI),
|
||||
},
|
||||
[DMACH_SPI0_RX] = {
|
||||
.name = "spi0-rx",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_SPI0RX),
|
||||
},
|
||||
[DMACH_SPI0_TX] = {
|
||||
.name = "spi0-tx",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
|
||||
},
|
||||
[DMACH_SPI1_RX] = {
|
||||
.name = "spi1-rx",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_SPI1RX),
|
||||
},
|
||||
[DMACH_SPI1_TX] = {
|
||||
.name = "spi1-tx",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
|
||||
},
|
||||
[DMACH_UART0] = {
|
||||
.name = "uart0",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART0_0),
|
||||
},
|
||||
[DMACH_UART1] = {
|
||||
.name = "uart1",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART1_0),
|
||||
},
|
||||
[DMACH_UART2] = {
|
||||
.name = "uart2",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART2_0),
|
||||
},
|
||||
[DMACH_UART0_SRC2] = {
|
||||
.name = "uart0",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART0_1),
|
||||
},
|
||||
[DMACH_UART1_SRC2] = {
|
||||
.name = "uart1",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART1_1),
|
||||
},
|
||||
[DMACH_UART2_SRC2] = {
|
||||
.name = "uart2",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART2_1),
|
||||
},
|
||||
[DMACH_TIMER] = {
|
||||
.name = "timer",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_TIMER),
|
||||
},
|
||||
[DMACH_I2S_IN] = {
|
||||
.name = "i2s-sdi",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_I2SRX),
|
||||
},
|
||||
[DMACH_I2S_OUT] = {
|
||||
.name = "i2s-sdo",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_I2STX),
|
||||
},
|
||||
[DMACH_USB_EP1] = {
|
||||
.name = "usb-ep1",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_USBEP1),
|
||||
},
|
||||
[DMACH_USB_EP2] = {
|
||||
.name = "usb-ep2",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_USBEP2),
|
||||
},
|
||||
[DMACH_USB_EP3] = {
|
||||
.name = "usb-ep3",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_USBEP3),
|
||||
},
|
||||
[DMACH_USB_EP4] = {
|
||||
.name = "usb-ep4",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_USBEP4),
|
||||
},
|
||||
};
|
||||
|
||||
static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
|
||||
struct s3c24xx_dma_map *map)
|
||||
{
|
||||
unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
|
||||
writel(chsel | S3C2412_DMAREQSEL_HW,
|
||||
chan->regs + S3C2412_DMA_DMAREQSEL);
|
||||
}
|
||||
|
||||
static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
|
||||
.select = s3c2412_dma_select,
|
||||
.dcon_mask = 0,
|
||||
.map = s3c2412_dma_mappings,
|
||||
.map_size = ARRAY_SIZE(s3c2412_dma_mappings),
|
||||
};
|
||||
|
||||
static int __init s3c2412_dma_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
s3c2410_dma_init();
|
||||
return s3c24xx_dma_init_map(&s3c2412_dma_sel);
|
||||
}
|
||||
|
||||
static struct subsys_interface s3c2412_dma_interface = {
|
||||
.name = "s3c2412_dma",
|
||||
.subsys = &s3c2412_subsys,
|
||||
.add_dev = s3c2412_dma_add,
|
||||
};
|
||||
|
||||
static int __init s3c2412_dma_init(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2412_dma_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2412_dma_init);
|
||||
@ -1,193 +0,0 @@
|
||||
/* linux/arch/arm/mach-s3c2440/dma.c
|
||||
*
|
||||
* Copyright (c) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2440 DMA selection
|
||||
*
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/serial_s3c.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <plat/dma-s3c24xx.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
|
||||
[DMACH_XD0] = {
|
||||
.name = "xdreq0",
|
||||
.channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_XD1] = {
|
||||
.name = "xdreq1",
|
||||
.channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_SDI] = {
|
||||
.name = "sdi",
|
||||
.channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
|
||||
.channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
|
||||
.channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_SPI0] = {
|
||||
.name = "spi0",
|
||||
.channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_SPI1] = {
|
||||
.name = "spi1",
|
||||
.channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_UART0] = {
|
||||
.name = "uart0",
|
||||
.channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_UART1] = {
|
||||
.name = "uart1",
|
||||
.channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_UART2] = {
|
||||
.name = "uart2",
|
||||
.channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_TIMER] = {
|
||||
.name = "timer",
|
||||
.channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
|
||||
.channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_I2S_IN] = {
|
||||
.name = "i2s-sdi",
|
||||
.channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_I2S_OUT] = {
|
||||
.name = "i2s-sdo",
|
||||
.channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_PCM_IN] = {
|
||||
.name = "pcm-in",
|
||||
.channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
|
||||
.channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_PCM_OUT] = {
|
||||
.name = "pcm-out",
|
||||
.channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
|
||||
.channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_MIC_IN] = {
|
||||
.name = "mic-in",
|
||||
.channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
|
||||
.channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_USB_EP1] = {
|
||||
.name = "usb-ep1",
|
||||
.channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_USB_EP2] = {
|
||||
.name = "usb-ep2",
|
||||
.channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_USB_EP3] = {
|
||||
.name = "usb-ep3",
|
||||
.channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
|
||||
},
|
||||
[DMACH_USB_EP4] = {
|
||||
.name = "usb-ep4",
|
||||
.channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
|
||||
},
|
||||
};
|
||||
|
||||
static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
|
||||
struct s3c24xx_dma_map *map)
|
||||
{
|
||||
chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
|
||||
}
|
||||
|
||||
static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
|
||||
.select = s3c2440_dma_select,
|
||||
.dcon_mask = 7 << 24,
|
||||
.map = s3c2440_dma_mappings,
|
||||
.map_size = ARRAY_SIZE(s3c2440_dma_mappings),
|
||||
};
|
||||
|
||||
static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
|
||||
.channels = {
|
||||
[DMACH_SDI] = {
|
||||
.list = {
|
||||
[0] = 3 | DMA_CH_VALID,
|
||||
[1] = 2 | DMA_CH_VALID,
|
||||
[2] = 1 | DMA_CH_VALID,
|
||||
[3] = 0 | DMA_CH_VALID,
|
||||
},
|
||||
},
|
||||
[DMACH_I2S_IN] = {
|
||||
.list = {
|
||||
[0] = 1 | DMA_CH_VALID,
|
||||
[1] = 2 | DMA_CH_VALID,
|
||||
},
|
||||
},
|
||||
[DMACH_I2S_OUT] = {
|
||||
.list = {
|
||||
[0] = 2 | DMA_CH_VALID,
|
||||
[1] = 1 | DMA_CH_VALID,
|
||||
},
|
||||
},
|
||||
[DMACH_PCM_IN] = {
|
||||
.list = {
|
||||
[0] = 2 | DMA_CH_VALID,
|
||||
[1] = 1 | DMA_CH_VALID,
|
||||
},
|
||||
},
|
||||
[DMACH_PCM_OUT] = {
|
||||
.list = {
|
||||
[0] = 1 | DMA_CH_VALID,
|
||||
[1] = 3 | DMA_CH_VALID,
|
||||
},
|
||||
},
|
||||
[DMACH_MIC_IN] = {
|
||||
.list = {
|
||||
[0] = 3 | DMA_CH_VALID,
|
||||
[1] = 2 | DMA_CH_VALID,
|
||||
},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static int __init s3c2440_dma_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
s3c2410_dma_init();
|
||||
s3c24xx_dma_order_set(&s3c2440_dma_order);
|
||||
return s3c24xx_dma_init_map(&s3c2440_dma_sel);
|
||||
}
|
||||
|
||||
static struct subsys_interface s3c2440_dma_interface = {
|
||||
.name = "s3c2440_dma",
|
||||
.subsys = &s3c2440_subsys,
|
||||
.add_dev = s3c2440_dma_add,
|
||||
};
|
||||
|
||||
static int __init s3c2440_dma_init(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2440_dma_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2440_dma_init);
|
||||
|
||||
@ -1,179 +0,0 @@
|
||||
/* linux/arch/arm/mach-s3c2443/dma.c
|
||||
*
|
||||
* Copyright (c) 2007 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2443 DMA selection
|
||||
*
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/serial_s3c.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <plat/dma-s3c24xx.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
#define MAP(x) { \
|
||||
[0] = (x) | DMA_CH_VALID, \
|
||||
[1] = (x) | DMA_CH_VALID, \
|
||||
[2] = (x) | DMA_CH_VALID, \
|
||||
[3] = (x) | DMA_CH_VALID, \
|
||||
[4] = (x) | DMA_CH_VALID, \
|
||||
[5] = (x) | DMA_CH_VALID, \
|
||||
}
|
||||
|
||||
static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
|
||||
[DMACH_XD0] = {
|
||||
.name = "xdreq0",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
|
||||
},
|
||||
[DMACH_XD1] = {
|
||||
.name = "xdreq1",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
|
||||
},
|
||||
[DMACH_SDI] = { /* only on S3C2443 */
|
||||
.name = "sdi",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_SDI),
|
||||
},
|
||||
[DMACH_SPI0_RX] = {
|
||||
.name = "spi0-rx",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
|
||||
},
|
||||
[DMACH_SPI0_TX] = {
|
||||
.name = "spi0-tx",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
|
||||
},
|
||||
[DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
|
||||
.name = "spi1-rx",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
|
||||
},
|
||||
[DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
|
||||
.name = "spi1-tx",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
|
||||
},
|
||||
[DMACH_UART0] = {
|
||||
.name = "uart0",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART0_0),
|
||||
},
|
||||
[DMACH_UART1] = {
|
||||
.name = "uart1",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART1_0),
|
||||
},
|
||||
[DMACH_UART2] = {
|
||||
.name = "uart2",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART2_0),
|
||||
},
|
||||
[DMACH_UART3] = {
|
||||
.name = "uart3",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART3_0),
|
||||
},
|
||||
[DMACH_UART0_SRC2] = {
|
||||
.name = "uart0",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART0_1),
|
||||
},
|
||||
[DMACH_UART1_SRC2] = {
|
||||
.name = "uart1",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART1_1),
|
||||
},
|
||||
[DMACH_UART2_SRC2] = {
|
||||
.name = "uart2",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART2_1),
|
||||
},
|
||||
[DMACH_UART3_SRC2] = {
|
||||
.name = "uart3",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART3_1),
|
||||
},
|
||||
[DMACH_TIMER] = {
|
||||
.name = "timer",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_TIMER),
|
||||
},
|
||||
[DMACH_I2S_IN] = {
|
||||
.name = "i2s-sdi",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_I2SRX),
|
||||
},
|
||||
[DMACH_I2S_OUT] = {
|
||||
.name = "i2s-sdo",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_I2STX),
|
||||
},
|
||||
[DMACH_PCM_IN] = {
|
||||
.name = "pcm-in",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_PCMIN),
|
||||
},
|
||||
[DMACH_PCM_OUT] = {
|
||||
.name = "pcm-out",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
|
||||
},
|
||||
[DMACH_MIC_IN] = {
|
||||
.name = "mic-in",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_MICIN),
|
||||
},
|
||||
};
|
||||
|
||||
static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
|
||||
struct s3c24xx_dma_map *map)
|
||||
{
|
||||
unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
|
||||
writel(chsel | S3C2443_DMAREQSEL_HW,
|
||||
chan->regs + S3C2443_DMA_DMAREQSEL);
|
||||
}
|
||||
|
||||
static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
|
||||
.select = s3c2443_dma_select,
|
||||
.dcon_mask = 0,
|
||||
.map = s3c2443_dma_mappings,
|
||||
.map_size = ARRAY_SIZE(s3c2443_dma_mappings),
|
||||
};
|
||||
|
||||
static int __init s3c2443_dma_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
|
||||
return s3c24xx_dma_init_map(&s3c2443_dma_sel);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2416
|
||||
/* S3C2416 DMA contains the same selection table as the S3C2443 */
|
||||
static struct subsys_interface s3c2416_dma_interface = {
|
||||
.name = "s3c2416_dma",
|
||||
.subsys = &s3c2416_subsys,
|
||||
.add_dev = s3c2443_dma_add,
|
||||
};
|
||||
|
||||
static int __init s3c2416_dma_init(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2416_dma_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2416_dma_init);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2443
|
||||
static struct subsys_interface s3c2443_dma_interface = {
|
||||
.name = "s3c2443_dma",
|
||||
.subsys = &s3c2443_subsys,
|
||||
.add_dev = s3c2443_dma_add,
|
||||
};
|
||||
|
||||
static int __init s3c2443_dma_init(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2443_dma_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2443_dma_init);
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -15,8 +15,6 @@
|
||||
|
||||
#include <linux/device.h>
|
||||
|
||||
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
|
||||
|
||||
/* We use `virtual` dma channels to hide the fact we have only a limited
|
||||
* number of DMA channels, and not of all of them (dependent on the device)
|
||||
* can be attached to any DMA source. We therefore let the DMA core handle
|
||||
@ -54,161 +52,4 @@ enum dma_ch {
|
||||
DMACH_MAX, /* the end entry */
|
||||
};
|
||||
|
||||
static inline bool samsung_dma_has_circular(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool samsung_dma_is_dmadev(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#include <plat/dma.h>
|
||||
|
||||
#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
|
||||
|
||||
/* we have 4 dma channels */
|
||||
#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
|
||||
#define S3C_DMA_CHANNELS (4)
|
||||
#else
|
||||
#define S3C_DMA_CHANNELS (6)
|
||||
#endif
|
||||
|
||||
/* types */
|
||||
|
||||
enum s3c2410_dma_state {
|
||||
S3C2410_DMA_IDLE,
|
||||
S3C2410_DMA_RUNNING,
|
||||
S3C2410_DMA_PAUSED
|
||||
};
|
||||
|
||||
/* enum s3c2410_dma_loadst
|
||||
*
|
||||
* This represents the state of the DMA engine, wrt to the loaded / running
|
||||
* transfers. Since we don't have any way of knowing exactly the state of
|
||||
* the DMA transfers, we need to know the state to make decisions on whether
|
||||
* we can
|
||||
*
|
||||
* S3C2410_DMA_NONE
|
||||
*
|
||||
* There are no buffers loaded (the channel should be inactive)
|
||||
*
|
||||
* S3C2410_DMA_1LOADED
|
||||
*
|
||||
* There is one buffer loaded, however it has not been confirmed to be
|
||||
* loaded by the DMA engine. This may be because the channel is not
|
||||
* yet running, or the DMA driver decided that it was too costly to
|
||||
* sit and wait for it to happen.
|
||||
*
|
||||
* S3C2410_DMA_1RUNNING
|
||||
*
|
||||
* The buffer has been confirmed running, and not finisged
|
||||
*
|
||||
* S3C2410_DMA_1LOADED_1RUNNING
|
||||
*
|
||||
* There is a buffer waiting to be loaded by the DMA engine, and one
|
||||
* currently running.
|
||||
*/
|
||||
|
||||
enum s3c2410_dma_loadst {
|
||||
S3C2410_DMALOAD_NONE,
|
||||
S3C2410_DMALOAD_1LOADED,
|
||||
S3C2410_DMALOAD_1RUNNING,
|
||||
S3C2410_DMALOAD_1LOADED_1RUNNING,
|
||||
};
|
||||
|
||||
|
||||
/* flags */
|
||||
|
||||
#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
|
||||
* waiting for reloads */
|
||||
#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
|
||||
|
||||
#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
|
||||
|
||||
/* dma buffer */
|
||||
|
||||
struct s3c2410_dma_buf;
|
||||
|
||||
/* s3c2410_dma_buf
|
||||
*
|
||||
* internally used buffer structure to describe a queued or running
|
||||
* buffer.
|
||||
*/
|
||||
|
||||
struct s3c2410_dma_buf {
|
||||
struct s3c2410_dma_buf *next;
|
||||
int magic; /* magic */
|
||||
int size; /* buffer size in bytes */
|
||||
dma_addr_t data; /* start of DMA data */
|
||||
dma_addr_t ptr; /* where the DMA got to [1] */
|
||||
void *id; /* client's id */
|
||||
};
|
||||
|
||||
/* [1] is this updated for both recv/send modes? */
|
||||
|
||||
struct s3c2410_dma_stats {
|
||||
unsigned long loads;
|
||||
unsigned long timeout_longest;
|
||||
unsigned long timeout_shortest;
|
||||
unsigned long timeout_avg;
|
||||
unsigned long timeout_failed;
|
||||
};
|
||||
|
||||
struct s3c2410_dma_map;
|
||||
|
||||
/* struct s3c2410_dma_chan
|
||||
*
|
||||
* full state information for each DMA channel
|
||||
*/
|
||||
|
||||
struct s3c2410_dma_chan {
|
||||
/* channel state flags and information */
|
||||
unsigned char number; /* number of this dma channel */
|
||||
unsigned char in_use; /* channel allocated */
|
||||
unsigned char irq_claimed; /* irq claimed for channel */
|
||||
unsigned char irq_enabled; /* irq enabled for channel */
|
||||
unsigned char xfer_unit; /* size of an transfer */
|
||||
|
||||
/* channel state */
|
||||
|
||||
enum s3c2410_dma_state state;
|
||||
enum s3c2410_dma_loadst load_state;
|
||||
struct s3c2410_dma_client *client;
|
||||
|
||||
/* channel configuration */
|
||||
enum dma_data_direction source;
|
||||
enum dma_ch req_ch;
|
||||
unsigned long dev_addr;
|
||||
unsigned long load_timeout;
|
||||
unsigned int flags; /* channel flags */
|
||||
|
||||
struct s3c24xx_dma_map *map; /* channel hw maps */
|
||||
|
||||
/* channel's hardware position and configuration */
|
||||
void __iomem *regs; /* channels registers */
|
||||
void __iomem *addr_reg; /* data address register */
|
||||
unsigned int irq; /* channel irq */
|
||||
unsigned long dcon; /* default value of DCON */
|
||||
|
||||
/* driver handles */
|
||||
s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
|
||||
s3c2410_dma_opfn_t op_fn; /* channel op callback */
|
||||
|
||||
/* stats gathering */
|
||||
struct s3c2410_dma_stats *stats;
|
||||
struct s3c2410_dma_stats stats_store;
|
||||
|
||||
/* buffer list and information */
|
||||
struct s3c2410_dma_buf *curr; /* current dma buffer */
|
||||
struct s3c2410_dma_buf *next; /* next buffer to load */
|
||||
struct s3c2410_dma_buf *end; /* end of queue */
|
||||
|
||||
/* system device */
|
||||
struct device dev;
|
||||
};
|
||||
|
||||
typedef unsigned long dma_device_t;
|
||||
|
||||
#endif /* __ASM_ARCH_DMA_H */
|
||||
|
||||
@ -51,21 +51,6 @@ enum dma_ch {
|
||||
DMACH_MAX = 32
|
||||
};
|
||||
|
||||
struct s3c2410_dma_client {
|
||||
char *name;
|
||||
};
|
||||
|
||||
static inline bool samsung_dma_has_circular(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool samsung_dma_is_dmadev(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <plat/dma-ops.h>
|
||||
|
||||
#endif /* __ASM_ARCH_IRQ_H */
|
||||
|
||||
@ -236,13 +236,6 @@ config S3C_SETUP_CAMIF
|
||||
help
|
||||
Compile in common setup code for S3C CAMIF devices
|
||||
|
||||
# DMA
|
||||
|
||||
config S3C_DMA
|
||||
bool
|
||||
help
|
||||
Internal configuration for S3C DMA core
|
||||
|
||||
config SAMSUNG_PM_GPIO
|
||||
bool
|
||||
default y if GPIO_SAMSUNG && PM
|
||||
@ -250,14 +243,6 @@ config SAMSUNG_PM_GPIO
|
||||
Include legacy GPIO power management code for platforms not using
|
||||
pinctrl-samsung driver.
|
||||
|
||||
config SAMSUNG_DMADEV
|
||||
bool "Use legacy Samsung DMA abstraction"
|
||||
depends on CPU_S5PV210 || ARCH_S3C64XX
|
||||
select DMADEVICES
|
||||
default y
|
||||
help
|
||||
Use DMA device engine for PL330 DMAC.
|
||||
|
||||
endif
|
||||
|
||||
config S5P_DEV_MFC
|
||||
|
||||
@ -26,12 +26,6 @@ obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
|
||||
|
||||
obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o
|
||||
|
||||
# DMA support
|
||||
|
||||
obj-$(CONFIG_S3C_DMA) += dma.o s3c-dma-ops.o
|
||||
|
||||
obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o
|
||||
|
||||
# PM support
|
||||
|
||||
obj-$(CONFIG_PM_SLEEP) += pm-common.o
|
||||
|
||||
@ -1,146 +0,0 @@
|
||||
/* linux/arch/arm/plat-samsung/dma-ops.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Samsung DMA Operations
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/amba/pl330.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#if defined(CONFIG_PL330_DMA)
|
||||
#define dma_filter pl330_filter
|
||||
#elif defined(CONFIG_S3C64XX_PL080)
|
||||
#define dma_filter pl08x_filter_id
|
||||
#endif
|
||||
|
||||
static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
|
||||
struct samsung_dma_req *param,
|
||||
struct device *dev, char *ch_name)
|
||||
{
|
||||
dma_cap_mask_t mask;
|
||||
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(param->cap, mask);
|
||||
|
||||
if (dev->of_node)
|
||||
return (unsigned)dma_request_slave_channel(dev, ch_name);
|
||||
else
|
||||
return (unsigned)dma_request_channel(mask, dma_filter,
|
||||
(void *)dma_ch);
|
||||
}
|
||||
|
||||
static int samsung_dmadev_release(unsigned ch, void *param)
|
||||
{
|
||||
dma_release_channel((struct dma_chan *)ch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int samsung_dmadev_config(unsigned ch,
|
||||
struct samsung_dma_config *param)
|
||||
{
|
||||
struct dma_chan *chan = (struct dma_chan *)ch;
|
||||
struct dma_slave_config slave_config;
|
||||
|
||||
if (param->direction == DMA_DEV_TO_MEM) {
|
||||
memset(&slave_config, 0, sizeof(struct dma_slave_config));
|
||||
slave_config.direction = param->direction;
|
||||
slave_config.src_addr = param->fifo;
|
||||
slave_config.src_addr_width = param->width;
|
||||
slave_config.src_maxburst = 1;
|
||||
dmaengine_slave_config(chan, &slave_config);
|
||||
} else if (param->direction == DMA_MEM_TO_DEV) {
|
||||
memset(&slave_config, 0, sizeof(struct dma_slave_config));
|
||||
slave_config.direction = param->direction;
|
||||
slave_config.dst_addr = param->fifo;
|
||||
slave_config.dst_addr_width = param->width;
|
||||
slave_config.dst_maxburst = 1;
|
||||
dmaengine_slave_config(chan, &slave_config);
|
||||
} else {
|
||||
pr_warn("unsupported direction\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int samsung_dmadev_prepare(unsigned ch,
|
||||
struct samsung_dma_prep *param)
|
||||
{
|
||||
struct scatterlist sg;
|
||||
struct dma_chan *chan = (struct dma_chan *)ch;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
|
||||
switch (param->cap) {
|
||||
case DMA_SLAVE:
|
||||
sg_init_table(&sg, 1);
|
||||
sg_dma_len(&sg) = param->len;
|
||||
sg_set_page(&sg, pfn_to_page(PFN_DOWN(param->buf)),
|
||||
param->len, offset_in_page(param->buf));
|
||||
sg_dma_address(&sg) = param->buf;
|
||||
|
||||
desc = dmaengine_prep_slave_sg(chan,
|
||||
&sg, 1, param->direction, DMA_PREP_INTERRUPT);
|
||||
break;
|
||||
case DMA_CYCLIC:
|
||||
desc = dmaengine_prep_dma_cyclic(chan, param->buf,
|
||||
param->len, param->period, param->direction,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
break;
|
||||
default:
|
||||
dev_err(&chan->dev->device, "unsupported format\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (!desc) {
|
||||
dev_err(&chan->dev->device, "cannot prepare cyclic dma\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
desc->callback = param->fp;
|
||||
desc->callback_param = param->fp_param;
|
||||
|
||||
dmaengine_submit((struct dma_async_tx_descriptor *)desc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int samsung_dmadev_trigger(unsigned ch)
|
||||
{
|
||||
dma_async_issue_pending((struct dma_chan *)ch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int samsung_dmadev_flush(unsigned ch)
|
||||
{
|
||||
return dmaengine_terminate_all((struct dma_chan *)ch);
|
||||
}
|
||||
|
||||
static struct samsung_dma_ops dmadev_ops = {
|
||||
.request = samsung_dmadev_request,
|
||||
.release = samsung_dmadev_release,
|
||||
.config = samsung_dmadev_config,
|
||||
.prepare = samsung_dmadev_prepare,
|
||||
.trigger = samsung_dmadev_trigger,
|
||||
.started = NULL,
|
||||
.flush = samsung_dmadev_flush,
|
||||
.stop = samsung_dmadev_flush,
|
||||
};
|
||||
|
||||
void *samsung_dmadev_get_ops(void)
|
||||
{
|
||||
return &dmadev_ops;
|
||||
}
|
||||
EXPORT_SYMBOL(samsung_dmadev_get_ops);
|
||||
@ -1,84 +0,0 @@
|
||||
/* linux/arch/arm/plat-samsung/dma.c
|
||||
*
|
||||
* Copyright (c) 2003-2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C DMA core
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
struct s3c2410_dma_buf;
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/* dma channel state information */
|
||||
struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
|
||||
struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
|
||||
|
||||
/* s3c_dma_lookup_channel
|
||||
*
|
||||
* change the dma channel number given into a real dma channel id
|
||||
*/
|
||||
|
||||
struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
|
||||
{
|
||||
if (channel & DMACH_LOW_LEVEL)
|
||||
return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
|
||||
else
|
||||
return s3c_dma_chan_map[channel];
|
||||
}
|
||||
|
||||
/* do we need to protect the settings of the fields from
|
||||
* irq?
|
||||
*/
|
||||
|
||||
int s3c2410_dma_set_opfn(enum dma_ch channel, s3c2410_dma_opfn_t rtn)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
|
||||
|
||||
chan->op_fn = rtn;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_set_opfn);
|
||||
|
||||
int s3c2410_dma_set_buffdone_fn(enum dma_ch channel, s3c2410_dma_cbfn_t rtn)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
|
||||
|
||||
chan->callback_fn = rtn;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
|
||||
|
||||
int s3c2410_dma_setflags(enum dma_ch channel, unsigned int flags)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
chan->flags = flags;
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_setflags);
|
||||
@ -1,22 +0,0 @@
|
||||
/* arch/arm/plat-s3c/include/plat/dma.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* Samsung S3C DMA core support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
|
||||
|
||||
extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
|
||||
|
||||
/* the currently allocated channel information */
|
||||
extern struct s3c2410_dma_chan s3c2410_chans[];
|
||||
|
||||
|
||||
@ -1,69 +0,0 @@
|
||||
/* arch/arm/plat-samsung/include/plat/dma-ops.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Samsung DMA support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_DMA_OPS_H_
|
||||
#define __SAMSUNG_DMA_OPS_H_ __FILE__
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
struct samsung_dma_req {
|
||||
enum dma_transaction_type cap;
|
||||
struct s3c2410_dma_client *client;
|
||||
};
|
||||
|
||||
struct samsung_dma_prep {
|
||||
enum dma_transaction_type cap;
|
||||
enum dma_transfer_direction direction;
|
||||
dma_addr_t buf;
|
||||
unsigned long period;
|
||||
unsigned long len;
|
||||
void (*fp)(void *data);
|
||||
void *fp_param;
|
||||
};
|
||||
|
||||
struct samsung_dma_config {
|
||||
enum dma_transfer_direction direction;
|
||||
enum dma_slave_buswidth width;
|
||||
dma_addr_t fifo;
|
||||
};
|
||||
|
||||
struct samsung_dma_ops {
|
||||
unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param,
|
||||
struct device *dev, char *ch_name);
|
||||
int (*release)(unsigned ch, void *param);
|
||||
int (*config)(unsigned ch, struct samsung_dma_config *param);
|
||||
int (*prepare)(unsigned ch, struct samsung_dma_prep *param);
|
||||
int (*trigger)(unsigned ch);
|
||||
int (*started)(unsigned ch);
|
||||
int (*flush)(unsigned ch);
|
||||
int (*stop)(unsigned ch);
|
||||
};
|
||||
|
||||
extern void *samsung_dmadev_get_ops(void);
|
||||
extern void *s3c_dma_get_ops(void);
|
||||
|
||||
static inline void *__samsung_dma_get_ops(void)
|
||||
{
|
||||
if (samsung_dma_is_dmadev())
|
||||
return samsung_dmadev_get_ops();
|
||||
else
|
||||
return s3c_dma_get_ops();
|
||||
}
|
||||
|
||||
/*
|
||||
* samsung_dma_get_ops
|
||||
* get the set of samsung dma operations
|
||||
*/
|
||||
#define samsung_dma_get_ops() __samsung_dma_get_ops()
|
||||
|
||||
#endif /* __SAMSUNG_DMA_OPS_H_ */
|
||||
@ -1,121 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
|
||||
* Jaswinder Singh <jassi.brar@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DMA_PL330_H_
|
||||
#define __DMA_PL330_H_ __FILE__
|
||||
|
||||
/*
|
||||
* PL330 can assign any channel to communicate with
|
||||
* any of the peripherals attched to the DMAC.
|
||||
* For the sake of consistency across client drivers,
|
||||
* We keep the channel names unchanged and only add
|
||||
* missing peripherals are added.
|
||||
* Order is not important since DMA PL330 API driver
|
||||
* use these just as IDs.
|
||||
*/
|
||||
enum dma_ch {
|
||||
DMACH_UART0_RX = 0,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_UART5_RX,
|
||||
DMACH_UART5_TX,
|
||||
DMACH_USI_RX,
|
||||
DMACH_USI_TX,
|
||||
DMACH_IRDA,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_EXTERNAL,
|
||||
DMACH_PWM,
|
||||
DMACH_SPDIF,
|
||||
DMACH_HSI_RX,
|
||||
DMACH_HSI_TX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_MSM_REQ3,
|
||||
DMACH_MSM_REQ2,
|
||||
DMACH_MSM_REQ1,
|
||||
DMACH_MSM_REQ0,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS0AUX_RX,
|
||||
DMACH_SLIMBUS0AUX_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
DMACH_MIPI_HSI0,
|
||||
DMACH_MIPI_HSI1,
|
||||
DMACH_MIPI_HSI2,
|
||||
DMACH_MIPI_HSI3,
|
||||
DMACH_MIPI_HSI4,
|
||||
DMACH_MIPI_HSI5,
|
||||
DMACH_MIPI_HSI6,
|
||||
DMACH_MIPI_HSI7,
|
||||
DMACH_DISP1,
|
||||
DMACH_MTOM_0,
|
||||
DMACH_MTOM_1,
|
||||
DMACH_MTOM_2,
|
||||
DMACH_MTOM_3,
|
||||
DMACH_MTOM_4,
|
||||
DMACH_MTOM_5,
|
||||
DMACH_MTOM_6,
|
||||
DMACH_MTOM_7,
|
||||
/* END Marker, also used to denote a reserved channel */
|
||||
DMACH_MAX,
|
||||
};
|
||||
|
||||
struct s3c2410_dma_client {
|
||||
char *name;
|
||||
};
|
||||
|
||||
static inline bool samsung_dma_has_circular(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool samsung_dma_is_dmadev(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
#include <plat/dma-ops.h>
|
||||
|
||||
#endif /* __DMA_PL330_H_ */
|
||||
@ -1,73 +0,0 @@
|
||||
/* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
|
||||
*
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Samsung S3C24XX DMA support - per SoC functions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <plat/dma-core.h>
|
||||
|
||||
extern struct bus_type dma_subsys;
|
||||
extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
|
||||
|
||||
#define DMA_CH_VALID (1<<31)
|
||||
#define DMA_CH_NEVER (1<<30)
|
||||
|
||||
/* struct s3c24xx_dma_map
|
||||
*
|
||||
* this holds the mapping information for the channel selected
|
||||
* to be connected to the specified device
|
||||
*/
|
||||
|
||||
struct s3c24xx_dma_map {
|
||||
const char *name;
|
||||
|
||||
unsigned long channels[S3C_DMA_CHANNELS];
|
||||
};
|
||||
|
||||
struct s3c24xx_dma_selection {
|
||||
struct s3c24xx_dma_map *map;
|
||||
unsigned long map_size;
|
||||
unsigned long dcon_mask;
|
||||
|
||||
void (*select)(struct s3c2410_dma_chan *chan,
|
||||
struct s3c24xx_dma_map *map);
|
||||
};
|
||||
|
||||
extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
|
||||
|
||||
/* struct s3c24xx_dma_order_ch
|
||||
*
|
||||
* channel map for one of the `enum dma_ch` dma channels. the list
|
||||
* entry contains a set of low-level channel numbers, orred with
|
||||
* DMA_CH_VALID, which are checked in the order in the array.
|
||||
*/
|
||||
|
||||
struct s3c24xx_dma_order_ch {
|
||||
unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
|
||||
unsigned int flags; /* flags */
|
||||
};
|
||||
|
||||
/* struct s3c24xx_dma_order
|
||||
*
|
||||
* information provided by either the core or the board to give the
|
||||
* dma system a hint on how to allocate channels
|
||||
*/
|
||||
|
||||
struct s3c24xx_dma_order {
|
||||
struct s3c24xx_dma_order_ch channels[DMACH_MAX];
|
||||
};
|
||||
|
||||
extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
|
||||
|
||||
/* DMA init code, called from the cpu support code */
|
||||
|
||||
extern int s3c2410_dma_init(void);
|
||||
|
||||
extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
|
||||
unsigned int stride);
|
||||
@ -1,130 +0,0 @@
|
||||
/* arch/arm/plat-samsung/include/plat/dma.h
|
||||
*
|
||||
* Copyright (C) 2003-2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Samsung S3C DMA support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_DMA_H
|
||||
#define __PLAT_DMA_H
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
enum s3c2410_dma_buffresult {
|
||||
S3C2410_RES_OK,
|
||||
S3C2410_RES_ERR,
|
||||
S3C2410_RES_ABORT
|
||||
};
|
||||
|
||||
/* enum s3c2410_chan_op
|
||||
*
|
||||
* operation codes passed to the DMA code by the user, and also used
|
||||
* to inform the current channel owner of any changes to the system state
|
||||
*/
|
||||
|
||||
enum s3c2410_chan_op {
|
||||
S3C2410_DMAOP_START,
|
||||
S3C2410_DMAOP_STOP,
|
||||
S3C2410_DMAOP_PAUSE,
|
||||
S3C2410_DMAOP_RESUME,
|
||||
S3C2410_DMAOP_FLUSH,
|
||||
S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
|
||||
S3C2410_DMAOP_STARTED, /* indicate channel started */
|
||||
};
|
||||
|
||||
struct s3c2410_dma_client {
|
||||
char *name;
|
||||
};
|
||||
|
||||
struct s3c2410_dma_chan;
|
||||
enum dma_ch;
|
||||
|
||||
/* s3c2410_dma_cbfn_t
|
||||
*
|
||||
* buffer callback routine type
|
||||
*/
|
||||
|
||||
typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
|
||||
void *buf, int size,
|
||||
enum s3c2410_dma_buffresult result);
|
||||
|
||||
typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
|
||||
enum s3c2410_chan_op );
|
||||
|
||||
|
||||
|
||||
/* s3c2410_dma_request
|
||||
*
|
||||
* request a dma channel exclusivley
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_request(enum dma_ch channel,
|
||||
struct s3c2410_dma_client *, void *dev);
|
||||
|
||||
|
||||
/* s3c2410_dma_ctrl
|
||||
*
|
||||
* change the state of the dma channel
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op);
|
||||
|
||||
/* s3c2410_dma_setflags
|
||||
*
|
||||
* set the channel's flags to a given state
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_setflags(enum dma_ch channel,
|
||||
unsigned int flags);
|
||||
|
||||
/* s3c2410_dma_free
|
||||
*
|
||||
* free the dma channel (will also abort any outstanding operations)
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *);
|
||||
|
||||
/* s3c2410_dma_enqueue
|
||||
*
|
||||
* place the given buffer onto the queue of operations for the channel.
|
||||
* The buffer must be allocated from dma coherent memory, or the Dcache/WB
|
||||
* drained before the buffer is given to the DMA system.
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
|
||||
dma_addr_t data, int size);
|
||||
|
||||
/* s3c2410_dma_config
|
||||
*
|
||||
* configure the dma channel
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_config(enum dma_ch channel, int xferunit);
|
||||
|
||||
/* s3c2410_dma_devconfig
|
||||
*
|
||||
* configure the device we're talking to
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_devconfig(enum dma_ch channel,
|
||||
enum dma_data_direction source, unsigned long devaddr);
|
||||
|
||||
/* s3c2410_dma_getposition
|
||||
*
|
||||
* get the position that the dma transfer is currently at
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_getposition(enum dma_ch channel,
|
||||
dma_addr_t *src, dma_addr_t *dest);
|
||||
|
||||
extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn);
|
||||
extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn);
|
||||
|
||||
#include <plat/dma-ops.h>
|
||||
|
||||
#endif
|
||||
@ -1,151 +0,0 @@
|
||||
/* arch/arm/plat-samsung/include/plat/regs-dma.h
|
||||
*
|
||||
* Copyright (C) 2003-2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Samsung S3C24XX DMA support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_PLAT_REGS_DMA_H
|
||||
#define __ASM_PLAT_REGS_DMA_H __FILE__
|
||||
|
||||
#define S3C2410_DMA_DISRC (0x00)
|
||||
#define S3C2410_DMA_DISRCC (0x04)
|
||||
#define S3C2410_DMA_DIDST (0x08)
|
||||
#define S3C2410_DMA_DIDSTC (0x0C)
|
||||
#define S3C2410_DMA_DCON (0x10)
|
||||
#define S3C2410_DMA_DSTAT (0x14)
|
||||
#define S3C2410_DMA_DCSRC (0x18)
|
||||
#define S3C2410_DMA_DCDST (0x1C)
|
||||
#define S3C2410_DMA_DMASKTRIG (0x20)
|
||||
#define S3C2412_DMA_DMAREQSEL (0x24)
|
||||
#define S3C2443_DMA_DMAREQSEL (0x24)
|
||||
|
||||
#define S3C2410_DISRCC_INC (1 << 0)
|
||||
#define S3C2410_DISRCC_APB (1 << 1)
|
||||
|
||||
#define S3C2410_DMASKTRIG_STOP (1 << 2)
|
||||
#define S3C2410_DMASKTRIG_ON (1 << 1)
|
||||
#define S3C2410_DMASKTRIG_SWTRIG (1 << 0)
|
||||
|
||||
#define S3C2410_DCON_DEMAND (0 << 31)
|
||||
#define S3C2410_DCON_HANDSHAKE (1 << 31)
|
||||
#define S3C2410_DCON_SYNC_PCLK (0 << 30)
|
||||
#define S3C2410_DCON_SYNC_HCLK (1 << 30)
|
||||
|
||||
#define S3C2410_DCON_INTREQ (1 << 29)
|
||||
|
||||
#define S3C2410_DCON_CH0_XDREQ0 (0 << 24)
|
||||
#define S3C2410_DCON_CH0_UART0 (1 << 24)
|
||||
#define S3C2410_DCON_CH0_SDI (2 << 24)
|
||||
#define S3C2410_DCON_CH0_TIMER (3 << 24)
|
||||
#define S3C2410_DCON_CH0_USBEP1 (4 << 24)
|
||||
|
||||
#define S3C2410_DCON_CH1_XDREQ1 (0 << 24)
|
||||
#define S3C2410_DCON_CH1_UART1 (1 << 24)
|
||||
#define S3C2410_DCON_CH1_I2SSDI (2 << 24)
|
||||
#define S3C2410_DCON_CH1_SPI (3 << 24)
|
||||
#define S3C2410_DCON_CH1_USBEP2 (4 << 24)
|
||||
|
||||
#define S3C2410_DCON_CH2_I2SSDO (0 << 24)
|
||||
#define S3C2410_DCON_CH2_I2SSDI (1 << 24)
|
||||
#define S3C2410_DCON_CH2_SDI (2 << 24)
|
||||
#define S3C2410_DCON_CH2_TIMER (3 << 24)
|
||||
#define S3C2410_DCON_CH2_USBEP3 (4 << 24)
|
||||
|
||||
#define S3C2410_DCON_CH3_UART2 (0 << 24)
|
||||
#define S3C2410_DCON_CH3_SDI (1 << 24)
|
||||
#define S3C2410_DCON_CH3_SPI (2 << 24)
|
||||
#define S3C2410_DCON_CH3_TIMER (3 << 24)
|
||||
#define S3C2410_DCON_CH3_USBEP4 (4 << 24)
|
||||
|
||||
#define S3C2410_DCON_SRCSHIFT (24)
|
||||
#define S3C2410_DCON_SRCMASK (7 << 24)
|
||||
|
||||
#define S3C2410_DCON_BYTE (0 << 20)
|
||||
#define S3C2410_DCON_HALFWORD (1 << 20)
|
||||
#define S3C2410_DCON_WORD (2 << 20)
|
||||
|
||||
#define S3C2410_DCON_AUTORELOAD (0 << 22)
|
||||
#define S3C2410_DCON_NORELOAD (1 << 22)
|
||||
#define S3C2410_DCON_HWTRIG (1 << 23)
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
|
||||
#define S3C2440_DIDSTC_CHKINT (1 << 2)
|
||||
|
||||
#define S3C2440_DCON_CH0_I2SSDO (5 << 24)
|
||||
#define S3C2440_DCON_CH0_PCMIN (6 << 24)
|
||||
|
||||
#define S3C2440_DCON_CH1_PCMOUT (5 << 24)
|
||||
#define S3C2440_DCON_CH1_SDI (6 << 24)
|
||||
|
||||
#define S3C2440_DCON_CH2_PCMIN (5 << 24)
|
||||
#define S3C2440_DCON_CH2_MICIN (6 << 24)
|
||||
|
||||
#define S3C2440_DCON_CH3_MICIN (5 << 24)
|
||||
#define S3C2440_DCON_CH3_PCMOUT (6 << 24)
|
||||
#endif /* CONFIG_CPU_S3C2440 */
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2412
|
||||
|
||||
#define S3C2412_DMAREQSEL_SRC(x) ((x) << 1)
|
||||
|
||||
#define S3C2412_DMAREQSEL_HW (1)
|
||||
|
||||
#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
|
||||
#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
|
||||
#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
|
||||
#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
|
||||
#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
|
||||
#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
|
||||
#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
|
||||
#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
|
||||
#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
|
||||
#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
|
||||
#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
|
||||
#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
|
||||
#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
|
||||
#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
|
||||
#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
|
||||
#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
|
||||
#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
|
||||
#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
|
||||
#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
|
||||
#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
|
||||
#endif /* CONFIG_CPU_S3C2412 */
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
|
||||
|
||||
#define S3C2443_DMAREQSEL_SRC(x) ((x) << 1)
|
||||
|
||||
#define S3C2443_DMAREQSEL_HW (1)
|
||||
|
||||
#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
|
||||
#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
|
||||
#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
|
||||
#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
|
||||
#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
|
||||
#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
|
||||
#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
|
||||
#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
|
||||
#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
|
||||
#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
|
||||
#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
|
||||
#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
|
||||
#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
|
||||
#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
|
||||
#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
|
||||
#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
|
||||
#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
|
||||
#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
|
||||
#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
|
||||
#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
|
||||
#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
|
||||
#endif /* CONFIG_CPU_S3C2443 */
|
||||
|
||||
#endif /* __ASM_PLAT_REGS_DMA_H */
|
||||
@ -1,146 +0,0 @@
|
||||
/* linux/arch/arm/plat-samsung/s3c-dma-ops.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Samsung S3C-DMA Operations
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
struct cb_data {
|
||||
void (*fp) (void *);
|
||||
void *fp_param;
|
||||
unsigned ch;
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
static LIST_HEAD(dma_list);
|
||||
|
||||
static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
|
||||
int size, enum s3c2410_dma_buffresult res)
|
||||
{
|
||||
struct cb_data *data = param;
|
||||
|
||||
data->fp(data->fp_param);
|
||||
}
|
||||
|
||||
static unsigned s3c_dma_request(enum dma_ch dma_ch,
|
||||
struct samsung_dma_req *param,
|
||||
struct device *dev, char *ch_name)
|
||||
{
|
||||
struct cb_data *data;
|
||||
|
||||
if (s3c2410_dma_request(dma_ch, param->client, NULL) < 0) {
|
||||
s3c2410_dma_free(dma_ch, param->client);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (param->cap == DMA_CYCLIC)
|
||||
s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
|
||||
|
||||
data = kzalloc(sizeof(struct cb_data), GFP_KERNEL);
|
||||
data->ch = dma_ch;
|
||||
list_add_tail(&data->node, &dma_list);
|
||||
|
||||
return (unsigned)dma_ch;
|
||||
}
|
||||
|
||||
static int s3c_dma_release(unsigned ch, void *param)
|
||||
{
|
||||
struct cb_data *data;
|
||||
|
||||
list_for_each_entry(data, &dma_list, node)
|
||||
if (data->ch == ch)
|
||||
break;
|
||||
list_del(&data->node);
|
||||
|
||||
s3c2410_dma_free(ch, param);
|
||||
kfree(data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param)
|
||||
{
|
||||
s3c2410_dma_devconfig(ch, param->direction, param->fifo);
|
||||
s3c2410_dma_config(ch, param->width);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param)
|
||||
{
|
||||
struct cb_data *data;
|
||||
dma_addr_t pos = param->buf;
|
||||
dma_addr_t end = param->buf + param->len;
|
||||
|
||||
list_for_each_entry(data, &dma_list, node)
|
||||
if (data->ch == ch)
|
||||
break;
|
||||
|
||||
if (!data->fp) {
|
||||
s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb);
|
||||
data->fp = param->fp;
|
||||
data->fp_param = param->fp_param;
|
||||
}
|
||||
|
||||
if (param->cap != DMA_CYCLIC) {
|
||||
s3c2410_dma_enqueue(ch, (void *)data, param->buf, param->len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
while (pos < end) {
|
||||
s3c2410_dma_enqueue(ch, (void *)data, pos, param->period);
|
||||
pos += param->period;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int s3c_dma_trigger(unsigned ch)
|
||||
{
|
||||
return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_START);
|
||||
}
|
||||
|
||||
static inline int s3c_dma_started(unsigned ch)
|
||||
{
|
||||
return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STARTED);
|
||||
}
|
||||
|
||||
static inline int s3c_dma_flush(unsigned ch)
|
||||
{
|
||||
return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_FLUSH);
|
||||
}
|
||||
|
||||
static inline int s3c_dma_stop(unsigned ch)
|
||||
{
|
||||
return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STOP);
|
||||
}
|
||||
|
||||
static struct samsung_dma_ops s3c_dma_ops = {
|
||||
.request = s3c_dma_request,
|
||||
.release = s3c_dma_release,
|
||||
.config = s3c_dma_config,
|
||||
.prepare = s3c_dma_prepare,
|
||||
.trigger = s3c_dma_trigger,
|
||||
.started = s3c_dma_started,
|
||||
.flush = s3c_dma_flush,
|
||||
.stop = s3c_dma_stop,
|
||||
};
|
||||
|
||||
void *s3c_dma_get_ops(void)
|
||||
{
|
||||
return &s3c_dma_ops;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c_dma_get_ops);
|
||||
@ -184,7 +184,7 @@ config TEGRA20_APB_DMA
|
||||
|
||||
config S3C24XX_DMAC
|
||||
tristate "Samsung S3C24XX DMA support"
|
||||
depends on ARCH_S3C24XX && !S3C24XX_DMA
|
||||
depends on ARCH_S3C24XX
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
|
||||
Loading…
Reference in New Issue
Block a user