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octeontx2-af: enable tx shaping feature for 96xx C0
Starting from 96xx C0 onwards all silicons support traffic shaping. This patch enables that feature along with other changes - When PIR/CIR shaping config is modified, toggle SW_XOFF for config to take effect - Before SMQ flush, clear SW_XOFF at all parent schedulers - Support to read current transmit scheduler configuration via mbox Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Nithin Dabilpuram
David S. Miller
parent
fbcf8a3401
commit
d06411632e
@ -87,7 +87,7 @@ struct mbox_msghdr {
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#define OTX2_MBOX_REQ_SIG (0xdead)
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#define OTX2_MBOX_RSP_SIG (0xbeef)
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u16 sig; /* Signature, for validating corrupted msgs */
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#define OTX2_MBOX_VERSION (0x0007)
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#define OTX2_MBOX_VERSION (0x0009)
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u16 ver; /* Version of msg's structure for this ID */
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u16 next_msgoff; /* Offset of next msg within mailbox region */
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int rc; /* Msg process'ed response code */
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@ -243,7 +243,8 @@ M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
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M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
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nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
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M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
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M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \
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M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
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nix_txschq_config) \
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M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
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M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
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nix_vtag_config_rsp) \
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@ -370,16 +371,20 @@ struct msix_offset_rsp {
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struct mbox_msghdr hdr;
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u16 npa_msixoff;
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u16 nix_msixoff;
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u8 sso;
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u8 ssow;
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u8 timlfs;
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u8 cptlfs;
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u16 sso;
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u16 ssow;
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u16 timlfs;
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u16 cptlfs;
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u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
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u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
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u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
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u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
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u8 cpt1_lfs;
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u16 cpt1_lfs;
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u16 ree0_lfs;
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u16 ree1_lfs;
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u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
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u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
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u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
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};
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struct get_hw_cap_rsp {
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@ -836,6 +841,7 @@ struct nix_txsch_free_req {
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struct nix_txschq_config {
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struct mbox_msghdr hdr;
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u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
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u8 read;
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#define TXSCHQ_IDX_SHIFT 16
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#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
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#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
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@ -843,6 +849,8 @@ struct nix_txschq_config {
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#define MAX_REGS_PER_MBOX_MSG 20
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u64 reg[MAX_REGS_PER_MBOX_MSG];
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u64 regval[MAX_REGS_PER_MBOX_MSG];
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/* All 0's => overwrite with new value */
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u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
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};
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struct nix_vtag_config {
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@ -70,18 +70,21 @@ static void rvu_setup_hw_capabilities(struct rvu *rvu)
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hw->cap.nix_shaping = true;
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hw->cap.nix_tx_link_bp = true;
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hw->cap.nix_rx_multicast = true;
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hw->cap.nix_shaper_toggle_wait = false;
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hw->rvu = rvu;
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if (is_rvu_96xx_B0(rvu)) {
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if (is_rvu_pre_96xx_C0(rvu)) {
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hw->cap.nix_fixed_txschq_mapping = true;
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hw->cap.nix_txsch_per_cgx_lmac = 4;
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hw->cap.nix_txsch_per_lbk_lmac = 132;
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hw->cap.nix_txsch_per_sdp_lmac = 76;
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hw->cap.nix_shaping = false;
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hw->cap.nix_tx_link_bp = false;
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if (is_rvu_96xx_A0(rvu))
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if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu))
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hw->cap.nix_rx_multicast = false;
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}
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if (!is_rvu_pre_96xx_C0(rvu))
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hw->cap.nix_shaper_toggle_wait = true;
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if (!is_rvu_otx2(rvu))
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hw->cap.per_pf_mbox_regs = true;
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@ -328,6 +328,7 @@ struct hw_cap {
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u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
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bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
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bool nix_shaping; /* Is shaping and coloring supported */
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bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
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bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
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bool nix_rx_multicast; /* Rx packet replication support */
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bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
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@ -517,20 +518,34 @@ static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
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}
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/* Silicon revisions */
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static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
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{
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struct pci_dev *pdev = rvu->pdev;
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/* 96XX A0/B0, 95XX A0/A1/B0 chips */
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return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
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(pdev->revision == 0x10) || (pdev->revision == 0x11) ||
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(pdev->revision == 0x14));
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}
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static inline bool is_rvu_96xx_A0(struct rvu *rvu)
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{
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struct pci_dev *pdev = rvu->pdev;
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return (pdev->revision == 0x00) &&
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(pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
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return (pdev->revision == 0x00);
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}
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static inline bool is_rvu_96xx_B0(struct rvu *rvu)
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{
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struct pci_dev *pdev = rvu->pdev;
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return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) &&
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(pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
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return (pdev->revision == 0x00) || (pdev->revision == 0x01);
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}
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static inline bool is_rvu_95xx_A0(struct rvu *rvu)
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{
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struct pci_dev *pdev = rvu->pdev;
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return (pdev->revision == 0x10) || (pdev->revision == 0x11);
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}
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/* REVID for PCIe devices.
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@ -1423,12 +1423,104 @@ int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu,
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return 0;
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}
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/* Handle shaper update specially for few revisions */
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static bool
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handle_txschq_shaper_update(struct rvu *rvu, int blkaddr, int nixlf,
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int lvl, u64 reg, u64 regval)
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{
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u64 regbase, oldval, sw_xoff = 0;
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u64 dbgval, md_debug0 = 0;
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unsigned long poll_tmo;
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bool rate_reg = 0;
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u32 schq;
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regbase = reg & 0xFFFF;
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schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT);
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/* Check for rate register */
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switch (lvl) {
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case NIX_TXSCH_LVL_TL1:
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md_debug0 = NIX_AF_TL1X_MD_DEBUG0(schq);
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sw_xoff = NIX_AF_TL1X_SW_XOFF(schq);
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rate_reg = !!(regbase == NIX_AF_TL1X_CIR(0));
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break;
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case NIX_TXSCH_LVL_TL2:
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md_debug0 = NIX_AF_TL2X_MD_DEBUG0(schq);
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sw_xoff = NIX_AF_TL2X_SW_XOFF(schq);
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rate_reg = (regbase == NIX_AF_TL2X_CIR(0) ||
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regbase == NIX_AF_TL2X_PIR(0));
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break;
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case NIX_TXSCH_LVL_TL3:
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md_debug0 = NIX_AF_TL3X_MD_DEBUG0(schq);
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sw_xoff = NIX_AF_TL3X_SW_XOFF(schq);
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rate_reg = (regbase == NIX_AF_TL3X_CIR(0) ||
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regbase == NIX_AF_TL3X_PIR(0));
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break;
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case NIX_TXSCH_LVL_TL4:
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md_debug0 = NIX_AF_TL4X_MD_DEBUG0(schq);
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sw_xoff = NIX_AF_TL4X_SW_XOFF(schq);
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rate_reg = (regbase == NIX_AF_TL4X_CIR(0) ||
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regbase == NIX_AF_TL4X_PIR(0));
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break;
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case NIX_TXSCH_LVL_MDQ:
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sw_xoff = NIX_AF_MDQX_SW_XOFF(schq);
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rate_reg = (regbase == NIX_AF_MDQX_CIR(0) ||
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regbase == NIX_AF_MDQX_PIR(0));
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break;
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}
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if (!rate_reg)
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return false;
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/* Nothing special to do when state is not toggled */
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oldval = rvu_read64(rvu, blkaddr, reg);
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if ((oldval & 0x1) == (regval & 0x1)) {
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rvu_write64(rvu, blkaddr, reg, regval);
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return true;
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}
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/* PIR/CIR disable */
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if (!(regval & 0x1)) {
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rvu_write64(rvu, blkaddr, sw_xoff, 1);
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rvu_write64(rvu, blkaddr, reg, 0);
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udelay(4);
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rvu_write64(rvu, blkaddr, sw_xoff, 0);
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return true;
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}
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/* PIR/CIR enable */
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rvu_write64(rvu, blkaddr, sw_xoff, 1);
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if (md_debug0) {
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poll_tmo = jiffies + usecs_to_jiffies(10000);
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/* Wait until VLD(bit32) == 1 or C_CON(bit48) == 0 */
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do {
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if (time_after(jiffies, poll_tmo)) {
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dev_err(rvu->dev,
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"NIXLF%d: TLX%u(lvl %u) CIR/PIR enable failed\n",
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nixlf, schq, lvl);
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goto exit;
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}
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usleep_range(1, 5);
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dbgval = rvu_read64(rvu, blkaddr, md_debug0);
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} while (!(dbgval & BIT_ULL(32)) && (dbgval & BIT_ULL(48)));
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}
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rvu_write64(rvu, blkaddr, reg, regval);
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exit:
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rvu_write64(rvu, blkaddr, sw_xoff, 0);
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return true;
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}
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/* Disable shaping of pkts by a scheduler queue
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* at a given scheduler level.
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*/
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static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr,
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int lvl, int schq)
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int nixlf, int lvl, int schq)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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u64 cir_reg = 0, pir_reg = 0;
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u64 cfg;
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@ -1449,6 +1541,21 @@ static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr,
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cir_reg = NIX_AF_TL4X_CIR(schq);
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pir_reg = NIX_AF_TL4X_PIR(schq);
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break;
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case NIX_TXSCH_LVL_MDQ:
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cir_reg = NIX_AF_MDQX_CIR(schq);
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pir_reg = NIX_AF_MDQX_PIR(schq);
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break;
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}
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/* Shaper state toggle needs wait/poll */
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if (hw->cap.nix_shaper_toggle_wait) {
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if (cir_reg)
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handle_txschq_shaper_update(rvu, blkaddr, nixlf,
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lvl, cir_reg, 0);
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if (pir_reg)
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handle_txschq_shaper_update(rvu, blkaddr, nixlf,
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lvl, pir_reg, 0);
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return;
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}
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if (!cir_reg)
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@ -1466,6 +1573,7 @@ static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr,
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int lvl, int schq)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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int link_level;
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int link;
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if (lvl >= hw->cap.nix_tx_aggr_lvl)
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@ -1475,7 +1583,9 @@ static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr,
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if (lvl == NIX_TXSCH_LVL_TL4)
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rvu_write64(rvu, blkaddr, NIX_AF_TL4X_SDP_LINK_CFG(schq), 0x00);
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if (lvl != NIX_TXSCH_LVL_TL2)
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link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ?
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NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2;
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if (lvl != link_level)
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return;
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/* Reset TL2's CGX or LBK link config */
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@ -1484,6 +1594,40 @@ static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr,
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NIX_AF_TL3_TL2X_LINKX_CFG(schq, link), 0x00);
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}
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static void nix_clear_tx_xoff(struct rvu *rvu, int blkaddr,
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int lvl, int schq)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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u64 reg;
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/* Skip this if shaping is not supported */
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if (!hw->cap.nix_shaping)
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return;
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/* Clear level specific SW_XOFF */
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switch (lvl) {
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case NIX_TXSCH_LVL_TL1:
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reg = NIX_AF_TL1X_SW_XOFF(schq);
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break;
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case NIX_TXSCH_LVL_TL2:
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reg = NIX_AF_TL2X_SW_XOFF(schq);
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break;
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case NIX_TXSCH_LVL_TL3:
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reg = NIX_AF_TL3X_SW_XOFF(schq);
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break;
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case NIX_TXSCH_LVL_TL4:
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reg = NIX_AF_TL4X_SW_XOFF(schq);
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break;
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case NIX_TXSCH_LVL_MDQ:
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reg = NIX_AF_MDQX_SW_XOFF(schq);
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break;
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default:
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return;
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}
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rvu_write64(rvu, blkaddr, reg, 0x0);
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}
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static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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@ -1661,15 +1805,14 @@ int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu,
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int link, blkaddr, rc = 0;
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int lvl, idx, start, end;
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struct nix_txsch *txsch;
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struct rvu_pfvf *pfvf;
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struct nix_hw *nix_hw;
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u32 *pfvf_map;
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int nixlf;
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u16 schq;
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pfvf = rvu_get_pfvf(rvu, pcifunc);
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
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if (!pfvf->nixlf || blkaddr < 0)
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return NIX_AF_ERR_AF_LF_INVALID;
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rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
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if (rc)
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return rc;
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nix_hw = get_nix_hw(rvu->hw, blkaddr);
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if (!nix_hw)
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@ -1718,7 +1861,7 @@ int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu,
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NIX_TXSCHQ_CFG_DONE))
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pfvf_map[schq] = TXSCH_MAP(pcifunc, 0);
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nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq);
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nix_reset_tx_shaping(rvu, blkaddr, lvl, schq);
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nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq);
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}
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for (idx = 0; idx < req->schq[lvl]; idx++) {
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@ -1727,7 +1870,7 @@ int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu,
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NIX_TXSCHQ_CFG_DONE))
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pfvf_map[schq] = TXSCH_MAP(pcifunc, 0);
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nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq);
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nix_reset_tx_shaping(rvu, blkaddr, lvl, schq);
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nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq);
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}
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}
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@ -1744,7 +1887,7 @@ exit:
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return rc;
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}
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static void nix_smq_flush(struct rvu *rvu, int blkaddr,
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static int nix_smq_flush(struct rvu *rvu, int blkaddr,
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int smq, u16 pcifunc, int nixlf)
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{
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int pf = rvu_get_pf(pcifunc);
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@ -1780,6 +1923,7 @@ static void nix_smq_flush(struct rvu *rvu, int blkaddr,
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/* restore cgx tx state */
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if (restore_tx_en)
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cgx_lmac_tx_enable(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false);
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return err;
|
||||
}
|
||||
|
||||
static int nix_txschq_free(struct rvu *rvu, u16 pcifunc)
|
||||
@ -1788,6 +1932,7 @@ static int nix_txschq_free(struct rvu *rvu, u16 pcifunc)
|
||||
struct rvu_hwinfo *hw = rvu->hw;
|
||||
struct nix_txsch *txsch;
|
||||
struct nix_hw *nix_hw;
|
||||
u16 map_func;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
|
||||
if (blkaddr < 0)
|
||||
@ -1801,19 +1946,36 @@ static int nix_txschq_free(struct rvu *rvu, u16 pcifunc)
|
||||
if (nixlf < 0)
|
||||
return NIX_AF_ERR_AF_LF_INVALID;
|
||||
|
||||
/* Disable TL2/3 queue links before SMQ flush*/
|
||||
/* Disable TL2/3 queue links and all XOFF's before SMQ flush*/
|
||||
mutex_lock(&rvu->rsrc_lock);
|
||||
for (lvl = NIX_TXSCH_LVL_TL4; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
|
||||
if (lvl != NIX_TXSCH_LVL_TL2 && lvl != NIX_TXSCH_LVL_TL4)
|
||||
for (lvl = NIX_TXSCH_LVL_MDQ; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
|
||||
txsch = &nix_hw->txsch[lvl];
|
||||
|
||||
if (lvl >= hw->cap.nix_tx_aggr_lvl)
|
||||
continue;
|
||||
|
||||
txsch = &nix_hw->txsch[lvl];
|
||||
for (schq = 0; schq < txsch->schq.max; schq++) {
|
||||
if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
|
||||
continue;
|
||||
nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq);
|
||||
nix_clear_tx_xoff(rvu, blkaddr, lvl, schq);
|
||||
}
|
||||
}
|
||||
nix_clear_tx_xoff(rvu, blkaddr, NIX_TXSCH_LVL_TL1,
|
||||
nix_get_tx_link(rvu, pcifunc));
|
||||
|
||||
/* On PF cleanup, clear cfg done flag as
|
||||
* PF would have changed default config.
|
||||
*/
|
||||
if (!(pcifunc & RVU_PFVF_FUNC_MASK)) {
|
||||
txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL1];
|
||||
schq = nix_get_tx_link(rvu, pcifunc);
|
||||
/* Do not clear pcifunc in txsch->pfvf_map[schq] because
|
||||
* VF might be using this TL1 queue
|
||||
*/
|
||||
map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]);
|
||||
txsch->pfvf_map[schq] = TXSCH_SET_FLAG(map_func, 0x0);
|
||||
}
|
||||
|
||||
/* Flush SMQs */
|
||||
txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
|
||||
@ -1859,6 +2021,7 @@ static int nix_txschq_free_one(struct rvu *rvu,
|
||||
struct nix_txsch *txsch;
|
||||
struct nix_hw *nix_hw;
|
||||
u32 *pfvf_map;
|
||||
int rc;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
|
||||
if (blkaddr < 0)
|
||||
@ -1883,15 +2046,24 @@ static int nix_txschq_free_one(struct rvu *rvu,
|
||||
mutex_lock(&rvu->rsrc_lock);
|
||||
|
||||
if (TXSCH_MAP_FUNC(pfvf_map[schq]) != pcifunc) {
|
||||
mutex_unlock(&rvu->rsrc_lock);
|
||||
rc = NIX_AF_ERR_TLX_INVALID;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Clear SW_XOFF of this resource only.
|
||||
* For SMQ level, all path XOFF's
|
||||
* need to be made clear by user
|
||||
*/
|
||||
nix_clear_tx_xoff(rvu, blkaddr, lvl, schq);
|
||||
|
||||
/* Flush if it is a SMQ. Onus of disabling
|
||||
* TL2/3 queue links before SMQ flush is on user
|
||||
*/
|
||||
if (lvl == NIX_TXSCH_LVL_SMQ)
|
||||
nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf);
|
||||
if (lvl == NIX_TXSCH_LVL_SMQ &&
|
||||
nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf)) {
|
||||
rc = NIX_AF_SMQ_FLUSH_FAILED;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Free the resource */
|
||||
rvu_free_rsrc(&txsch->schq, schq);
|
||||
@ -1899,7 +2071,8 @@ static int nix_txschq_free_one(struct rvu *rvu,
|
||||
mutex_unlock(&rvu->rsrc_lock);
|
||||
return 0;
|
||||
err:
|
||||
return NIX_AF_ERR_TLX_INVALID;
|
||||
mutex_unlock(&rvu->rsrc_lock);
|
||||
return rc;
|
||||
}
|
||||
|
||||
int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu,
|
||||
@ -1982,6 +2155,11 @@ static bool is_txschq_shaping_valid(struct rvu_hwinfo *hw, int lvl, u64 reg)
|
||||
regbase == NIX_AF_TL4X_PIR(0))
|
||||
return false;
|
||||
break;
|
||||
case NIX_TXSCH_LVL_MDQ:
|
||||
if (regbase == NIX_AF_MDQX_CIR(0) ||
|
||||
regbase == NIX_AF_MDQX_PIR(0))
|
||||
return false;
|
||||
break;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
@ -2014,6 +2192,33 @@ static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw,
|
||||
pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE);
|
||||
}
|
||||
|
||||
/* Register offset - [15:0]
|
||||
* Scheduler Queue number - [25:16]
|
||||
*/
|
||||
#define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0)
|
||||
|
||||
static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw,
|
||||
int blkaddr, struct nix_txschq_config *req,
|
||||
struct nix_txschq_config *rsp)
|
||||
{
|
||||
u16 pcifunc = req->hdr.pcifunc;
|
||||
int idx, schq;
|
||||
u64 reg;
|
||||
|
||||
for (idx = 0; idx < req->num_regs; idx++) {
|
||||
reg = req->reg[idx];
|
||||
reg &= NIX_TX_SCHQ_MASK;
|
||||
schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT);
|
||||
if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, req->lvl, reg) ||
|
||||
!is_valid_txschq(rvu, blkaddr, req->lvl, pcifunc, schq))
|
||||
return NIX_AF_INVAL_TXSCHQ_CFG;
|
||||
rsp->regval[idx] = rvu_read64(rvu, blkaddr, reg);
|
||||
}
|
||||
rsp->lvl = req->lvl;
|
||||
rsp->num_regs = req->num_regs;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr,
|
||||
u16 pcifunc, struct nix_txsch *txsch)
|
||||
{
|
||||
@ -2045,11 +2250,11 @@ static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr,
|
||||
|
||||
int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
|
||||
struct nix_txschq_config *req,
|
||||
struct msg_rsp *rsp)
|
||||
struct nix_txschq_config *rsp)
|
||||
{
|
||||
u64 reg, val, regval, schq_regbase, val_mask;
|
||||
struct rvu_hwinfo *hw = rvu->hw;
|
||||
u16 pcifunc = req->hdr.pcifunc;
|
||||
u64 reg, regval, schq_regbase;
|
||||
struct nix_txsch *txsch;
|
||||
struct nix_hw *nix_hw;
|
||||
int blkaddr, idx, err;
|
||||
@ -2068,6 +2273,9 @@ int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
|
||||
if (!nix_hw)
|
||||
return NIX_AF_ERR_INVALID_NIXBLK;
|
||||
|
||||
if (req->read)
|
||||
return nix_txschq_cfg_read(rvu, nix_hw, blkaddr, req, rsp);
|
||||
|
||||
txsch = &nix_hw->txsch[req->lvl];
|
||||
pfvf_map = txsch->pfvf_map;
|
||||
|
||||
@ -2082,8 +2290,10 @@ int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
|
||||
|
||||
for (idx = 0; idx < req->num_regs; idx++) {
|
||||
reg = req->reg[idx];
|
||||
reg &= NIX_TX_SCHQ_MASK;
|
||||
regval = req->regval[idx];
|
||||
schq_regbase = reg & 0xFFFF;
|
||||
val_mask = req->regval_mask[idx];
|
||||
|
||||
if (!is_txschq_hierarchy_valid(rvu, pcifunc, blkaddr,
|
||||
txsch->lvl, reg, regval))
|
||||
@ -2093,6 +2303,15 @@ int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
|
||||
if (!is_txschq_shaping_valid(hw, req->lvl, reg))
|
||||
continue;
|
||||
|
||||
val = rvu_read64(rvu, blkaddr, reg);
|
||||
regval = (val & val_mask) | (regval & ~val_mask);
|
||||
|
||||
/* Handle shaping state toggle specially */
|
||||
if (hw->cap.nix_shaper_toggle_wait &&
|
||||
handle_txschq_shaper_update(rvu, blkaddr, nixlf,
|
||||
req->lvl, reg, regval))
|
||||
continue;
|
||||
|
||||
/* Replace PF/VF visible NIXLF slot with HW NIXLF id */
|
||||
if (schq_regbase == NIX_AF_SMQX_CFG(0)) {
|
||||
nixlf = rvu_get_lf(rvu, &hw->block[blkaddr],
|
||||
@ -2133,7 +2352,6 @@ int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
|
||||
|
||||
rvu_nix_tx_tl2_cfg(rvu, blkaddr, pcifunc,
|
||||
&nix_hw->txsch[NIX_TXSCH_LVL_TL2]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -33,8 +33,8 @@ static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
|
||||
{NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
|
||||
{NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
|
||||
{0x1200, 0x12E0} } },
|
||||
{NIX_TXSCH_LVL_TL3, 3, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
|
||||
{0x1610, 0x1618} } },
|
||||
{NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
|
||||
{0x1610, 0x1618}, {0x1700, 0x17B0} } },
|
||||
{NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0} } },
|
||||
{NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user