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drm/i915/gen8: Move WaDisablePartialInstShootdown to common init fn
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -810,6 +810,10 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
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/* WaDisableAsyncFlipPerfMode:bdw,chv */
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WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
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/* WaDisablePartialInstShootdown:bdw,chv */
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
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return 0;
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}
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@ -823,11 +827,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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if (ret)
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return ret;
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/* WaDisablePartialInstShootdown:bdw */
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/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
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STALL_DOP_GATING_DISABLE);
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
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/* WaDisableDopClockGating:bdw */
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WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
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@ -889,11 +890,8 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
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if (ret)
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return ret;
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/* WaDisablePartialInstShootdown:chv */
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/* WaDisableThreadStallDopClockGating:chv */
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
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STALL_DOP_GATING_DISABLE);
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
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/* Use Force Non-Coherent whenever executing a 3D context. This is a
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* workaround for a possible hang in the unlikely event a TLB
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