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ARM: SoC cleanups for v4.1
We've got a fairly large cleanup branch this time. The bulk of this is removal of non-DT platforms of several flavors: - Atmel at91 platforms go full-DT, with removal of remaining board-file based support - OMAP removes legacy board files for three more platforms - Removal of non-DT mach-msm, newer Qualcomm platforms now live in mach-qcom - Freescale i.MX25 also removes non-DT platform support Most of the rest of the changes here are fallout from the above, i.e. for example removal of drivers that now lack platforms, etc. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVNzI3AAoJEIwa5zzehBx3ePwQAJKb4Mf72/4iiKb4dbVcooQN EiZ84fwWiWD6Mww/3A76xVnz/b7JWmB3vwW0b4fcbvzubmOjnROBmZgCWeNy4ZTv dOZc3/9jK7OrlwvpFBeZykQwHcbz+550+m3WxmLft1oqH/7BA1k5aunwYtFB96ii 5Owi4Cy9OmxEyALQAvzktFaJdI7J66LNb+i30r5zIZHlkVooeF3UyadndiswUP2o EBzCE8UPqRi5kV6FuwVyf4MZaV28FWoglTqdx9OxogcTnKNFT6RlHQ39q/iPu348 Wkh4kOryVy7Rlab1K4wQRpBoOwkonKDV73u2H2ifRFj7V9ZAdjibK8pgKn3kjkba bJkwHIqlqtqqqjj2Hh93wl+8hKSypoLXO9tagPWYBiLtFXCH/+EVsihWYpAc/A5E pUS6hJrJyXKJouwwsXu6459zP0ieqhvpbQG72xs9PRimAfAdSTulSTzdI/dMh42Q pwYkmvh+ReY3Ll4MeCzu7+eCIY0qAKsor48W1ImuziwQhg2lZj16qWtA4YdPk3+O N8ckyaaFg663PAfsZgBx1qTgxw5v0ec2k68/iEVGS5mUJCgcWxFvR95chTDIxQXq ZmJ+SuMFyLB/2zVSiGU96L1PQTcUkxJJ8LVB3qNp6KlYT7qUSsgAU+qYveFlUh+p X8MVsSVh8n1MTNepsLij =BV8A -----END PGP SIGNATURE----- Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "We've got a fairly large cleanup branch this time. The bulk of this is removal of non-DT platforms of several flavors: - Atmel at91 platforms go full-DT, with removal of remaining board-file based support - OMAP removes legacy board files for three more platforms - removal of non-DT mach-msm, newer Qualcomm platforms now live in mach-qcom - Freescale i.MX25 also removes non-DT platform support" Most of the rest of the changes here are fallout from the above, i.e. for example removal of drivers that now lack platforms, etc. * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (58 commits) mmc: Remove msm_sdcc driver gpio: Remove gpio-msm-v1 driver ARM: Remove mach-msm and associated ARM architecture code ARM: shmobile: cpuidle: Remove the pointless default driver ARM: davinci: dm646x: Add interrupt resource for McASPs ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x ARM: davinci: dm646x: Clean up the McASP DMA resources ARM: davinci: devices-da8xx: Add support for McASP2 on da830 ARM: davinci: devices-da8xx: Clean up and correct the McASP device creation ARM: davinci: devices-da8xx: Add interrupt resource to McASP structs ARM: davinci: devices-da8xx: Add resource name for the McASP DMA request ARM: OMAP2+: Remove legacy support for omap3 TouchBook ARM: OMAP3: Remove legacy support for devkit8000 ARM: OMAP3: Remove legacy support for EMA-Tech Stalker board ARM: shmobile: Consolidate the pm code for R-Car Gen2 ARM: shmobile: r8a7791: Correct SYSCIER value ARM: shmobile: r8a7790: Correct SYSCIER value ARM: at91: remove old setup ARM: at91: sama5d4: remove useless map_io ARM: at91: sama5 use SoC detection infrastructure ...
This commit is contained in:
commit
d0440c59f5
@ -10,8 +10,6 @@ IXP4xx
|
||||
- Intel IXP4xx Network processor.
|
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Makefile
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- Build sourcefiles as part of the Documentation-build for arm
|
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msm/
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- MSM specific documentation
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Netwinder
|
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- Netwinder specific documentation
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Porting
|
||||
|
@ -1,176 +0,0 @@
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This document provides an overview of the msm_gpiomux interface, which
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is used to provide gpio pin multiplexing and configuration on mach-msm
|
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targets.
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|
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History
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=======
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The first-generation API for gpio configuration & multiplexing on msm
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is the function gpio_tlmm_config(). This function has a few notable
|
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shortcomings, which led to its deprecation and replacement by gpiomux:
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The 'disable' parameter: Setting the second parameter to
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gpio_tlmm_config to GPIO_CFG_DISABLE tells the peripheral
|
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processor in charge of the subsystem to perform a look-up into a
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low-power table and apply the low-power/sleep setting for the pin.
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As the msm family evolved this became problematic. Not all pins
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have sleep settings, not all peripheral processors will accept requests
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to apply said sleep settings, and not all msm targets have their gpio
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subsystems managed by a peripheral processor. In order to get consistent
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behavior on all targets, drivers are forced to ignore this parameter,
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rendering it useless.
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The 'direction' flag: for all mux-settings other than raw-gpio (0),
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the output-enable bit of a gpio is hard-wired to a known
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input (usually VDD or ground). For those settings, the direction flag
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is meaningless at best, and deceptive at worst. In addition, using the
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direction flag to change output-enable (OE) directly can cause trouble in
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gpiolib, which has no visibility into gpio direction changes made
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in this way. Direction control in gpio mode should be made through gpiolib.
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Key Features of gpiomux
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=======================
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- A consistent interface across all generations of msm. Drivers can expect
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the same results on every target.
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- gpiomux plays nicely with gpiolib. Functions that should belong to gpiolib
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are left to gpiolib and not duplicated here. gpiomux is written with the
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intent that gpio_chips will call gpiomux reference-counting methods
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from their request() and free() hooks, providing full integration.
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- Tabular configuration. Instead of having to call gpio_tlmm_config
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hundreds of times, gpio configuration is placed in a single table.
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- Per-gpio sleep. Each gpio is individually reference counted, allowing only
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those lines which are in use to be put in high-power states.
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- 0 means 'do nothing': all flags are designed so that the default memset-zero
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equates to a sensible default of 'no configuration', preventing users
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from having to provide hundreds of 'no-op' configs for unused or
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unwanted lines.
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Usage
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=====
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To use gpiomux, provide configuration information for relevant gpio lines
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in the msm_gpiomux_configs table. Since a 0 equates to "unconfigured",
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only those lines to be managed by gpiomux need to be specified. Here
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is a completely fictional example:
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struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
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[12] = {
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.active = GPIOMUX_VALID | GPIOMUX_DRV_8MA | GPIOMUX_FUNC_1,
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.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
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},
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[34] = {
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.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
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},
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};
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To indicate that a gpio is in use, call msm_gpiomux_get() to increase
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its reference count. To decrease the reference count, call msm_gpiomux_put().
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The effect of this configuration is as follows:
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When the system boots, gpios 12 and 34 will be initialized with their
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'suspended' configurations. All other gpios, which were left unconfigured,
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will not be touched.
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When msm_gpiomux_get() is called on gpio 12 to raise its reference count
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above 0, its active configuration will be applied. Since no other gpio
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line has a valid active configuration, msm_gpiomux_get() will have no
|
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effect on any other line.
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When msm_gpiomux_put() is called on gpio 12 or 34 to drop their reference
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count to 0, their suspended configurations will be applied.
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Since no other gpio line has a valid suspended configuration, no other
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gpio line will be effected by msm_gpiomux_put(). Since gpio 34 has no valid
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active configuration, this is effectively a no-op for gpio 34 as well,
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with one small caveat, see the section "About Output-Enable Settings".
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All of the GPIOMUX_VALID flags may seem like unnecessary overhead, but
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they address some important issues. As unused entries (all those
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except 12 and 34) are zero-filled, gpiomux needs a way to distinguish
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the used fields from the unused. In addition, the all-zero pattern
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is a valid configuration! Therefore, gpiomux defines an additional bit
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which is used to indicate when a field is used. This has the pleasant
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||||
side-effect of allowing calls to msm_gpiomux_write to use '0' to indicate
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that a value should not be changed:
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msm_gpiomux_write(0, GPIOMUX_VALID, 0);
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replaces the active configuration of gpio 0 with an all-zero configuration,
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but leaves the suspended configuration as it was.
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Static Configurations
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=====================
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To install a static configuration, which is applied at boot and does
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not change after that, install a configuration with a suspended component
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but no active component, as in the previous example:
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[34] = {
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.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
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},
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The suspended setting is applied during boot, and the lack of any valid
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active setting prevents any other setting from being applied at runtime.
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If other subsystems attempting to access the line is a concern, one could
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*really* anchor the configuration down by calling msm_gpiomux_get on the
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line at initialization to move the line into active mode. With the line
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held, it will never be re-suspended, and with no valid active configuration,
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no new configurations will be applied.
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But then, if having other subsystems grabbing for the line is truly a concern,
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it should be reserved with gpio_request instead, which carries an implicit
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msm_gpiomux_get.
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gpiomux and gpiolib
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===================
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It is expected that msm gpio_chips will call msm_gpiomux_get() and
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msm_gpiomux_put() from their request and free hooks, like this fictional
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example:
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static int request(struct gpio_chip *chip, unsigned offset)
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{
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return msm_gpiomux_get(chip->base + offset);
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}
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static void free(struct gpio_chip *chip, unsigned offset)
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{
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msm_gpiomux_put(chip->base + offset);
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}
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...somewhere in a gpio_chip declaration...
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.request = request,
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.free = free,
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This provides important functionality:
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- It guarantees that a gpio line will have its 'active' config applied
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when the line is requested, and will not be suspended while the line
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remains requested; and
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- It guarantees that gpio-direction settings from gpiolib behave sensibly.
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See "About Output-Enable Settings."
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This mechanism allows for "auto-request" of gpiomux lines via gpiolib
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when it is suitable. Drivers wishing more exact control are, of course,
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free to also use msm_gpiomux_set and msm_gpiomux_get.
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About Output-Enable Settings
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============================
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Some msm targets do not have the ability to query the current gpio
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configuration setting. This means that changes made to the output-enable
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(OE) bit by gpiolib cannot be consistently detected and preserved by gpiomux.
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Therefore, when gpiomux applies a configuration setting, any direction
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settings which may have been applied by gpiolib are lost and the default
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input settings are re-applied.
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For this reason, drivers should not assume that gpio direction settings
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continue to hold if they free and then re-request a gpio. This seems like
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common sense - after all, anybody could have obtained the line in the
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meantime - but it needs saying.
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This also means that calls to msm_gpiomux_write will reset the OE bit,
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which means that if the gpio line is held by a client of gpiolib and
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msm_gpiomux_write is called, the direction setting has been lost and
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gpiolib's internal state has been broken.
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Release gpio lines before reconfiguring them.
|
@ -1,9 +1,10 @@
|
||||
* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
|
||||
|
||||
Required properties:
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- compatible: Should be "atmel,<chip>-usart"
|
||||
- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
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The compatible <chip> indicated will be the first SoC to support an
|
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additional mode or an USART new feature.
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For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt
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- clock-names: tuple listing input clock names.
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|
20
MAINTAINERS
20
MAINTAINERS
@ -1261,22 +1261,6 @@ L: openmoko-kernel@lists.openmoko.org (subscribers-only)
|
||||
W: http://wiki.openmoko.org/wiki/Neo_FreeRunner
|
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S: Supported
|
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ARM/QUALCOMM MSM MACHINE SUPPORT
|
||||
M: David Brown <davidb@codeaurora.org>
|
||||
M: Daniel Walker <dwalker@fifo99.com>
|
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M: Bryan Huntsman <bryanh@codeaurora.org>
|
||||
L: linux-arm-msm@vger.kernel.org
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F: arch/arm/mach-msm/
|
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F: drivers/video/fbdev/msm/
|
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F: drivers/mmc/host/msm_sdcc.c
|
||||
F: drivers/mmc/host/msm_sdcc.h
|
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F: drivers/tty/serial/msm_serial.h
|
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F: drivers/tty/serial/msm_serial.c
|
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F: drivers/*/pm8???-*
|
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F: drivers/mfd/ssbi.c
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git
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S: Maintained
|
||||
|
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ARM/TOSA MACHINE SUPPORT
|
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M: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
|
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M: Dirk Opfer <dirk@opfer-online.de>
|
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@ -1334,6 +1318,10 @@ L: linux-soc@vger.kernel.org
|
||||
S: Maintained
|
||||
F: arch/arm/mach-qcom/
|
||||
F: drivers/soc/qcom/
|
||||
F: drivers/tty/serial/msm_serial.h
|
||||
F: drivers/tty/serial/msm_serial.c
|
||||
F: drivers/*/pm8???-*
|
||||
F: drivers/mfd/ssbi.c
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
|
||||
|
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ARM/RADISYS ENP2611 MACHINE SUPPORT
|
||||
|
@ -367,9 +367,9 @@ config ARCH_AT91
|
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select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKDEV_LOOKUP
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select IRQ_DOMAIN
|
||||
select NEED_MACH_IO_H if PCCARD
|
||||
select PINCTRL
|
||||
select PINCTRL_AT91
|
||||
select SOC_BUS
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for systems based on Atmel
|
||||
@ -632,18 +632,6 @@ config ARCH_PXA
|
||||
help
|
||||
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
|
||||
|
||||
config ARCH_MSM
|
||||
bool "Qualcomm MSM (non-multiplatform)"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select COMMON_CLK
|
||||
select GENERIC_CLOCKEVENTS
|
||||
help
|
||||
Support for Qualcomm MSM/QSD based systems. This runs on the
|
||||
apps processor of the MSM/QSD and depends on a shared memory
|
||||
interface to the modem processor which runs the baseband
|
||||
stack and controls some vital subsystems
|
||||
(clock and power control, etc).
|
||||
|
||||
config ARCH_SHMOBILE_LEGACY
|
||||
bool "Renesas ARM SoCs (non-multiplatform)"
|
||||
select ARCH_SHMOBILE
|
||||
@ -897,8 +885,6 @@ source "arch/arm/mach-ks8695/Kconfig"
|
||||
|
||||
source "arch/arm/mach-meson/Kconfig"
|
||||
|
||||
source "arch/arm/mach-msm/Kconfig"
|
||||
|
||||
source "arch/arm/mach-moxart/Kconfig"
|
||||
|
||||
source "arch/arm/mach-mv78xx0/Kconfig"
|
||||
|
@ -448,25 +448,6 @@ choice
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on MMP UART3.
|
||||
|
||||
config DEBUG_MSM_UART
|
||||
bool "Kernel low-level debugging messages via MSM UART"
|
||||
depends on ARCH_MSM
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on MSM devices.
|
||||
|
||||
ARCH DEBUG_UART_PHYS DEBUG_UART_VIRT #
|
||||
MSM7X00A, QSD8X50 0xa9a00000 0xe1000000 UART1
|
||||
MSM7X00A, QSD8X50 0xa9b00000 0xe1000000 UART2
|
||||
MSM7X00A, QSD8X50 0xa9c00000 0xe1000000 UART3
|
||||
|
||||
MSM7X30 0xaca00000 0xe1000000 UART1
|
||||
MSM7X30 0xacb00000 0xe1000000 UART2
|
||||
MSM7X30 0xacc00000 0xe1000000 UART3
|
||||
|
||||
Please adjust DEBUG_UART_PHYS and DEBUG_UART_BASE configuration
|
||||
options based on your needs.
|
||||
|
||||
config DEBUG_QCOM_UARTDM
|
||||
bool "Kernel low-level debugging messages via QCOM UARTDM"
|
||||
depends on ARCH_QCOM
|
||||
@ -806,7 +787,7 @@ choice
|
||||
via SCIF2 on Renesas R-Car H1 (R8A7779).
|
||||
|
||||
config DEBUG_RCAR_GEN2_SCIF0
|
||||
bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7793)"
|
||||
bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7793"
|
||||
depends on ARCH_R8A7790 || ARCH_R8A7791 || ARCH_R8A7793
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
@ -1295,7 +1276,7 @@ config DEBUG_LL_INCLUDE
|
||||
DEBUG_IMX6SL_UART || \
|
||||
DEBUG_IMX6SX_UART
|
||||
default "debug/ks8695.S" if DEBUG_KS8695_UART
|
||||
default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
|
||||
default "debug/msm.S" if DEBUG_QCOM_UARTDM
|
||||
default "debug/netx.S" if DEBUG_NETX_UART
|
||||
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
|
||||
default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
|
||||
@ -1388,7 +1369,6 @@ config DEBUG_UART_PHYS
|
||||
default 0x80230000 if DEBUG_PICOXCELL_UART
|
||||
default 0x808c0000 if ARCH_EP93XX
|
||||
default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
|
||||
default 0xa9a00000 if DEBUG_MSM_UART
|
||||
default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1
|
||||
default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
|
||||
default 0xc0013000 if DEBUG_U300_UART
|
||||
@ -1433,7 +1413,7 @@ config DEBUG_UART_PHYS
|
||||
DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
|
||||
DEBUG_LL_UART_EFM32 || \
|
||||
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
|
||||
DEBUG_MSM_UART || DEBUG_NETX_UART || \
|
||||
DEBUG_NETX_UART || \
|
||||
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
|
||||
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
|
||||
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
|
||||
@ -1446,7 +1426,6 @@ config DEBUG_UART_VIRT
|
||||
hex "Virtual base address of debug UART"
|
||||
default 0xe0000a00 if DEBUG_NETX_UART
|
||||
default 0xe0010fe0 if ARCH_RPC
|
||||
default 0xe1000000 if DEBUG_MSM_UART
|
||||
default 0xf0000be0 if ARCH_EBSA110
|
||||
default 0xf0010000 if DEBUG_ASM9260_UART
|
||||
default 0xf01fb000 if DEBUG_NOMADIK_UART
|
||||
@ -1526,7 +1505,7 @@ config DEBUG_UART_VIRT
|
||||
default DEBUG_UART_PHYS if !MMU
|
||||
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
|
||||
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
|
||||
DEBUG_MSM_UART || DEBUG_NETX_UART || \
|
||||
DEBUG_NETX_UART || \
|
||||
DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
|
||||
DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \
|
||||
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0
|
||||
@ -1556,7 +1535,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
|
||||
|
||||
config DEBUG_UNCOMPRESS
|
||||
bool
|
||||
depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG
|
||||
depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG
|
||||
default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
|
||||
(!DEBUG_TEGRA_UART || !ZBOOT_ROM)
|
||||
help
|
||||
|
@ -136,7 +136,6 @@ textofs-$(CONFIG_PM_H1940) := 0x00108000
|
||||
ifeq ($(CONFIG_ARCH_SA1100),y)
|
||||
textofs-$(CONFIG_SA1111) := 0x00208000
|
||||
endif
|
||||
textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
|
||||
@ -171,7 +170,6 @@ machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
|
||||
machine-$(CONFIG_ARCH_MESON) += meson
|
||||
machine-$(CONFIG_ARCH_MMP) += mmp
|
||||
machine-$(CONFIG_ARCH_MOXART) += moxart
|
||||
machine-$(CONFIG_ARCH_MSM) += msm
|
||||
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
|
||||
machine-$(CONFIG_ARCH_MVEBU) += mvebu
|
||||
machine-$(CONFIG_ARCH_MXC) += imx
|
||||
|
@ -830,7 +830,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91rm9200-usart";
|
||||
compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -753,7 +753,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -276,7 +276,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -762,7 +762,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xffffee00 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -893,7 +893,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xffffee00 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -757,7 +757,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -377,7 +377,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -860,7 +860,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -439,7 +439,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xffffee00 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
|
||||
|
@ -1064,7 +1064,7 @@
|
||||
};
|
||||
|
||||
dbgu: serial@fc069000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xfc069000 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -24,9 +24,8 @@ CONFIG_ARCH_MXC=y
|
||||
CONFIG_MACH_SCB9328=y
|
||||
CONFIG_MACH_APF9328=y
|
||||
CONFIG_MACH_MX21ADS=y
|
||||
CONFIG_MACH_MX25_3DS=y
|
||||
CONFIG_MACH_EUKREA_CPUIMX25SD=y
|
||||
CONFIG_MACH_IMX25_DT=y
|
||||
CONFIG_SOC_IMX25=y
|
||||
CONFIG_MACH_MX27ADS=y
|
||||
CONFIG_MACH_MX27_3DS=y
|
||||
CONFIG_MACH_IMX27_VISSTRIM_M10=y
|
||||
|
@ -1,121 +0,0 @@
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HIGHPTE=y
|
||||
CONFIG_CLEANCACHE=y
|
||||
CONFIG_AUTO_ZRELADDR=y
|
||||
CONFIG_VFP=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_CFG80211=y
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
CONFIG_USB_USBNET=y
|
||||
# CONFIG_USB_NET_AX8817X is not set
|
||||
# CONFIG_USB_NET_ZAURUS is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
# CONFIG_MOUSE_PS2 is not set
|
||||
CONFIG_INPUT_JOYSTICK=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_DYNAMIC_MINORS=y
|
||||
# CONFIG_SND_ARM is not set
|
||||
# CONFIG_SND_SPI is not set
|
||||
# CONFIG_SND_USB is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_SERIAL=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DEBUG_FILES=y
|
||||
CONFIG_USB_GADGET_VBUS_DRAW=500
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_CIFS=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
# CONFIG_DETECT_HUNG_TASK is not set
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
@ -13,7 +13,7 @@ CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_MACH_KIRKWOOD=y
|
||||
CONFIG_MACH_NETXBIG=y
|
||||
CONFIG_ARCH_MXC=y
|
||||
CONFIG_MACH_IMX25_DT=y
|
||||
CONFIG_SOC_IMX25=y
|
||||
CONFIG_MACH_IMX27_DT=y
|
||||
CONFIG_ARCH_U300=y
|
||||
CONFIG_PCI_MVEBU=y
|
||||
|
@ -16,24 +16,17 @@
|
||||
*/
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
#ifdef CONFIG_DEBUG_UART_PHYS
|
||||
ldr \rp, =CONFIG_DEBUG_UART_PHYS
|
||||
ldr \rv, =CONFIG_DEBUG_UART_VIRT
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro senduart, rd, rx
|
||||
ARM_BE8(rev \rd, \rd )
|
||||
#ifdef CONFIG_DEBUG_QCOM_UARTDM
|
||||
@ Write the 1 character to UARTDM_TF
|
||||
str \rd, [\rx, #0x70]
|
||||
#else
|
||||
str \rd, [\rx, #0x0C]
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro waituart, rd, rx
|
||||
#ifdef CONFIG_DEBUG_QCOM_UARTDM
|
||||
@ check for TX_EMT in UARTDM_SR
|
||||
ldr \rd, [\rx, #0x08]
|
||||
ARM_BE8(rev \rd, \rd )
|
||||
@ -55,13 +48,6 @@ ARM_BE8(rev \rd, \rd )
|
||||
str \rd, [\rx, #0x40]
|
||||
@ UARTDM reg. Read to induce delay
|
||||
ldr \rd, [\rx, #0x08]
|
||||
#else
|
||||
@ wait for TX_READY
|
||||
1001: ldr \rd, [\rx, #0x08]
|
||||
ARM_BE8(rev \rd, \rd )
|
||||
tst \rd, #0x04
|
||||
beq 1001b
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro busyuart, rd, rx
|
||||
|
@ -24,7 +24,7 @@ config SOC_SAMA5
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MEMORY
|
||||
select ATMEL_SDRAMC
|
||||
select PHYLIB if NETDEVICES
|
||||
select SRAM if PM
|
||||
|
||||
menu "Atmel AT91 System-on-Chip"
|
||||
|
||||
@ -81,6 +81,8 @@ config SOC_AT91RM9200
|
||||
select CPU_ARM920T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_USB_CLK
|
||||
select MIGHT_HAVE_PCI
|
||||
select SRAM if PM
|
||||
|
||||
config SOC_AT91SAM9
|
||||
bool "AT91SAM9"
|
||||
@ -94,6 +96,7 @@ config SOC_AT91SAM9
|
||||
select HAVE_AT91_UTMI
|
||||
select HAVE_FB_ATMEL
|
||||
select MEMORY
|
||||
select SRAM if PM
|
||||
help
|
||||
Select this if you are using one of those Atmel SoC:
|
||||
AT91SAM9260
|
||||
@ -116,20 +119,6 @@ endif # SOC_SAM_V4_V5
|
||||
|
||||
comment "AT91 Feature Selections"
|
||||
|
||||
config AT91_SLOW_CLOCK
|
||||
bool "Suspend-to-RAM disables main oscillator"
|
||||
select SRAM
|
||||
depends on SUSPEND
|
||||
help
|
||||
Select this if you want Suspend-to-RAM to save the most power
|
||||
possible (without powering off the CPU) by disabling the PLLs
|
||||
and main oscillator so that only the 32 KiHz clock is available.
|
||||
|
||||
When only that slow-clock is available, some peripherals lose
|
||||
functionality. Many can't issue wakeup events unless faster
|
||||
clocks are available. Some lose their operating state and
|
||||
need to be completely re-initialized.
|
||||
|
||||
config AT91_TIMER_HZ
|
||||
int "Kernel HZ (jiffies per second)"
|
||||
range 32 1024
|
||||
|
@ -2,7 +2,7 @@
|
||||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
obj-y := setup.o
|
||||
obj-y := soc.o
|
||||
|
||||
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
|
||||
|
||||
@ -13,7 +13,7 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o
|
||||
|
||||
# Power Management
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
|
||||
obj-$(CONFIG_PM) += pm_suspend.o
|
||||
|
||||
ifeq ($(CONFIG_PM_DEBUG),y)
|
||||
CFLAGS_pm.o += -DDEBUG
|
||||
|
@ -8,25 +8,22 @@
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include <mach/at91_st.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "soc.h"
|
||||
|
||||
static const struct at91_soc rm9200_socs[] = {
|
||||
AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
|
||||
{
|
||||
@ -45,15 +42,20 @@ static void __init at91rm9200_dt_timer_init(void)
|
||||
|
||||
static void __init at91rm9200_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
struct soc_device *soc;
|
||||
struct device *soc_dev = NULL;
|
||||
|
||||
soc = at91_soc_init(rm9200_socs);
|
||||
if (soc != NULL)
|
||||
soc_dev = soc_device_to_device(soc);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
|
||||
|
||||
arm_pm_idle = at91rm9200_idle;
|
||||
arm_pm_restart = at91rm9200_restart;
|
||||
at91rm9200_pm_init();
|
||||
}
|
||||
|
||||
|
||||
|
||||
static const char *at91rm9200_dt_board_compat[] __initconst = {
|
||||
"atmel,at91rm9200",
|
||||
NULL
|
||||
@ -61,7 +63,6 @@ static const char *at91rm9200_dt_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200")
|
||||
.init_time = at91rm9200_dt_timer_init,
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = at91rm9200_dt_device_init,
|
||||
.dt_compat = at91rm9200_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
@ -7,29 +7,68 @@
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "soc.h"
|
||||
|
||||
static const struct at91_soc at91sam9_socs[] = {
|
||||
AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
|
||||
AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
|
||||
AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
|
||||
AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
|
||||
AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
|
||||
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
|
||||
"at91sam9m11", "at91sam9g45"),
|
||||
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
|
||||
"at91sam9m10", "at91sam9g45"),
|
||||
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
|
||||
"at91sam9g46", "at91sam9g45"),
|
||||
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
|
||||
"at91sam9g45", "at91sam9g45"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
|
||||
"at91sam9g15", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
|
||||
"at91sam9g35", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
|
||||
"at91sam9x35", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
|
||||
"at91sam9g25", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
|
||||
"at91sam9x25", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
|
||||
"at91sam9cn12", "at91sam9n12"),
|
||||
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
|
||||
"at91sam9n12", "at91sam9n12"),
|
||||
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
|
||||
"at91sam9cn11", "at91sam9n12"),
|
||||
AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
|
||||
AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
|
||||
AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static void __init at91sam9_common_init(void)
|
||||
{
|
||||
struct soc_device *soc;
|
||||
struct device *soc_dev = NULL;
|
||||
|
||||
soc = at91_soc_init(at91sam9_socs);
|
||||
if (soc != NULL)
|
||||
soc_dev = soc_device_to_device(soc);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
}
|
||||
|
||||
static void __init at91sam9_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91sam9_common_init();
|
||||
at91sam9260_pm_init();
|
||||
}
|
||||
|
||||
@ -40,16 +79,13 @@ static const char *at91_dt_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = at91sam9_dt_device_init,
|
||||
.dt_compat = at91_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
static void __init at91sam9g45_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91sam9_common_init();
|
||||
at91sam9g45_pm_init();
|
||||
}
|
||||
|
||||
@ -60,16 +96,13 @@ static const char *at91sam9g45_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = at91sam9g45_dt_device_init,
|
||||
.dt_compat = at91sam9g45_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
static void __init at91sam9x5_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91sam9_common_init();
|
||||
at91sam9x5_pm_init();
|
||||
}
|
||||
|
||||
@ -81,7 +114,6 @@ static const char *at91sam9x5_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = at91sam9x5_dt_device_init,
|
||||
.dt_compat = at91sam9x5_board_compat,
|
||||
MACHINE_END
|
||||
|
@ -25,10 +25,6 @@ extern void at91rm9200_timer_init(void);
|
||||
extern void at91rm9200_idle(void);
|
||||
extern void at91sam9_idle(void);
|
||||
|
||||
/* Matrix */
|
||||
extern void at91_ioremap_matrix(u32 base_addr);
|
||||
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void __init at91rm9200_pm_init(void);
|
||||
extern void __init at91sam9260_pm_init(void);
|
||||
|
@ -1,23 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Under GPLv2
|
||||
*/
|
||||
|
||||
#ifndef __MACH_AT91_MATRIX_H__
|
||||
#define __MACH_AT91_MATRIX_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void __iomem *at91_matrix_base;
|
||||
|
||||
#define at91_matrix_read(field) \
|
||||
__raw_readl(at91_matrix_base + field)
|
||||
|
||||
#define at91_matrix_write(field, value) \
|
||||
__raw_writel(value, at91_matrix_base + field)
|
||||
|
||||
#else
|
||||
.extern at91_matrix_base
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_AT91_MATRIX_H__ */
|
@ -1,80 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9260 datasheet revision B.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_MATRIX_H
|
||||
#define AT91SAM9260_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#endif
|
@ -1,64 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9261_MATRIX_H
|
||||
#define AT91SAM9261_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
|
||||
#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_ITCM_64 (7 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
|
||||
#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
|
||||
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
|
||||
|
||||
#endif
|
@ -1,129 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
|
||||
*
|
||||
* Copyright (C) 2006 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9263_MATRIX_H
|
||||
#define AT91SAM9263_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
|
||||
#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
|
||||
#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
|
||||
#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
|
||||
#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
|
||||
#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
|
||||
#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
|
||||
#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||
|
||||
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||
|
||||
#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#endif
|
@ -1,153 +0,0 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9G45 family
|
||||
*
|
||||
* Copyright (C) 2008-2009 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9G45 preliminary datasheet.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9G45_MATRIX_H
|
||||
#define AT91SAM9G45_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
|
||||
#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
|
||||
#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
|
||||
#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
|
||||
#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
|
||||
#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
|
||||
#define AT91_MATRIX_ULBT_128 (7 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
|
||||
#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
|
||||
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
|
||||
#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
|
||||
#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
|
||||
#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
|
||||
#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
||||
|
||||
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||
#define AT91_MATRIX_RCB9 (1 << 9)
|
||||
#define AT91_MATRIX_RCB10 (1 << 10)
|
||||
#define AT91_MATRIX_RCB11 (1 << 11)
|
||||
|
||||
#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||
#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
|
||||
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
|
||||
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
|
||||
|
||||
#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
|
||||
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
|
||||
#define AT91C_VDEC_SEL_OFF (0 << 0)
|
||||
#define AT91C_VDEC_SEL_ON (1 << 0)
|
||||
|
||||
#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
|
||||
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
|
||||
#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
@ -1,53 +0,0 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9N12
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation.
|
||||
*
|
||||
* Only EBI related registers.
|
||||
* Write Protect register definitions may be useful.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _AT91SAM9N12_MATRIX_H_
|
||||
#define _AT91SAM9N12_MATRIX_H_
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
@ -1,96 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9RL_MATRIX_H
|
||||
#define AT91SAM9RL_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
|
||||
#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
|
||||
#endif
|
@ -1,53 +0,0 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||
*
|
||||
* Only EBI related registers.
|
||||
* Write Protect register definitions may be useful.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9X5_MATRIX_H
|
||||
#define AT91SAM9X5_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/io.h
|
||||
*
|
||||
* Copyright (C) 2003 SAN People
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#define IO_SPACE_LIMIT 0xFFFFFFFF
|
||||
#define __io(a) __typesafe_io(a)
|
||||
|
||||
#endif
|
@ -29,6 +29,8 @@
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/fncpy.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/hardware.h>
|
||||
@ -41,7 +43,6 @@ static struct {
|
||||
int memctrl;
|
||||
} at91_pm_data;
|
||||
|
||||
static void (*at91_pm_standby)(void);
|
||||
void __iomem *at91_ramc_base[2];
|
||||
|
||||
static int at91_pm_valid_state(suspend_state_t state)
|
||||
@ -119,15 +120,28 @@ int at91_suspend_entering_slow_clock(void)
|
||||
}
|
||||
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
|
||||
|
||||
|
||||
static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
|
||||
static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
|
||||
void __iomem *ramc1, int memctrl);
|
||||
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
|
||||
extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
|
||||
void __iomem *ramc1, int memctrl);
|
||||
extern u32 at91_slow_clock_sz;
|
||||
#endif
|
||||
extern u32 at91_pm_suspend_in_sram_sz;
|
||||
|
||||
static void at91_pm_suspend(suspend_state_t state)
|
||||
{
|
||||
unsigned int pm_data = at91_pm_data.memctrl;
|
||||
|
||||
pm_data |= (state == PM_SUSPEND_MEM) ?
|
||||
AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
|
||||
|
||||
flush_cache_all();
|
||||
outer_disable();
|
||||
|
||||
at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
|
||||
at91_ramc_base[1], pm_data);
|
||||
|
||||
outer_resume();
|
||||
}
|
||||
|
||||
static int at91_pm_enter(suspend_state_t state)
|
||||
{
|
||||
@ -136,8 +150,8 @@ static int at91_pm_enter(suspend_state_t state)
|
||||
switch (state) {
|
||||
/*
|
||||
* Suspend-to-RAM is like STANDBY plus slow clock mode, so
|
||||
* drivers must suspend more deeply: only the master clock
|
||||
* controller may be using the main oscillator.
|
||||
* drivers must suspend more deeply, the master clock switches
|
||||
* to the clk32k and turns off the main oscillator
|
||||
*/
|
||||
case PM_SUSPEND_MEM:
|
||||
/*
|
||||
@ -146,23 +160,9 @@ static int at91_pm_enter(suspend_state_t state)
|
||||
if (!at91_pm_verify_clocks())
|
||||
goto error;
|
||||
|
||||
/*
|
||||
* Enter slow clock mode by switching over to clk32k and
|
||||
* turning off the main oscillator; reverse on wakeup.
|
||||
*/
|
||||
if (slow_clock) {
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
/* copy slow_clock handler to SRAM, and call it */
|
||||
memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
|
||||
#endif
|
||||
slow_clock(at91_pmc_base, at91_ramc_base[0],
|
||||
at91_ramc_base[1],
|
||||
at91_pm_data.memctrl);
|
||||
at91_pm_suspend(state);
|
||||
|
||||
break;
|
||||
} else {
|
||||
pr_info("AT91: PM - no slow clock mode enabled ...\n");
|
||||
/* FALLTHROUGH leaving master clock alone */
|
||||
}
|
||||
|
||||
/*
|
||||
* STANDBY mode has *all* drivers suspended; ignores irqs not
|
||||
@ -171,15 +171,7 @@ static int at91_pm_enter(suspend_state_t state)
|
||||
* nothing fancy done with main or cpu clocks.
|
||||
*/
|
||||
case PM_SUSPEND_STANDBY:
|
||||
/*
|
||||
* NOTE: the Wait-for-Interrupt instruction needs to be
|
||||
* in icache so no SDRAM accesses are needed until the
|
||||
* wakeup IRQ occurs and self-refresh is terminated.
|
||||
* For ARM 926 based chips, this requirement is weaker
|
||||
* as at91sam9 can access a RAM in self-refresh mode.
|
||||
*/
|
||||
if (at91_pm_standby)
|
||||
at91_pm_standby();
|
||||
at91_pm_suspend(state);
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_ON:
|
||||
@ -218,12 +210,10 @@ static struct platform_device at91_cpuidle_device = {
|
||||
.name = "cpuidle-at91",
|
||||
};
|
||||
|
||||
void at91_pm_set_standby(void (*at91_standby)(void))
|
||||
static void at91_pm_set_standby(void (*at91_standby)(void))
|
||||
{
|
||||
if (at91_standby) {
|
||||
if (at91_standby)
|
||||
at91_cpuidle_device.dev.platform_data = at91_standby;
|
||||
at91_pm_standby = at91_standby;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct of_device_id ramc_ids[] __initconst = {
|
||||
@ -263,7 +253,6 @@ static __init void at91_dt_ramc(void)
|
||||
at91_pm_set_standby(standby);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
static void __init at91_pm_sram_init(void)
|
||||
{
|
||||
struct gen_pool *sram_pool;
|
||||
@ -291,30 +280,36 @@ static void __init at91_pm_sram_init(void)
|
||||
return;
|
||||
}
|
||||
|
||||
sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
|
||||
sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
|
||||
if (!sram_base) {
|
||||
pr_warn("%s: unable to alloc ocram!\n", __func__);
|
||||
pr_warn("%s: unable to alloc sram!\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
|
||||
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
|
||||
}
|
||||
#endif
|
||||
at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
|
||||
at91_pm_suspend_in_sram_sz, false);
|
||||
if (!at91_suspend_sram_fn) {
|
||||
pr_warn("SRAM: Could not map\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Copy the pm suspend handler to SRAM */
|
||||
at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
|
||||
&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
|
||||
}
|
||||
|
||||
static void __init at91_pm_init(void)
|
||||
{
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
at91_pm_sram_init();
|
||||
#endif
|
||||
|
||||
pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
|
||||
|
||||
if (at91_cpuidle_device.dev.platform_data)
|
||||
platform_device_register(&at91_cpuidle_device);
|
||||
|
||||
if (at91_suspend_sram_fn)
|
||||
suspend_set_ops(&at91_pm_ops);
|
||||
else
|
||||
pr_info("AT91: PM not supported, due to no SRAM allocated\n");
|
||||
}
|
||||
|
||||
void __init at91rm9200_pm_init(void)
|
||||
|
@ -15,11 +15,13 @@
|
||||
|
||||
#include <mach/at91_ramc.h>
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void at91_pm_set_standby(void (*at91_standby)(void));
|
||||
#else
|
||||
static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
|
||||
#endif
|
||||
#define AT91_PM_MEMTYPE_MASK 0x0f
|
||||
|
||||
#define AT91_PM_MODE_OFFSET 4
|
||||
#define AT91_PM_MODE_MASK 0x01
|
||||
#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
|
||||
|
||||
#define AT91_PM_SLOW_CLOCK 0x01
|
||||
|
||||
/*
|
||||
* The AT91RM9200 goes into self-refresh mode with this command, and will
|
||||
@ -31,6 +33,7 @@ static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
|
||||
* still in self-refresh is "not recommended", but seems to work.
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
static inline void at91rm9200_standby(void)
|
||||
{
|
||||
u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
|
||||
@ -112,3 +115,4 @@ static inline void at91sam9_sdram_standby(void)
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
@ -1,335 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/pm_slow_clock.S
|
||||
*
|
||||
* Copyright (C) 2006 Savin Zlobec
|
||||
*
|
||||
* AT91SAM9 support:
|
||||
* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/clk/at91_pmc.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/at91_ramc.h>
|
||||
|
||||
/*
|
||||
* When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
|
||||
* clock during suspend by adjusting its prescalar and divisor.
|
||||
* NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
|
||||
* are errata regarding adjusting the prescalar and divisor.
|
||||
*/
|
||||
#undef SLOWDOWN_MASTER_CLOCK
|
||||
|
||||
pmc .req r0
|
||||
sdramc .req r1
|
||||
ramc1 .req r2
|
||||
memctrl .req r3
|
||||
tmp1 .req r4
|
||||
tmp2 .req r5
|
||||
|
||||
/*
|
||||
* Wait until master clock is ready (after switching master clock source)
|
||||
*/
|
||||
.macro wait_mckrdy
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MCKRDY
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until master oscillator has stabilized.
|
||||
*/
|
||||
.macro wait_moscrdy
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MOSCS
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until PLLA has locked.
|
||||
*/
|
||||
.macro wait_pllalock
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKA
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until PLLB has locked.
|
||||
*/
|
||||
.macro wait_pllblock
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKB
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
.arm
|
||||
|
||||
/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
|
||||
* void __iomem *ramc1, int memctrl)
|
||||
*/
|
||||
ENTRY(at91_slow_clock)
|
||||
/* Save registers on stack */
|
||||
stmfd sp!, {r4 - r12, lr}
|
||||
|
||||
/*
|
||||
* Register usage:
|
||||
* R0 = Base address of AT91_PMC
|
||||
* R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
|
||||
* R2 = Base address of second RAM Controller or 0 if not present
|
||||
* R3 = Memory controller
|
||||
* R4 = temporary register
|
||||
* R5 = temporary register
|
||||
*/
|
||||
|
||||
/* Drain write buffer */
|
||||
mov tmp1, #0
|
||||
mcr p15, 0, tmp1, c7, c10, 4
|
||||
|
||||
cmp memctrl, #AT91_MEMCTRL_MC
|
||||
bne ddr_sr_enable
|
||||
|
||||
/*
|
||||
* at91rm9200 Memory controller
|
||||
*/
|
||||
/* Put SDRAM in self-refresh mode */
|
||||
mov tmp1, #1
|
||||
str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
|
||||
b sdr_sr_done
|
||||
|
||||
/*
|
||||
* DDRSDR Memory controller
|
||||
*/
|
||||
ddr_sr_enable:
|
||||
cmp memctrl, #AT91_MEMCTRL_DDRSDR
|
||||
bne sdr_sr_enable
|
||||
|
||||
/* LPDDR1 --> force DDR2 mode during self-refresh */
|
||||
ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
|
||||
str tmp1, .saved_sam9_mdr
|
||||
bic tmp1, tmp1, #~AT91_DDRSDRC_MD
|
||||
cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
||||
ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
|
||||
biceq tmp1, tmp1, #AT91_DDRSDRC_MD
|
||||
orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
|
||||
streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
|
||||
|
||||
/* prepare for DDRAM self-refresh mode */
|
||||
ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
str tmp1, .saved_sam9_lpr
|
||||
bic tmp1, #AT91_DDRSDRC_LPCB
|
||||
orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
|
||||
/* figure out if we use the second ram controller */
|
||||
cmp ramc1, #0
|
||||
beq ddr_no_2nd_ctrl
|
||||
|
||||
ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
|
||||
str tmp2, .saved_sam9_mdr1
|
||||
bic tmp2, tmp2, #~AT91_DDRSDRC_MD
|
||||
cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
||||
ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
|
||||
biceq tmp2, tmp2, #AT91_DDRSDRC_MD
|
||||
orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
|
||||
streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
|
||||
|
||||
ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
str tmp2, .saved_sam9_lpr1
|
||||
bic tmp2, #AT91_DDRSDRC_LPCB
|
||||
orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
|
||||
/* Enable DDRAM self-refresh mode */
|
||||
str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
ddr_no_2nd_ctrl:
|
||||
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
|
||||
b sdr_sr_done
|
||||
|
||||
/*
|
||||
* SDRAMC Memory controller
|
||||
*/
|
||||
sdr_sr_enable:
|
||||
/* Enable SDRAM self-refresh mode */
|
||||
ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||
str tmp1, .saved_sam9_lpr
|
||||
|
||||
bic tmp1, #AT91_SDRAMC_LPCB
|
||||
orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
||||
str tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||
|
||||
sdr_sr_done:
|
||||
/* Save Master clock setting */
|
||||
ldr tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
str tmp1, .saved_mckr
|
||||
|
||||
/*
|
||||
* Set the Master clock source to slow clock
|
||||
*/
|
||||
bic tmp1, tmp1, #AT91_PMC_CSS
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
#ifdef SLOWDOWN_MASTER_CLOCK
|
||||
/*
|
||||
* Set the Master Clock PRES and MDIV fields.
|
||||
*
|
||||
* See AT91RM9200 errata #27 and #28 for details.
|
||||
*/
|
||||
mov tmp1, #0
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
#endif
|
||||
|
||||
/* Save PLLA setting and disable it */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
str tmp1, .saved_pllar
|
||||
|
||||
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
/* Save PLLB setting and disable it */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
str tmp1, .saved_pllbr
|
||||
|
||||
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
|
||||
/* Turn off the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
bic tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
orr tmp1, tmp1, #AT91_PMC_KEY
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
/* Wait for interrupt */
|
||||
mcr p15, 0, tmp1, c7, c0, 4
|
||||
|
||||
/* Turn on the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
orr tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
orr tmp1, tmp1, #AT91_PMC_KEY
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
wait_moscrdy
|
||||
|
||||
/* Restore PLLB setting */
|
||||
ldr tmp1, .saved_pllbr
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
|
||||
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||
bne 1f
|
||||
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
|
||||
beq 2f
|
||||
1:
|
||||
wait_pllblock
|
||||
2:
|
||||
|
||||
/* Restore PLLA setting */
|
||||
ldr tmp1, .saved_pllar
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||
bne 3f
|
||||
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
|
||||
beq 4f
|
||||
3:
|
||||
wait_pllalock
|
||||
4:
|
||||
|
||||
#ifdef SLOWDOWN_MASTER_CLOCK
|
||||
/*
|
||||
* First set PRES if it was not 0,
|
||||
* than set CSS and MDIV fields.
|
||||
*
|
||||
* See AT91RM9200 errata #27 and #28 for details.
|
||||
*/
|
||||
ldr tmp1, .saved_mckr
|
||||
tst tmp1, #AT91_PMC_PRES
|
||||
beq 2f
|
||||
and tmp1, tmp1, #AT91_PMC_PRES
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Restore master clock setting
|
||||
*/
|
||||
2: ldr tmp1, .saved_mckr
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
/*
|
||||
* at91rm9200 Memory controller
|
||||
* Do nothing - self-refresh is automatically disabled.
|
||||
*/
|
||||
cmp memctrl, #AT91_MEMCTRL_MC
|
||||
beq ram_restored
|
||||
|
||||
/*
|
||||
* DDRSDR Memory controller
|
||||
*/
|
||||
cmp memctrl, #AT91_MEMCTRL_DDRSDR
|
||||
bne sdr_en_restore
|
||||
/* Restore MDR in case of LPDDR1 */
|
||||
ldr tmp1, .saved_sam9_mdr
|
||||
str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
|
||||
/* Restore LPR on AT91 with DDRAM */
|
||||
ldr tmp1, .saved_sam9_lpr
|
||||
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
|
||||
/* if we use the second ram controller */
|
||||
cmp ramc1, #0
|
||||
ldrne tmp2, .saved_sam9_mdr1
|
||||
strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
|
||||
ldrne tmp2, .saved_sam9_lpr1
|
||||
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
|
||||
b ram_restored
|
||||
|
||||
/*
|
||||
* SDRAMC Memory controller
|
||||
*/
|
||||
sdr_en_restore:
|
||||
/* Restore LPR on AT91 with SDRAM */
|
||||
ldr tmp1, .saved_sam9_lpr
|
||||
str tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||
|
||||
ram_restored:
|
||||
/* Restore registers, and return */
|
||||
ldmfd sp!, {r4 - r12, pc}
|
||||
|
||||
|
||||
.saved_mckr:
|
||||
.word 0
|
||||
|
||||
.saved_pllar:
|
||||
.word 0
|
||||
|
||||
.saved_pllbr:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_lpr:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_lpr1:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_mdr:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_mdr1:
|
||||
.word 0
|
||||
|
||||
ENTRY(at91_slow_clock_sz)
|
||||
.word .-at91_slow_clock
|
338
arch/arm/mach-at91/pm_suspend.S
Normal file
338
arch/arm/mach-at91/pm_suspend.S
Normal file
@ -0,0 +1,338 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/pm_slow_clock.S
|
||||
*
|
||||
* Copyright (C) 2006 Savin Zlobec
|
||||
*
|
||||
* AT91SAM9 support:
|
||||
* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/clk/at91_pmc.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/at91_ramc.h>
|
||||
#include "pm.h"
|
||||
|
||||
#define SRAMC_SELF_FRESH_ACTIVE 0x01
|
||||
#define SRAMC_SELF_FRESH_EXIT 0x00
|
||||
|
||||
pmc .req r0
|
||||
tmp1 .req r4
|
||||
tmp2 .req r5
|
||||
|
||||
/*
|
||||
* Wait until master clock is ready (after switching master clock source)
|
||||
*/
|
||||
.macro wait_mckrdy
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MCKRDY
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until master oscillator has stabilized.
|
||||
*/
|
||||
.macro wait_moscrdy
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MOSCS
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until PLLA has locked.
|
||||
*/
|
||||
.macro wait_pllalock
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKA
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Put the processor to enter the idle state
|
||||
*/
|
||||
.macro at91_cpu_idle
|
||||
|
||||
#if defined(CONFIG_CPU_V7)
|
||||
mov tmp1, #AT91_PMC_PCK
|
||||
str tmp1, [pmc, #AT91_PMC_SCDR]
|
||||
|
||||
dsb
|
||||
|
||||
wfi @ Wait For Interrupt
|
||||
#else
|
||||
mcr p15, 0, tmp1, c7, c0, 4
|
||||
#endif
|
||||
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
.arm
|
||||
|
||||
/*
|
||||
* void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc,
|
||||
* void __iomem *ramc1, int memctrl)
|
||||
* @input param:
|
||||
* @r0: base address of AT91_PMC
|
||||
* @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
|
||||
* @r2: base address of second SDRAM Controller or 0 if not present
|
||||
* @r3: pm information
|
||||
*/
|
||||
ENTRY(at91_pm_suspend_in_sram)
|
||||
/* Save registers on stack */
|
||||
stmfd sp!, {r4 - r12, lr}
|
||||
|
||||
/* Drain write buffer */
|
||||
mov tmp1, #0
|
||||
mcr p15, 0, tmp1, c7, c10, 4
|
||||
|
||||
str r0, .pmc_base
|
||||
str r1, .sramc_base
|
||||
str r2, .sramc1_base
|
||||
|
||||
and r0, r3, #AT91_PM_MEMTYPE_MASK
|
||||
str r0, .memtype
|
||||
|
||||
lsr r0, r3, #AT91_PM_MODE_OFFSET
|
||||
and r0, r0, #AT91_PM_MODE_MASK
|
||||
str r0, .pm_mode
|
||||
|
||||
/* Active the self-refresh mode */
|
||||
mov r0, #SRAMC_SELF_FRESH_ACTIVE
|
||||
bl at91_sramc_self_refresh
|
||||
|
||||
ldr r0, .pm_mode
|
||||
tst r0, #AT91_PM_SLOW_CLOCK
|
||||
beq skip_disable_main_clock
|
||||
|
||||
ldr pmc, .pmc_base
|
||||
|
||||
/* Save Master clock setting */
|
||||
ldr tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
str tmp1, .saved_mckr
|
||||
|
||||
/*
|
||||
* Set the Master clock source to slow clock
|
||||
*/
|
||||
bic tmp1, tmp1, #AT91_PMC_CSS
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
/* Save PLLA setting and disable it */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
str tmp1, .saved_pllar
|
||||
|
||||
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
/* Turn off the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
bic tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
orr tmp1, tmp1, #AT91_PMC_KEY
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
skip_disable_main_clock:
|
||||
ldr pmc, .pmc_base
|
||||
|
||||
/* Wait for interrupt */
|
||||
at91_cpu_idle
|
||||
|
||||
ldr r0, .pm_mode
|
||||
tst r0, #AT91_PM_SLOW_CLOCK
|
||||
beq skip_enable_main_clock
|
||||
|
||||
ldr pmc, .pmc_base
|
||||
|
||||
/* Turn on the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
orr tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
orr tmp1, tmp1, #AT91_PMC_KEY
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
wait_moscrdy
|
||||
|
||||
/* Restore PLLA setting */
|
||||
ldr tmp1, .saved_pllar
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||
bne 3f
|
||||
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
|
||||
beq 4f
|
||||
3:
|
||||
wait_pllalock
|
||||
4:
|
||||
|
||||
/*
|
||||
* Restore master clock setting
|
||||
*/
|
||||
ldr tmp1, .saved_mckr
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
skip_enable_main_clock:
|
||||
/* Exit the self-refresh mode */
|
||||
mov r0, #SRAMC_SELF_FRESH_EXIT
|
||||
bl at91_sramc_self_refresh
|
||||
|
||||
/* Restore registers, and return */
|
||||
ldmfd sp!, {r4 - r12, pc}
|
||||
ENDPROC(at91_pm_suspend_in_sram)
|
||||
|
||||
/*
|
||||
* void at91_sramc_self_refresh(unsigned int is_active)
|
||||
*
|
||||
* @input param:
|
||||
* @r0: 1 - active self-refresh mode
|
||||
* 0 - exit self-refresh mode
|
||||
* register usage:
|
||||
* @r1: memory type
|
||||
* @r2: base address of the sram controller
|
||||
*/
|
||||
|
||||
ENTRY(at91_sramc_self_refresh)
|
||||
ldr r1, .memtype
|
||||
ldr r2, .sramc_base
|
||||
|
||||
cmp r1, #AT91_MEMCTRL_MC
|
||||
bne ddrc_sf
|
||||
|
||||
/*
|
||||
* at91rm9200 Memory controller
|
||||
*/
|
||||
|
||||
/*
|
||||
* For exiting the self-refresh mode, do nothing,
|
||||
* automatically exit the self-refresh mode.
|
||||
*/
|
||||
tst r0, #SRAMC_SELF_FRESH_ACTIVE
|
||||
beq exit_sramc_sf
|
||||
|
||||
/* Active SDRAM self-refresh mode */
|
||||
mov r3, #1
|
||||
str r3, [r2, #AT91RM9200_SDRAMC_SRR]
|
||||
b exit_sramc_sf
|
||||
|
||||
ddrc_sf:
|
||||
cmp r1, #AT91_MEMCTRL_DDRSDR
|
||||
bne sdramc_sf
|
||||
|
||||
/*
|
||||
* DDR Memory controller
|
||||
*/
|
||||
tst r0, #SRAMC_SELF_FRESH_ACTIVE
|
||||
beq ddrc_exit_sf
|
||||
|
||||
/* LPDDR1 --> force DDR2 mode during self-refresh */
|
||||
ldr r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
str r3, .saved_sam9_mdr
|
||||
bic r3, r3, #~AT91_DDRSDRC_MD
|
||||
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
||||
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
biceq r3, r3, #AT91_DDRSDRC_MD
|
||||
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
|
||||
streq r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
|
||||
/* Active DDRC self-refresh mode */
|
||||
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
str r3, .saved_sam9_lpr
|
||||
bic r3, r3, #AT91_DDRSDRC_LPCB
|
||||
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
/* If using the 2nd ddr controller */
|
||||
ldr r2, .sramc1_base
|
||||
cmp r2, #0
|
||||
beq no_2nd_ddrc
|
||||
|
||||
ldr r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
str r3, .saved_sam9_mdr1
|
||||
bic r3, r3, #~AT91_DDRSDRC_MD
|
||||
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
||||
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
biceq r3, r3, #AT91_DDRSDRC_MD
|
||||
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
|
||||
streq r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
|
||||
/* Active DDRC self-refresh mode */
|
||||
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
str r3, .saved_sam9_lpr1
|
||||
bic r3, r3, #AT91_DDRSDRC_LPCB
|
||||
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
no_2nd_ddrc:
|
||||
b exit_sramc_sf
|
||||
|
||||
ddrc_exit_sf:
|
||||
/* Restore MDR in case of LPDDR1 */
|
||||
ldr r3, .saved_sam9_mdr
|
||||
str r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
/* Restore LPR on AT91 with DDRAM */
|
||||
ldr r3, .saved_sam9_lpr
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
/* If using the 2nd ddr controller */
|
||||
ldr r2, .sramc1_base
|
||||
cmp r2, #0
|
||||
ldrne r3, .saved_sam9_mdr1
|
||||
strne r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
ldrne r3, .saved_sam9_lpr1
|
||||
strne r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
b exit_sramc_sf
|
||||
|
||||
/*
|
||||
* SDRAMC Memory controller
|
||||
*/
|
||||
sdramc_sf:
|
||||
tst r0, #SRAMC_SELF_FRESH_ACTIVE
|
||||
beq sdramc_exit_sf
|
||||
|
||||
/* Active SDRAMC self-refresh mode */
|
||||
ldr r3, [r2, #AT91_SDRAMC_LPR]
|
||||
str r3, .saved_sam9_lpr
|
||||
bic r3, r3, #AT91_SDRAMC_LPCB
|
||||
orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
||||
|
||||
sdramc_exit_sf:
|
||||
ldr r3, .saved_sam9_lpr
|
||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
||||
|
||||
exit_sramc_sf:
|
||||
mov pc, lr
|
||||
ENDPROC(at91_sramc_self_refresh)
|
||||
|
||||
.pmc_base:
|
||||
.word 0
|
||||
.sramc_base:
|
||||
.word 0
|
||||
.sramc1_base:
|
||||
.word 0
|
||||
.memtype:
|
||||
.word 0
|
||||
.pm_mode:
|
||||
.word 0
|
||||
.saved_mckr:
|
||||
.word 0
|
||||
.saved_pllar:
|
||||
.word 0
|
||||
.saved_sam9_lpr:
|
||||
.word 0
|
||||
.saved_sam9_lpr1:
|
||||
.word 0
|
||||
.saved_sam9_mdr:
|
||||
.word 0
|
||||
.saved_sam9_mdr1:
|
||||
.word 0
|
||||
|
||||
ENTRY(at91_pm_suspend_in_sram_sz)
|
||||
.word .-at91_pm_suspend_in_sram
|
@ -7,48 +7,50 @@
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "soc.h"
|
||||
|
||||
static int ksz8081_phy_fixup(struct phy_device *phy)
|
||||
{
|
||||
int value;
|
||||
|
||||
value = phy_read(phy, 0x16);
|
||||
value &= ~0x20;
|
||||
phy_write(phy, 0x16, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static const struct at91_soc sama5_socs[] = {
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
|
||||
"sama5d31", "sama5d3"),
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
|
||||
"sama5d33", "sama5d3"),
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
|
||||
"sama5d34", "sama5d3"),
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
|
||||
"sama5d35", "sama5d3"),
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
|
||||
"sama5d36", "sama5d3"),
|
||||
AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
|
||||
"sama5d41", "sama5d4"),
|
||||
AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
|
||||
"sama5d42", "sama5d4"),
|
||||
AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
|
||||
"sama5d43", "sama5d4"),
|
||||
AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
|
||||
"sama5d44", "sama5d4"),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static void __init sama5_dt_device_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("atmel,sama5d4ek") &&
|
||||
IS_ENABLED(CONFIG_PHYLIB)) {
|
||||
phy_register_fixup_for_id("fc028000.etherne:00",
|
||||
ksz8081_phy_fixup);
|
||||
}
|
||||
struct soc_device *soc;
|
||||
struct device *soc_dev = NULL;
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
soc = at91_soc_init(sama5_socs);
|
||||
if (soc != NULL)
|
||||
soc_dev = soc_device_to_device(soc);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
|
||||
at91sam9x5_pm_init();
|
||||
}
|
||||
|
||||
@ -59,44 +61,10 @@ static const char *sama5_dt_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(sama5_dt, "Atmel SAMA5")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = sama5_dt_device_init,
|
||||
.dt_compat = sama5_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
static struct map_desc at91_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
|
||||
.pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
|
||||
.length = SZ_512,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
|
||||
.pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
|
||||
.length = SZ_512,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{ /* On sama5d4, we use USART3 as serial console */
|
||||
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
|
||||
.pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
|
||||
.length = SZ_256,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{ /* A bunch of peripheral with fine grained IO space */
|
||||
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
|
||||
.pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
|
||||
.length = SZ_2K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init sama5_alt_map_io(void)
|
||||
{
|
||||
at91_alt_map_io();
|
||||
iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
|
||||
}
|
||||
|
||||
static const char *sama5_alt_dt_board_compat[] __initconst = {
|
||||
"atmel,sama5d4",
|
||||
NULL
|
||||
@ -104,7 +72,6 @@ static const char *sama5_alt_dt_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = sama5_alt_map_io,
|
||||
.init_machine = sama5_dt_device_init,
|
||||
.dt_compat = sama5_alt_dt_board_compat,
|
||||
.l2c_aux_mask = ~0UL,
|
||||
|
@ -1,330 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Under GPLv2
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "AT91: " fmt
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/clk/at91_pmc.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/at91_dbgu.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "pm.h"
|
||||
|
||||
struct at91_socinfo at91_soc_initdata;
|
||||
EXPORT_SYMBOL(at91_soc_initdata);
|
||||
|
||||
static struct map_desc at91_io_desc __initdata __maybe_unused = {
|
||||
.virtual = (unsigned long)AT91_VA_BASE_SYS,
|
||||
.pfn = __phys_to_pfn(AT91_BASE_SYS),
|
||||
.length = SZ_16K,
|
||||
.type = MT_DEVICE,
|
||||
};
|
||||
|
||||
static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
|
||||
.virtual = (unsigned long)AT91_ALT_VA_BASE_SYS,
|
||||
.pfn = __phys_to_pfn(AT91_ALT_BASE_SYS),
|
||||
.length = 24 * SZ_1K,
|
||||
.type = MT_DEVICE,
|
||||
};
|
||||
|
||||
static void __init soc_detect(u32 dbgu_base)
|
||||
{
|
||||
u32 cidr, socid;
|
||||
|
||||
cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
|
||||
socid = cidr & ~AT91_CIDR_VERSION;
|
||||
|
||||
switch (socid) {
|
||||
case ARCH_ID_AT91RM9200:
|
||||
at91_soc_initdata.type = AT91_SOC_RM9200;
|
||||
if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9260:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9260;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9261:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9261;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9263:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9263;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9G20:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9G20;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9G45:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9G45;
|
||||
if (cidr == ARCH_ID_AT91SAM9G45ES)
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9RL64:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9RL;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9X5:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9X5;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9N12:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9N12;
|
||||
break;
|
||||
|
||||
case ARCH_ID_SAMA5:
|
||||
at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
|
||||
if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* at91sam9g10 */
|
||||
if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9G10;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
}
|
||||
/* at91sam9xe */
|
||||
else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9260;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
|
||||
}
|
||||
|
||||
if (!at91_soc_is_detected())
|
||||
return;
|
||||
|
||||
at91_soc_initdata.cidr = cidr;
|
||||
|
||||
/* sub version of soc */
|
||||
if (!at91_soc_initdata.exid)
|
||||
at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_AT91SAM9M10:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9G46:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9M11:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_AT91SAM9G15:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9G35:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9X35:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9G25:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9X25:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_SAMA5D31:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D33:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D34:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D35:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D36:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void __init alt_soc_detect(u32 dbgu_base)
|
||||
{
|
||||
u32 cidr, socid;
|
||||
|
||||
/* SoC ID */
|
||||
cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
|
||||
socid = cidr & ~AT91_CIDR_VERSION;
|
||||
|
||||
switch (socid) {
|
||||
case ARCH_ID_SAMA5:
|
||||
at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
|
||||
if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
|
||||
} else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAMA5D4;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (!at91_soc_is_detected())
|
||||
return;
|
||||
|
||||
at91_soc_initdata.cidr = cidr;
|
||||
|
||||
/* sub version of soc */
|
||||
if (!at91_soc_initdata.exid)
|
||||
at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_SAMA5D41:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D42:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D43:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D44:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const char *soc_name[] = {
|
||||
[AT91_SOC_RM9200] = "at91rm9200",
|
||||
[AT91_SOC_SAM9260] = "at91sam9260",
|
||||
[AT91_SOC_SAM9261] = "at91sam9261",
|
||||
[AT91_SOC_SAM9263] = "at91sam9263",
|
||||
[AT91_SOC_SAM9G10] = "at91sam9g10",
|
||||
[AT91_SOC_SAM9G20] = "at91sam9g20",
|
||||
[AT91_SOC_SAM9G45] = "at91sam9g45",
|
||||
[AT91_SOC_SAM9RL] = "at91sam9rl",
|
||||
[AT91_SOC_SAM9X5] = "at91sam9x5",
|
||||
[AT91_SOC_SAM9N12] = "at91sam9n12",
|
||||
[AT91_SOC_SAMA5D3] = "sama5d3",
|
||||
[AT91_SOC_SAMA5D4] = "sama5d4",
|
||||
[AT91_SOC_UNKNOWN] = "Unknown",
|
||||
};
|
||||
|
||||
const char *at91_get_soc_type(struct at91_socinfo *c)
|
||||
{
|
||||
return soc_name[c->type];
|
||||
}
|
||||
EXPORT_SYMBOL(at91_get_soc_type);
|
||||
|
||||
static const char *soc_subtype_name[] = {
|
||||
[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
|
||||
[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
|
||||
[AT91_SOC_SAM9XE] = "at91sam9xe",
|
||||
[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
|
||||
[AT91_SOC_SAM9M10] = "at91sam9m10",
|
||||
[AT91_SOC_SAM9G46] = "at91sam9g46",
|
||||
[AT91_SOC_SAM9M11] = "at91sam9m11",
|
||||
[AT91_SOC_SAM9G15] = "at91sam9g15",
|
||||
[AT91_SOC_SAM9G35] = "at91sam9g35",
|
||||
[AT91_SOC_SAM9X35] = "at91sam9x35",
|
||||
[AT91_SOC_SAM9G25] = "at91sam9g25",
|
||||
[AT91_SOC_SAM9X25] = "at91sam9x25",
|
||||
[AT91_SOC_SAMA5D31] = "sama5d31",
|
||||
[AT91_SOC_SAMA5D33] = "sama5d33",
|
||||
[AT91_SOC_SAMA5D34] = "sama5d34",
|
||||
[AT91_SOC_SAMA5D35] = "sama5d35",
|
||||
[AT91_SOC_SAMA5D36] = "sama5d36",
|
||||
[AT91_SOC_SAMA5D41] = "sama5d41",
|
||||
[AT91_SOC_SAMA5D42] = "sama5d42",
|
||||
[AT91_SOC_SAMA5D43] = "sama5d43",
|
||||
[AT91_SOC_SAMA5D44] = "sama5d44",
|
||||
[AT91_SOC_SUBTYPE_NONE] = "None",
|
||||
[AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
|
||||
};
|
||||
|
||||
const char *at91_get_soc_subtype(struct at91_socinfo *c)
|
||||
{
|
||||
return soc_subtype_name[c->subtype];
|
||||
}
|
||||
EXPORT_SYMBOL(at91_get_soc_subtype);
|
||||
|
||||
void __init at91_map_io(void)
|
||||
{
|
||||
/* Map peripherals */
|
||||
iotable_init(&at91_io_desc, 1);
|
||||
|
||||
at91_soc_initdata.type = AT91_SOC_UNKNOWN;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
|
||||
|
||||
soc_detect(AT91_BASE_DBGU0);
|
||||
if (!at91_soc_is_detected())
|
||||
soc_detect(AT91_BASE_DBGU1);
|
||||
|
||||
if (!at91_soc_is_detected())
|
||||
panic(pr_fmt("Impossible to detect the SOC type"));
|
||||
|
||||
pr_info("Detected soc type: %s\n",
|
||||
at91_get_soc_type(&at91_soc_initdata));
|
||||
if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
|
||||
pr_info("Detected soc subtype: %s\n",
|
||||
at91_get_soc_subtype(&at91_soc_initdata));
|
||||
}
|
||||
|
||||
void __init at91_alt_map_io(void)
|
||||
{
|
||||
/* Map peripherals */
|
||||
iotable_init(&at91_alt_io_desc, 1);
|
||||
|
||||
at91_soc_initdata.type = AT91_SOC_UNKNOWN;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
|
||||
|
||||
alt_soc_detect(AT91_BASE_DBGU2);
|
||||
if (!at91_soc_is_detected())
|
||||
panic("AT91: Impossible to detect the SOC type");
|
||||
|
||||
pr_info("AT91: Detected soc type: %s\n",
|
||||
at91_get_soc_type(&at91_soc_initdata));
|
||||
if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
|
||||
pr_info("AT91: Detected soc subtype: %s\n",
|
||||
at91_get_soc_subtype(&at91_soc_initdata));
|
||||
}
|
||||
|
||||
void __iomem *at91_matrix_base;
|
||||
EXPORT_SYMBOL_GPL(at91_matrix_base);
|
||||
|
||||
void __init at91_ioremap_matrix(u32 base_addr)
|
||||
{
|
||||
at91_matrix_base = ioremap(base_addr, 512);
|
||||
if (!at91_matrix_base)
|
||||
panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
|
||||
}
|
97
arch/arm/mach-at91/soc.c
Normal file
97
arch/arm/mach-at91/soc.c
Normal file
@ -0,0 +1,97 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Atmel
|
||||
*
|
||||
* Alexandre Belloni <alexandre.belloni@free-electrons.com
|
||||
* Boris Brezillon <boris.brezillon@free-electrons.com
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "AT91: " fmt
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define AT91_DBGU_CIDR 0x40
|
||||
#define AT91_DBGU_CIDR_VERSION(x) ((x) & 0x1f)
|
||||
#define AT91_DBGU_CIDR_EXT BIT(31)
|
||||
#define AT91_DBGU_CIDR_MATCH_MASK 0x7fffffe0
|
||||
#define AT91_DBGU_EXID 0x44
|
||||
|
||||
struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
|
||||
{
|
||||
struct soc_device_attribute *soc_dev_attr;
|
||||
const struct at91_soc *soc;
|
||||
struct soc_device *soc_dev;
|
||||
struct device_node *np;
|
||||
void __iomem *regs;
|
||||
u32 cidr, exid;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
|
||||
if (!np)
|
||||
np = of_find_compatible_node(NULL, NULL,
|
||||
"atmel,at91sam9260-dbgu");
|
||||
|
||||
if (!np) {
|
||||
pr_warn("Could not find DBGU node");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
regs = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
|
||||
if (!regs) {
|
||||
pr_warn("Could not map DBGU iomem range");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cidr = readl(regs + AT91_DBGU_CIDR);
|
||||
exid = readl(regs + AT91_DBGU_EXID);
|
||||
|
||||
iounmap(regs);
|
||||
|
||||
for (soc = socs; soc->name; soc++) {
|
||||
if (soc->cidr_match != (cidr & AT91_DBGU_CIDR_MATCH_MASK))
|
||||
continue;
|
||||
|
||||
if (!(cidr & AT91_DBGU_CIDR_EXT) || soc->exid_match == exid)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!soc->name) {
|
||||
pr_warn("Could not find matching SoC description\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
|
||||
if (!soc_dev_attr)
|
||||
return NULL;
|
||||
|
||||
soc_dev_attr->family = soc->family;
|
||||
soc_dev_attr->soc_id = soc->name;
|
||||
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
|
||||
AT91_DBGU_CIDR_VERSION(cidr));
|
||||
soc_dev = soc_device_register(soc_dev_attr);
|
||||
if (IS_ERR(soc_dev)) {
|
||||
kfree(soc_dev_attr->revision);
|
||||
kfree(soc_dev_attr);
|
||||
pr_warn("Could not register SoC device\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (soc->family)
|
||||
pr_info("Detected SoC family: %s\n", soc->family);
|
||||
pr_info("Detected SoC: %s, revision %X\n", soc->name,
|
||||
AT91_DBGU_CIDR_VERSION(cidr));
|
||||
|
||||
return soc_dev;
|
||||
}
|
78
arch/arm/mach-at91/soc.h
Normal file
78
arch/arm/mach-at91/soc.h
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Atmel
|
||||
*
|
||||
* Boris Brezillon <boris.brezillon@free-electrons.com
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AT91_SOC_H
|
||||
#define __AT91_SOC_H
|
||||
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
struct at91_soc {
|
||||
u32 cidr_match;
|
||||
u32 exid_match;
|
||||
const char *name;
|
||||
const char *family;
|
||||
};
|
||||
|
||||
#define AT91_SOC(__cidr, __exid, __name, __family) \
|
||||
{ \
|
||||
.cidr_match = (__cidr), \
|
||||
.exid_match = (__exid), \
|
||||
.name = (__name), \
|
||||
.family = (__family), \
|
||||
}
|
||||
|
||||
struct soc_device * __init
|
||||
at91_soc_init(const struct at91_soc *socs);
|
||||
|
||||
#define AT91RM9200_CIDR_MATCH 0x09290780
|
||||
|
||||
#define AT91SAM9260_CIDR_MATCH 0x019803a0
|
||||
#define AT91SAM9261_CIDR_MATCH 0x019703a0
|
||||
#define AT91SAM9263_CIDR_MATCH 0x019607a0
|
||||
#define AT91SAM9G20_CIDR_MATCH 0x019905a0
|
||||
#define AT91SAM9RL64_CIDR_MATCH 0x019b03a0
|
||||
#define AT91SAM9G45_CIDR_MATCH 0x019b05a0
|
||||
#define AT91SAM9X5_CIDR_MATCH 0x019a05a0
|
||||
#define AT91SAM9N12_CIDR_MATCH 0x019a07a0
|
||||
|
||||
#define AT91SAM9M11_EXID_MATCH 0x00000001
|
||||
#define AT91SAM9M10_EXID_MATCH 0x00000002
|
||||
#define AT91SAM9G46_EXID_MATCH 0x00000003
|
||||
#define AT91SAM9G45_EXID_MATCH 0x00000004
|
||||
|
||||
#define AT91SAM9G15_EXID_MATCH 0x00000000
|
||||
#define AT91SAM9G35_EXID_MATCH 0x00000001
|
||||
#define AT91SAM9X35_EXID_MATCH 0x00000002
|
||||
#define AT91SAM9G25_EXID_MATCH 0x00000003
|
||||
#define AT91SAM9X25_EXID_MATCH 0x00000004
|
||||
|
||||
#define AT91SAM9CN12_EXID_MATCH 0x00000005
|
||||
#define AT91SAM9N12_EXID_MATCH 0x00000006
|
||||
#define AT91SAM9CN11_EXID_MATCH 0x00000009
|
||||
|
||||
#define AT91SAM9XE128_CIDR_MATCH 0x329973a0
|
||||
#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0
|
||||
#define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0
|
||||
|
||||
#define SAMA5D3_CIDR_MATCH 0x0a5c07c0
|
||||
#define SAMA5D31_EXID_MATCH 0x00444300
|
||||
#define SAMA5D33_EXID_MATCH 0x00414300
|
||||
#define SAMA5D34_EXID_MATCH 0x00414301
|
||||
#define SAMA5D35_EXID_MATCH 0x00584300
|
||||
#define SAMA5D36_EXID_MATCH 0x00004301
|
||||
|
||||
#define SAMA5D4_CIDR_MATCH 0x0a5c07c0
|
||||
#define SAMA5D41_EXID_MATCH 0x00000001
|
||||
#define SAMA5D42_EXID_MATCH 0x00000002
|
||||
#define SAMA5D43_EXID_MATCH 0x00000003
|
||||
#define SAMA5D44_EXID_MATCH 0x00000004
|
||||
|
||||
#endif /* __AT91_SOC_H */
|
@ -21,6 +21,9 @@
|
||||
/* Bases of da830 McASP1 register banks */
|
||||
#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
|
||||
|
||||
/* Bases of da830 McASP2 register banks */
|
||||
#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000
|
||||
|
||||
/* EDMA channels of dm644x and dm355 */
|
||||
#define DAVINCI_DMA_ASP0_TX 2
|
||||
#define DAVINCI_DMA_ASP0_RX 3
|
||||
@ -40,6 +43,10 @@
|
||||
#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
|
||||
#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
|
||||
|
||||
/* EDMA channels of da830 McASP2 */
|
||||
#define DAVINCI_DA830_DMA_MCASP2_AREVT 4
|
||||
#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5
|
||||
|
||||
/* Interrupts */
|
||||
#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
|
||||
#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
|
||||
|
@ -463,16 +463,23 @@ static struct resource da830_mcasp1_resources[] = {
|
||||
},
|
||||
/* TX event */
|
||||
{
|
||||
.name = "tx",
|
||||
.start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
|
||||
.end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
/* RX event */
|
||||
{
|
||||
.name = "rx",
|
||||
.start = DAVINCI_DA830_DMA_MCASP1_AREVT,
|
||||
.end = DAVINCI_DA830_DMA_MCASP1_AREVT,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.name = "common",
|
||||
.start = IRQ_DA8XX_MCASPINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device da830_mcasp1_device = {
|
||||
@ -482,6 +489,41 @@ static struct platform_device da830_mcasp1_device = {
|
||||
.resource = da830_mcasp1_resources,
|
||||
};
|
||||
|
||||
static struct resource da830_mcasp2_resources[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.start = DAVINCI_DA830_MCASP2_REG_BASE,
|
||||
.end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
/* TX event */
|
||||
{
|
||||
.name = "tx",
|
||||
.start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
|
||||
.end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
/* RX event */
|
||||
{
|
||||
.name = "rx",
|
||||
.start = DAVINCI_DA830_DMA_MCASP2_AREVT,
|
||||
.end = DAVINCI_DA830_DMA_MCASP2_AREVT,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.name = "common",
|
||||
.start = IRQ_DA8XX_MCASPINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device da830_mcasp2_device = {
|
||||
.name = "davinci-mcasp",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(da830_mcasp2_resources),
|
||||
.resource = da830_mcasp2_resources,
|
||||
};
|
||||
|
||||
static struct resource da850_mcasp_resources[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
@ -491,16 +533,23 @@ static struct resource da850_mcasp_resources[] = {
|
||||
},
|
||||
/* TX event */
|
||||
{
|
||||
.name = "tx",
|
||||
.start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
|
||||
.end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
/* RX event */
|
||||
{
|
||||
.name = "rx",
|
||||
.start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
|
||||
.end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.name = "common",
|
||||
.start = IRQ_DA8XX_MCASPINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device da850_mcasp_device = {
|
||||
@ -512,14 +561,31 @@ static struct platform_device da850_mcasp_device = {
|
||||
|
||||
void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
|
||||
{
|
||||
/* DA830/OMAP-L137 has 3 instances of McASP */
|
||||
if (cpu_is_davinci_da830() && id == 1) {
|
||||
da830_mcasp1_device.dev.platform_data = pdata;
|
||||
platform_device_register(&da830_mcasp1_device);
|
||||
} else if (cpu_is_davinci_da850()) {
|
||||
da850_mcasp_device.dev.platform_data = pdata;
|
||||
platform_device_register(&da850_mcasp_device);
|
||||
struct platform_device *pdev;
|
||||
|
||||
switch (id) {
|
||||
case 0:
|
||||
/* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
|
||||
pdev = &da850_mcasp_device;
|
||||
break;
|
||||
case 1:
|
||||
/* Valid for DA830/OMAP-L137 only */
|
||||
if (!cpu_is_davinci_da830())
|
||||
return;
|
||||
pdev = &da830_mcasp1_device;
|
||||
break;
|
||||
case 2:
|
||||
/* Valid for DA830/OMAP-L137 only */
|
||||
if (!cpu_is_davinci_da830())
|
||||
return;
|
||||
pdev = &da830_mcasp2_device;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
pdev->dev.platform_data = pdata;
|
||||
platform_device_register(pdev);
|
||||
}
|
||||
|
||||
static struct resource da8xx_pruss_resources[] = {
|
||||
|
@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
|
||||
[IRQ_DM646X_EMACMISCINT] = 7,
|
||||
[IRQ_DM646X_MCASP0TXINT] = 7,
|
||||
[IRQ_DM646X_MCASP0RXINT] = 7,
|
||||
[IRQ_AEMIFINT] = 7,
|
||||
[IRQ_DM646X_RESERVED_3] = 7,
|
||||
[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
|
||||
[IRQ_TINT0_TINT34] = 7, /* clocksource */
|
||||
@ -610,19 +609,31 @@ static struct resource dm646x_mcasp0_resources[] = {
|
||||
.end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
/* first TX, then RX */
|
||||
{
|
||||
.name = "tx",
|
||||
.start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
|
||||
.end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.name = "rx",
|
||||
.start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
|
||||
.end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.name = "tx",
|
||||
.start = IRQ_DM646X_MCASP0TXINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.name = "rx",
|
||||
.start = IRQ_DM646X_MCASP0RXINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
/* DIT mode only, rx is not supported */
|
||||
static struct resource dm646x_mcasp1_resources[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
@ -630,17 +641,16 @@ static struct resource dm646x_mcasp1_resources[] = {
|
||||
.end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
/* DIT mode, only TX event */
|
||||
{
|
||||
.name = "tx",
|
||||
.start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
|
||||
.end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
/* DIT mode, dummy entry */
|
||||
{
|
||||
.start = -1,
|
||||
.end = -1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
.name = "tx",
|
||||
.start = IRQ_DM646X_MCASP1TXINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -129,8 +129,8 @@
|
||||
#define IRQ_DM646X_EMACMISCINT 27
|
||||
#define IRQ_DM646X_MCASP0TXINT 28
|
||||
#define IRQ_DM646X_MCASP0RXINT 29
|
||||
#define IRQ_DM646X_MCASP1TXINT 30
|
||||
#define IRQ_DM646X_RESERVED_3 31
|
||||
#define IRQ_DM646X_MCASP1TXINT 32
|
||||
#define IRQ_DM646X_VLQINT 38
|
||||
#define IRQ_DM646X_UARTINT2 42
|
||||
#define IRQ_DM646X_SPINT0 43
|
||||
|
@ -77,13 +77,6 @@ config SOC_IMX21
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MXC_AVIC
|
||||
|
||||
config SOC_IMX25
|
||||
bool
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select CPU_ARM926T
|
||||
select MXC_AVIC
|
||||
select PINCTRL_IMX25
|
||||
|
||||
config SOC_IMX27
|
||||
bool
|
||||
select CPU_ARM926T
|
||||
@ -149,62 +142,6 @@ config MACH_MX21ADS
|
||||
Include support for MX21ADS platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
comment "MX25 platforms:"
|
||||
|
||||
config MACH_MX25_3DS
|
||||
bool "Support MX25PDK (3DS) Platform"
|
||||
select IMX_HAVE_PLATFORM_FLEXCAN
|
||||
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMXDI_RTC
|
||||
select IMX_HAVE_PLATFORM_IMX_FB
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_KEYPAD
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_MXC_EHCI
|
||||
select IMX_HAVE_PLATFORM_MXC_NAND
|
||||
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
||||
select SOC_IMX25
|
||||
|
||||
config MACH_EUKREA_CPUIMX25SD
|
||||
bool "Support Eukrea CPUIMX25 Platform"
|
||||
select IMX_HAVE_PLATFORM_FLEXCAN
|
||||
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMXDI_RTC
|
||||
select IMX_HAVE_PLATFORM_IMX_FB
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_MXC_EHCI
|
||||
select IMX_HAVE_PLATFORM_MXC_NAND
|
||||
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
||||
select USB_ULPI_VIEWPORT if USB_ULPI
|
||||
select SOC_IMX25
|
||||
|
||||
choice
|
||||
prompt "Baseboard"
|
||||
depends on MACH_EUKREA_CPUIMX25SD
|
||||
default MACH_EUKREA_MBIMXSD25_BASEBOARD
|
||||
|
||||
config MACH_EUKREA_MBIMXSD25_BASEBOARD
|
||||
bool "Eukrea MBIMXSD development board"
|
||||
select IMX_HAVE_PLATFORM_GPIO_KEYS
|
||||
select IMX_HAVE_PLATFORM_IMX_SSI
|
||||
select IMX_HAVE_PLATFORM_SPI_IMX
|
||||
select LEDS_GPIO_REGISTER
|
||||
help
|
||||
This adds board specific devices that can be found on Eukrea's
|
||||
MBIMXSD evaluation board.
|
||||
|
||||
endchoice
|
||||
|
||||
config MACH_IMX25_DT
|
||||
bool "Support i.MX25 platforms from device tree"
|
||||
select SOC_IMX25
|
||||
help
|
||||
Include support for Freescale i.MX25 based platforms
|
||||
using the device tree for discovery
|
||||
|
||||
comment "MX27 platforms:"
|
||||
|
||||
config MACH_MX27ADS
|
||||
@ -557,6 +494,20 @@ config MACH_VPR200
|
||||
|
||||
endif
|
||||
|
||||
if ARCH_MULTI_V5
|
||||
|
||||
comment "Device tree only"
|
||||
|
||||
config SOC_IMX25
|
||||
bool "i.MX25 support"
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select CPU_ARM926T
|
||||
select MXC_AVIC
|
||||
select PINCTRL_IMX25
|
||||
help
|
||||
This enables support for Freescale i.MX25 processor
|
||||
endif
|
||||
|
||||
if ARCH_MULTI_V7
|
||||
|
||||
comment "Device tree only"
|
||||
@ -637,7 +588,7 @@ config SOC_VF610
|
||||
select PL310_ERRATA_769419 if CACHE_L2X0
|
||||
|
||||
help
|
||||
This enable support for Freescale Vybrid VF610 processor.
|
||||
This enables support for Freescale Vybrid VF610 processor.
|
||||
|
||||
choice
|
||||
prompt "Clocksource for scheduler clock"
|
||||
@ -667,7 +618,7 @@ config SOC_LS1021A
|
||||
select ZONE_DMA if ARM_LPAE
|
||||
|
||||
help
|
||||
This enable support for Freescale LS1021A processor.
|
||||
This enables support for Freescale LS1021A processor.
|
||||
|
||||
endif
|
||||
|
||||
|
@ -3,7 +3,7 @@ obj-y := time.o cpu.o system.o irq-common.o
|
||||
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
|
||||
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
|
||||
obj-$(CONFIG_SOC_IMX25) += clk-imx25.o cpu-imx25.o mach-imx25.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
|
||||
obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
|
||||
@ -48,12 +48,6 @@ obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
|
||||
# i.MX21 based machines
|
||||
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
|
||||
|
||||
# i.MX25 based machines
|
||||
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
|
||||
obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
|
||||
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
|
||||
obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
|
||||
|
||||
# i.MX27 based machines
|
||||
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
|
||||
obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
|
||||
|
@ -30,7 +30,6 @@
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
#include "mx25.h"
|
||||
|
||||
#define CCM_MPCTL 0x00
|
||||
#define CCM_UPCTL 0x04
|
||||
@ -239,80 +238,6 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init mx25_clocks_init(void)
|
||||
{
|
||||
void __iomem *ccm;
|
||||
|
||||
ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
|
||||
|
||||
__mx25_clocks_init(24000000, ccm);
|
||||
|
||||
clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
/* i.mx25 has the i.mx21 type uart */
|
||||
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
|
||||
/* i.mx25 has the i.mx35 type cspi */
|
||||
clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
|
||||
clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
|
||||
clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
|
||||
clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
|
||||
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
|
||||
clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
|
||||
clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
|
||||
clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
|
||||
clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
|
||||
clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
|
||||
clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
|
||||
clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
|
||||
clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0");
|
||||
clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0");
|
||||
clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0");
|
||||
clk_register_clkdev(clk[dummy], "audmux", NULL);
|
||||
clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
|
||||
clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
|
||||
/* i.mx25 has the i.mx35 type sdma */
|
||||
clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
|
||||
clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
|
||||
clk_register_clkdev(clk[iim_ipg], "iim", NULL);
|
||||
|
||||
mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mx25_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
struct device_node *refnp;
|
||||
|
@ -23,13 +23,11 @@ struct of_device_id;
|
||||
|
||||
void mx1_map_io(void);
|
||||
void mx21_map_io(void);
|
||||
void mx25_map_io(void);
|
||||
void mx27_map_io(void);
|
||||
void mx31_map_io(void);
|
||||
void mx35_map_io(void);
|
||||
void imx1_init_early(void);
|
||||
void imx21_init_early(void);
|
||||
void imx25_init_early(void);
|
||||
void imx27_init_early(void);
|
||||
void imx31_init_early(void);
|
||||
void imx35_init_early(void);
|
||||
@ -37,13 +35,11 @@ void mxc_init_irq(void __iomem *);
|
||||
void tzic_init_irq(void);
|
||||
void mx1_init_irq(void);
|
||||
void mx21_init_irq(void);
|
||||
void mx25_init_irq(void);
|
||||
void mx27_init_irq(void);
|
||||
void mx31_init_irq(void);
|
||||
void mx35_init_irq(void);
|
||||
void imx1_soc_init(void);
|
||||
void imx21_soc_init(void);
|
||||
void imx25_soc_init(void);
|
||||
void imx27_soc_init(void);
|
||||
void imx31_soc_init(void);
|
||||
void imx35_soc_init(void);
|
||||
@ -51,7 +47,6 @@ void epit_timer_init(void __iomem *base, int irq);
|
||||
void mxc_timer_init(void __iomem *, int);
|
||||
int mx1_clocks_init(unsigned long fref);
|
||||
int mx21_clocks_init(unsigned long lref, unsigned long fref);
|
||||
int mx25_clocks_init(void);
|
||||
int mx27_clocks_init(unsigned long fref);
|
||||
int mx31_clocks_init(unsigned long fref);
|
||||
int mx35_clocks_init(void);
|
||||
|
@ -11,6 +11,8 @@
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "iim.h"
|
||||
#include "hardware.h"
|
||||
@ -20,8 +22,15 @@ static int mx25_cpu_rev = -1;
|
||||
static int mx25_read_cpu_rev(void)
|
||||
{
|
||||
u32 rev;
|
||||
void __iomem *iim_base;
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim");
|
||||
iim_base = of_iomap(np, 0);
|
||||
BUG_ON(!iim_base);
|
||||
rev = readl(iim_base + MXC_IIMSREV);
|
||||
iounmap(iim_base);
|
||||
|
||||
rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV));
|
||||
switch (rev) {
|
||||
case 0x00:
|
||||
return IMX_CHIP_REVISION_1_0;
|
||||
|
@ -1,85 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Pengutronix
|
||||
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include "devices/devices-common.h"
|
||||
|
||||
extern const struct imx_fec_data imx25_fec_data;
|
||||
#define imx25_add_fec(pdata) \
|
||||
imx_add_fec(&imx25_fec_data, pdata)
|
||||
|
||||
extern const struct imx_flexcan_data imx25_flexcan_data[];
|
||||
#define imx25_add_flexcan(id) \
|
||||
imx_add_flexcan(&imx25_flexcan_data[id])
|
||||
#define imx25_add_flexcan0() imx25_add_flexcan(0)
|
||||
#define imx25_add_flexcan1() imx25_add_flexcan(1)
|
||||
|
||||
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
|
||||
#define imx25_add_fsl_usb2_udc(pdata) \
|
||||
imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
|
||||
|
||||
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
|
||||
#define imx25_add_imxdi_rtc() \
|
||||
imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
|
||||
|
||||
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
|
||||
#define imx25_add_imx2_wdt() \
|
||||
imx_add_imx2_wdt(&imx25_imx2_wdt_data)
|
||||
|
||||
extern const struct imx_imx_fb_data imx25_imx_fb_data;
|
||||
#define imx25_add_imx_fb(pdata) \
|
||||
imx_add_imx_fb(&imx25_imx_fb_data, pdata)
|
||||
|
||||
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
|
||||
#define imx25_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
|
||||
#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
|
||||
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
|
||||
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
|
||||
|
||||
extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
|
||||
#define imx25_add_imx_keypad(pdata) \
|
||||
imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
|
||||
|
||||
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
|
||||
#define imx25_add_imx_ssi(id, pdata) \
|
||||
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
|
||||
#define imx25_add_imx_uart(id, pdata) \
|
||||
imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
|
||||
#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
|
||||
#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata)
|
||||
#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata)
|
||||
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
|
||||
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
|
||||
|
||||
extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
|
||||
#define imx25_add_mx2_camera(pdata) \
|
||||
imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
|
||||
|
||||
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
|
||||
#define imx25_add_mxc_ehci_otg(pdata) \
|
||||
imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
|
||||
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
|
||||
#define imx25_add_mxc_ehci_hs(pdata) \
|
||||
imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
|
||||
|
||||
extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
|
||||
#define imx25_add_mxc_nand(pdata) \
|
||||
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
|
||||
|
||||
extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
|
||||
#define imx25_add_sdhci_esdhc_imx(id, pdata) \
|
||||
imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
|
||||
|
||||
extern const struct imx_spi_imx_data imx25_cspi_data[];
|
||||
#define imx25_add_spi_imx(id, pdata) \
|
||||
imx_add_spi_imx(&imx25_cspi_data[id], pdata)
|
||||
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
|
||||
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
|
||||
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
|
@ -21,9 +21,6 @@ config IMX_HAVE_PLATFORM_IMX27_CODA
|
||||
config IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_IMXDI_RTC
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_IMX_FB
|
||||
bool
|
||||
|
||||
|
@ -8,7 +8,6 @@ obj-y += platform-gpio-mxc.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
|
||||
obj-y += platform-imx-dma.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
|
||||
|
@ -19,11 +19,6 @@
|
||||
.irq = soc ## _INT_FEC, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_fec_data imx25_fec_data __initconst =
|
||||
imx_fec_data_entry_single(MX25, "imx25-fec");
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_fec_data imx27_fec_data __initconst =
|
||||
imx_fec_data_entry_single(MX27, "imx27-fec");
|
||||
|
@ -18,11 +18,6 @@
|
||||
.irq = soc ## _INT_USB_OTG, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
|
||||
imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27");
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
|
||||
imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");
|
||||
|
@ -29,11 +29,6 @@ const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
|
||||
imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX21 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
|
||||
imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
|
||||
imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
|
||||
|
@ -31,16 +31,6 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
|
||||
imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX21 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
|
||||
#define imx25_imx_i2c_data_entry(_id, _hwid) \
|
||||
imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K)
|
||||
imx25_imx_i2c_data_entry(0, 1),
|
||||
imx25_imx_i2c_data_entry(1, 2),
|
||||
imx25_imx_i2c_data_entry(2, 3),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
|
||||
#define imx27_imx_i2c_data_entry(_id, _hwid) \
|
||||
|
@ -21,11 +21,6 @@ const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
|
||||
imx_imx_keypad_data_entry_single(MX21, SZ_16);
|
||||
#endif /* ifdef CONFIG_SOC_IMX21 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
|
||||
imx_imx_keypad_data_entry_single(MX25, SZ_16K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
|
||||
imx_imx_keypad_data_entry_single(MX27, SZ_16);
|
||||
|
@ -30,15 +30,6 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX21 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
|
||||
#define imx25_imx_ssi_data_entry(_id, _hwid) \
|
||||
imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
|
||||
imx25_imx_ssi_data_entry(0, 1),
|
||||
imx25_imx_ssi_data_entry(1, 2),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
|
||||
#define imx27_imx_ssi_data_entry(_id, _hwid) \
|
||||
|
@ -47,18 +47,6 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
|
||||
#define imx25_imx_uart_data_entry(_id, _hwid) \
|
||||
imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
|
||||
imx25_imx_uart_data_entry(0, 1),
|
||||
imx25_imx_uart_data_entry(1, 2),
|
||||
imx25_imx_uart_data_entry(2, 3),
|
||||
imx25_imx_uart_data_entry(3, 4),
|
||||
imx25_imx_uart_data_entry(4, 5),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
|
||||
#define imx27_imx_uart_data_entry(_id, _hwid) \
|
||||
|
@ -25,11 +25,6 @@ const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
|
||||
imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX21 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
|
||||
imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
|
||||
imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
|
||||
|
@ -1,42 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Pengutronix
|
||||
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include "../hardware.h"
|
||||
#include "devices-common.h"
|
||||
|
||||
#define imx_imxdi_rtc_data_entry_single(soc) \
|
||||
{ \
|
||||
.iobase = soc ## _DRYICE_BASE_ADDR, \
|
||||
.irq = soc ## _INT_DRYICE, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
|
||||
imx_imxdi_rtc_data_entry_single(MX25);
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
struct platform_device *__init imx_add_imxdi_rtc(
|
||||
const struct imx_imxdi_rtc_data *data)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = data->iobase,
|
||||
.end = data->iobase + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = data->irq,
|
||||
.end = data->irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
return imx_add_platform_device("imxdi_rtc", 0,
|
||||
res, ARRAY_SIZE(res), NULL, 0);
|
||||
}
|
@ -27,11 +27,6 @@
|
||||
.irqemmaprp = soc ## _INT_EMMAPRP, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
|
||||
imx_mx2_camera_data_entry_single(MX25, "imx25-camera");
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
|
||||
imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera");
|
||||
|
@ -18,13 +18,6 @@
|
||||
.irq = soc ## _INT_USB_ ## hs, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
|
||||
imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
|
||||
const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
|
||||
imx_mxc_ehci_data_entry_single(MX25, 1, HS);
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
|
||||
imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
|
||||
|
@ -34,11 +34,6 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
|
||||
imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX21 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
|
||||
imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
|
||||
imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
|
||||
|
@ -39,17 +39,6 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
/* i.mx25 has the i.mx35 type cspi */
|
||||
const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
|
||||
#define imx25_cspi_data_entry(_id, _hwid) \
|
||||
imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K)
|
||||
imx25_cspi_data_entry(0, 1),
|
||||
imx25_cspi_data_entry(1, 2),
|
||||
imx25_cspi_data_entry(2, 3),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX25 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX27
|
||||
const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
|
||||
#define imx27_cspi_data_entry(_id, _hwid) \
|
||||
|
@ -1,99 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/usb-ehci-mxc.h>
|
||||
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define USBCTRL_OTGBASE_OFFSET 0x600
|
||||
|
||||
#define MX25_OTG_SIC_SHIFT 29
|
||||
#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
|
||||
#define MX25_OTG_PM_BIT (1 << 24)
|
||||
#define MX25_OTG_PP_BIT (1 << 11)
|
||||
#define MX25_OTG_OCPOL_BIT (1 << 3)
|
||||
|
||||
#define MX25_H1_SIC_SHIFT 21
|
||||
#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
|
||||
#define MX25_H1_PP_BIT (1 << 18)
|
||||
#define MX25_H1_PM_BIT (1 << 16)
|
||||
#define MX25_H1_IPPUE_UP_BIT (1 << 7)
|
||||
#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
|
||||
#define MX25_H1_TLL_BIT (1 << 5)
|
||||
#define MX25_H1_USBTE_BIT (1 << 4)
|
||||
#define MX25_H1_OCPOL_BIT (1 << 2)
|
||||
|
||||
int mx25_initialize_usb_hw(int port, unsigned int flags)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
|
||||
|
||||
switch (port) {
|
||||
case 0: /* OTG port */
|
||||
v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
|
||||
MX25_OTG_OCPOL_BIT);
|
||||
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
|
||||
|
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
|
||||
v |= MX25_OTG_PM_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
|
||||
v |= MX25_OTG_PP_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
|
||||
v |= MX25_OTG_OCPOL_BIT;
|
||||
|
||||
break;
|
||||
case 1: /* H1 port */
|
||||
v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
|
||||
MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
|
||||
MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
|
||||
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
|
||||
|
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
|
||||
v |= MX25_H1_PM_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
|
||||
v |= MX25_H1_PP_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
|
||||
v |= MX25_H1_OCPOL_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_TTL_ENABLED))
|
||||
v |= MX25_H1_TLL_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_INTERNAL_PHY)
|
||||
v |= MX25_H1_USBTE_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_IPPUE_DOWN)
|
||||
v |= MX25_H1_IPPUE_DOWN_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_IPPUE_UP)
|
||||
v |= MX25_H1_IPPUE_UP_BIT;
|
||||
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1,310 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
|
||||
*
|
||||
* Based on pcm970-baseboard.c which is :
|
||||
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx25.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx25.h"
|
||||
#include "mx25.h"
|
||||
|
||||
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
|
||||
/* LCD */
|
||||
MX25_PAD_LD0__LD0,
|
||||
MX25_PAD_LD1__LD1,
|
||||
MX25_PAD_LD2__LD2,
|
||||
MX25_PAD_LD3__LD3,
|
||||
MX25_PAD_LD4__LD4,
|
||||
MX25_PAD_LD5__LD5,
|
||||
MX25_PAD_LD6__LD6,
|
||||
MX25_PAD_LD7__LD7,
|
||||
MX25_PAD_LD8__LD8,
|
||||
MX25_PAD_LD9__LD9,
|
||||
MX25_PAD_LD10__LD10,
|
||||
MX25_PAD_LD11__LD11,
|
||||
MX25_PAD_LD12__LD12,
|
||||
MX25_PAD_LD13__LD13,
|
||||
MX25_PAD_LD14__LD14,
|
||||
MX25_PAD_LD15__LD15,
|
||||
MX25_PAD_GPIO_E__LD16,
|
||||
MX25_PAD_GPIO_F__LD17,
|
||||
MX25_PAD_HSYNC__HSYNC,
|
||||
MX25_PAD_VSYNC__VSYNC,
|
||||
MX25_PAD_LSCLK__LSCLK,
|
||||
MX25_PAD_OE_ACD__OE_ACD,
|
||||
MX25_PAD_CONTRAST__CONTRAST,
|
||||
/* LCD_PWR */
|
||||
MX25_PAD_PWM__GPIO_1_26,
|
||||
/* LED */
|
||||
MX25_PAD_POWER_FAIL__GPIO_3_19,
|
||||
/* SWITCH */
|
||||
MX25_PAD_VSTBY_ACK__GPIO_3_18,
|
||||
/* UART2 */
|
||||
MX25_PAD_UART2_RTS__UART2_RTS,
|
||||
MX25_PAD_UART2_CTS__UART2_CTS,
|
||||
MX25_PAD_UART2_TXD__UART2_TXD,
|
||||
MX25_PAD_UART2_RXD__UART2_RXD,
|
||||
/* SD1 */
|
||||
MX25_PAD_SD1_CMD__SD1_CMD,
|
||||
MX25_PAD_SD1_CLK__SD1_CLK,
|
||||
MX25_PAD_SD1_DATA0__SD1_DATA0,
|
||||
MX25_PAD_SD1_DATA1__SD1_DATA1,
|
||||
MX25_PAD_SD1_DATA2__SD1_DATA2,
|
||||
MX25_PAD_SD1_DATA3__SD1_DATA3,
|
||||
/* SD1 CD */
|
||||
MX25_PAD_DE_B__GPIO_2_20,
|
||||
/* I2S */
|
||||
MX25_PAD_KPP_COL3__AUD5_TXFS,
|
||||
MX25_PAD_KPP_COL2__AUD5_TXC,
|
||||
MX25_PAD_KPP_COL1__AUD5_RXD,
|
||||
MX25_PAD_KPP_COL0__AUD5_TXD,
|
||||
/* CAN */
|
||||
MX25_PAD_GPIO_D__CAN2_RX,
|
||||
MX25_PAD_GPIO_C__CAN2_TX,
|
||||
/* SPI1 */
|
||||
MX25_PAD_CSPI1_MOSI__CSPI1_MOSI,
|
||||
MX25_PAD_CSPI1_MISO__CSPI1_MISO,
|
||||
MX25_PAD_CSPI1_SS0__GPIO_1_16,
|
||||
MX25_PAD_CSPI1_SS1__GPIO_1_17,
|
||||
MX25_PAD_CSPI1_SCLK__CSPI1_SCLK,
|
||||
MX25_PAD_CSPI1_RDY__GPIO_2_22,
|
||||
};
|
||||
|
||||
#define GPIO_LED1 IMX_GPIO_NR(3, 19)
|
||||
#define GPIO_SWITCH1 IMX_GPIO_NR(3, 18)
|
||||
#define GPIO_SD1CD IMX_GPIO_NR(2, 20)
|
||||
#define GPIO_LCDPWR IMX_GPIO_NR(1, 26)
|
||||
#define GPIO_SPI1_SS0 IMX_GPIO_NR(1, 16)
|
||||
#define GPIO_SPI1_SS1 IMX_GPIO_NR(1, 17)
|
||||
#define GPIO_SPI1_IRQ IMX_GPIO_NR(2, 22)
|
||||
|
||||
static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
|
||||
{
|
||||
.mode = {
|
||||
.name = "CMO-QVGA",
|
||||
.refresh = 60,
|
||||
.xres = 320,
|
||||
.yres = 240,
|
||||
.pixclock = KHZ2PICOS(6500),
|
||||
.left_margin = 30,
|
||||
.right_margin = 38,
|
||||
.upper_margin = 20,
|
||||
.lower_margin = 3,
|
||||
.hsync_len = 15,
|
||||
.vsync_len = 4,
|
||||
},
|
||||
.bpp = 16,
|
||||
.pcr = 0xCAD08B80,
|
||||
}, {
|
||||
.mode = {
|
||||
.name = "DVI-VGA",
|
||||
.refresh = 60,
|
||||
.xres = 640,
|
||||
.yres = 480,
|
||||
.pixclock = 32000,
|
||||
.hsync_len = 7,
|
||||
.left_margin = 100,
|
||||
.right_margin = 100,
|
||||
.vsync_len = 7,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 100,
|
||||
},
|
||||
.pcr = 0xFA208B80,
|
||||
.bpp = 16,
|
||||
}, {
|
||||
.mode = {
|
||||
.name = "DVI-SVGA",
|
||||
.refresh = 60,
|
||||
.xres = 800,
|
||||
.yres = 600,
|
||||
.pixclock = 25000,
|
||||
.hsync_len = 7,
|
||||
.left_margin = 75,
|
||||
.right_margin = 75,
|
||||
.vsync_len = 7,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 75,
|
||||
},
|
||||
.pcr = 0xFA208B80,
|
||||
.bpp = 16,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
|
||||
.mode = eukrea_mximxsd_modes,
|
||||
.num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
|
||||
.pwmr = 0x00A903FF,
|
||||
.lscr1 = 0x00120300,
|
||||
.dmacr = 0x00040060,
|
||||
};
|
||||
|
||||
static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
|
||||
unsigned int power)
|
||||
{
|
||||
if (power)
|
||||
gpio_direction_output(GPIO_LCDPWR, 1);
|
||||
else
|
||||
gpio_direction_output(GPIO_LCDPWR, 0);
|
||||
}
|
||||
|
||||
static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
|
||||
.set_power = eukrea_mbimxsd_lcd_power_set,
|
||||
};
|
||||
|
||||
static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
|
||||
.name = "platform-lcd",
|
||||
.dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
|
||||
};
|
||||
|
||||
static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
|
||||
{
|
||||
.name = "led1",
|
||||
.default_trigger = "heartbeat",
|
||||
.active_low = 1,
|
||||
.gpio = GPIO_LED1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led_platform_data
|
||||
eukrea_mbimxsd_led_info __initconst = {
|
||||
.leds = eukrea_mbimxsd_leds,
|
||||
.num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
|
||||
};
|
||||
|
||||
static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
|
||||
{
|
||||
.gpio = GPIO_SWITCH1,
|
||||
.code = BTN_0,
|
||||
.desc = "BP1",
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_keys_platform_data
|
||||
eukrea_mbimxsd_button_data __initconst = {
|
||||
.buttons = eukrea_mbimxsd_gpio_buttons,
|
||||
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
|
||||
};
|
||||
|
||||
static struct platform_device *platform_devices[] __initdata = {
|
||||
&eukrea_mbimxsd_lcd_powerdev,
|
||||
};
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("tlv320aic23", 0x1a),
|
||||
},
|
||||
};
|
||||
|
||||
static const
|
||||
struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
|
||||
.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
|
||||
};
|
||||
|
||||
static struct esdhc_platform_data sd1_pdata = {
|
||||
.cd_gpio = GPIO_SD1CD,
|
||||
.cd_type = ESDHC_CD_GPIO,
|
||||
.wp_type = ESDHC_WP_NONE,
|
||||
};
|
||||
|
||||
static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = {
|
||||
{
|
||||
.modalias = "spidev",
|
||||
.max_speed_hz = 20000000,
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.mode = SPI_MODE_0,
|
||||
},
|
||||
{
|
||||
.modalias = "spidev",
|
||||
.max_speed_hz = 20000000,
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
.mode = SPI_MODE_0,
|
||||
},
|
||||
};
|
||||
|
||||
static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
|
||||
|
||||
static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = {
|
||||
.chipselect = eukrea_mbimxsd25_spi_cs,
|
||||
.num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs),
|
||||
};
|
||||
|
||||
/*
|
||||
* system init for baseboard usage. Will be called by cpuimx25 init.
|
||||
*
|
||||
* Add platform devices present on this baseboard and init
|
||||
* them from CPU side as far as required to use them later on
|
||||
*/
|
||||
void __init eukrea_mbimxsd25_baseboard_init(void)
|
||||
{
|
||||
if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
|
||||
ARRAY_SIZE(eukrea_mbimxsd_pads)))
|
||||
printk(KERN_ERR "error setting mbimxsd pads !\n");
|
||||
|
||||
imx25_add_imx_uart1(&uart_pdata);
|
||||
imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
|
||||
imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
|
||||
|
||||
imx25_add_flexcan1();
|
||||
imx25_add_sdhci_esdhc_imx(0, &sd1_pdata);
|
||||
|
||||
gpio_request(GPIO_LED1, "LED1");
|
||||
gpio_direction_output(GPIO_LED1, 1);
|
||||
gpio_free(GPIO_LED1);
|
||||
|
||||
gpio_request(GPIO_SWITCH1, "SWITCH1");
|
||||
gpio_direction_input(GPIO_SWITCH1);
|
||||
gpio_free(GPIO_SWITCH1);
|
||||
|
||||
gpio_request(GPIO_LCDPWR, "LCDPWR");
|
||||
gpio_direction_output(GPIO_LCDPWR, 1);
|
||||
|
||||
i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
|
||||
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
|
||||
|
||||
gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
|
||||
gpio_direction_input(GPIO_SPI1_IRQ);
|
||||
gpio_free(GPIO_SPI1_IRQ);
|
||||
imx25_add_spi_imx0(&eukrea_mbimxsd25_spi0_data);
|
||||
spi_register_board_info(eukrea_mbimxsd25_spi_board_info,
|
||||
ARRAY_SIZE(eukrea_mbimxsd25_spi_board_info));
|
||||
|
||||
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
|
||||
gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
|
||||
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
|
||||
imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
|
||||
}
|
@ -100,7 +100,7 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = {
|
||||
.num_modes = ARRAY_SIZE(fb_modedb),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
|
||||
static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
|
||||
/* LCD */
|
||||
MX35_PAD_LD0__IPU_DISPB_DAT_0,
|
||||
MX35_PAD_LD1__IPU_DISPB_DAT_1,
|
||||
|
@ -112,7 +112,6 @@
|
||||
#include "mx21.h"
|
||||
#include "mx27.h"
|
||||
#include "mx1.h"
|
||||
#include "mx25.h"
|
||||
|
||||
#define imx_map_entry(soc, name, _type) { \
|
||||
.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
|
||||
|
@ -1,524 +0,0 @@
|
||||
/*
|
||||
* arch/arm/plat-mxc/include/mach/iomux-mx25.h
|
||||
*
|
||||
* Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* based on arch/arm/mach-mx25/mx25_pins.h
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* and
|
||||
* arch/arm/plat-mxc/include/mach/iomux-mx35.h
|
||||
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __MACH_IOMUX_MX25_H__
|
||||
#define __MACH_IOMUX_MX25_H__
|
||||
|
||||
#include "iomux-v3.h"
|
||||
|
||||
/*
|
||||
* IOMUX/PAD Bit field definitions
|
||||
*/
|
||||
|
||||
#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
|
||||
#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
|
||||
|
||||
#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
|
||||
|
||||
#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
|
||||
|
||||
#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
|
||||
|
||||
#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D2__CSPI3_MOSI IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D3__CSPI3_MISO IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D4__CSPI3_SCLK IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D5__CSPI3_RDY IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
|
||||
#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
|
||||
#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
|
||||
#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
|
||||
#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
|
||||
#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
|
||||
#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
|
||||
#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
|
||||
#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
|
||||
#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
|
||||
#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
|
||||
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
|
||||
#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
|
||||
#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
|
||||
#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
|
||||
|
||||
#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
|
||||
#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
|
||||
#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
|
||||
#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
|
||||
#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
|
||||
#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
|
||||
#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
|
||||
#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
|
||||
#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
|
||||
#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
|
||||
#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
|
||||
#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
|
||||
#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
|
||||
#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
|
||||
#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
|
||||
#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
|
||||
#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
|
||||
#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
|
||||
#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
|
||||
#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
|
||||
|
||||
#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP)
|
||||
#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
|
||||
|
||||
#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
|
||||
|
||||
#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
|
||||
|
||||
#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
|
||||
#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
|
||||
#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
|
||||
|
||||
#endif /* __MACH_IOMUX_MX25_H__ */
|
@ -114,7 +114,7 @@ enum iomux_gp_func {
|
||||
*/
|
||||
int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
|
||||
/*
|
||||
* setups mutliple pins
|
||||
* setups multiple pins
|
||||
* convenient way to call the above function with tables
|
||||
*/
|
||||
int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
|
||||
|
@ -56,9 +56,10 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
|
||||
int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
|
||||
unsigned count)
|
||||
{
|
||||
iomux_v3_cfg_t *p = pad_list;
|
||||
const iomux_v3_cfg_t *p = pad_list;
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
|
@ -128,10 +128,11 @@ typedef u64 iomux_v3_cfg_t;
|
||||
int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
|
||||
|
||||
/*
|
||||
* setups mutliple pads
|
||||
* setups multiple pads
|
||||
* convenient way to call the above function with tables
|
||||
*/
|
||||
int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
|
||||
int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
|
||||
unsigned count);
|
||||
|
||||
/*
|
||||
* Initialise the iomux controller
|
||||
|
@ -75,7 +75,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
|
||||
static const iomux_v3_cfg_t eukrea_cpuimx35_pads[] __initconst = {
|
||||
/* UART1 */
|
||||
MX35_PAD_CTS1__UART1_CTS,
|
||||
MX35_PAD_RTS1__UART1_RTS,
|
||||
|
@ -1,172 +0,0 @@
|
||||
/*
|
||||
* Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
|
||||
* Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/usb/otg.h>
|
||||
#include <linux/usb/ulpi.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx25.h"
|
||||
#include "ehci.h"
|
||||
#include "eukrea-baseboards.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx25.h"
|
||||
#include "mx25.h"
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
|
||||
/* FEC - RMII */
|
||||
MX25_PAD_FEC_MDC__FEC_MDC,
|
||||
MX25_PAD_FEC_MDIO__FEC_MDIO,
|
||||
MX25_PAD_FEC_TDATA0__FEC_TDATA0,
|
||||
MX25_PAD_FEC_TDATA1__FEC_TDATA1,
|
||||
MX25_PAD_FEC_TX_EN__FEC_TX_EN,
|
||||
MX25_PAD_FEC_RDATA0__FEC_RDATA0,
|
||||
MX25_PAD_FEC_RDATA1__FEC_RDATA1,
|
||||
MX25_PAD_FEC_RX_DV__FEC_RX_DV,
|
||||
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
|
||||
/* I2C1 */
|
||||
MX25_PAD_I2C1_CLK__I2C1_CLK,
|
||||
MX25_PAD_I2C1_DAT__I2C1_DAT,
|
||||
};
|
||||
|
||||
static const struct fec_platform_data mx25_fec_pdata __initconst = {
|
||||
.phy = PHY_INTERFACE_MODE_RMII,
|
||||
};
|
||||
|
||||
static const struct mxc_nand_platform_data
|
||||
eukrea_cpuimx25_nand_board_info __initconst = {
|
||||
.width = 1,
|
||||
.hw_ecc = 1,
|
||||
.flash_bbt = 1,
|
||||
};
|
||||
|
||||
static const struct imxi2c_platform_data
|
||||
eukrea_cpuimx25_i2c0_data __initconst = {
|
||||
.bitrate = 100000,
|
||||
};
|
||||
|
||||
static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("pcf8563", 0x51),
|
||||
},
|
||||
};
|
||||
|
||||
static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
|
||||
{
|
||||
return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
|
||||
}
|
||||
|
||||
static const struct mxc_usbh_platform_data otg_pdata __initconst = {
|
||||
.init = eukrea_cpuimx25_otg_init,
|
||||
.portsc = MXC_EHCI_MODE_UTMI,
|
||||
};
|
||||
|
||||
static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
|
||||
{
|
||||
return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
|
||||
MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
|
||||
}
|
||||
|
||||
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
|
||||
.init = eukrea_cpuimx25_usbh2_init,
|
||||
.portsc = MXC_EHCI_MODE_SERIAL,
|
||||
};
|
||||
|
||||
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
|
||||
.operating_mode = FSL_USB2_DR_DEVICE,
|
||||
.phy_mode = FSL_USB2_PHY_UTMI,
|
||||
.workaround = FLS_USB2_WORKAROUND_ENGCM09152,
|
||||
};
|
||||
|
||||
static bool otg_mode_host __initdata;
|
||||
|
||||
static int __init eukrea_cpuimx25_otg_mode(char *options)
|
||||
{
|
||||
if (!strcmp(options, "host"))
|
||||
otg_mode_host = true;
|
||||
else if (!strcmp(options, "device"))
|
||||
otg_mode_host = false;
|
||||
else
|
||||
pr_info("otg_mode neither \"host\" nor \"device\". "
|
||||
"Defaulting to device\n");
|
||||
return 1;
|
||||
}
|
||||
__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
|
||||
|
||||
static void __init eukrea_cpuimx25_init(void)
|
||||
{
|
||||
imx25_soc_init();
|
||||
|
||||
if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
|
||||
ARRAY_SIZE(eukrea_cpuimx25_pads)))
|
||||
printk(KERN_ERR "error setting cpuimx25 pads !\n");
|
||||
|
||||
imx25_add_imx_uart0(&uart_pdata);
|
||||
imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
|
||||
imx25_add_imxdi_rtc();
|
||||
imx25_add_fec(&mx25_fec_pdata);
|
||||
imx25_add_imx2_wdt();
|
||||
|
||||
i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
|
||||
ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
|
||||
imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
|
||||
|
||||
if (otg_mode_host)
|
||||
imx25_add_mxc_ehci_otg(&otg_pdata);
|
||||
else
|
||||
imx25_add_fsl_usb2_udc(&otg_device_pdata);
|
||||
|
||||
imx25_add_mxc_ehci_hs(&usbh2_pdata);
|
||||
|
||||
#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
|
||||
eukrea_mbimxsd25_baseboard_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init eukrea_cpuimx25_timer_init(void)
|
||||
{
|
||||
mx25_clocks_init();
|
||||
}
|
||||
|
||||
MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
|
||||
/* Maintainer: Eukrea Electromatique */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = mx25_map_io,
|
||||
.init_early = imx25_init_early,
|
||||
.init_irq = mx25_init_irq,
|
||||
.init_time = eukrea_cpuimx25_timer_init,
|
||||
.init_machine = eukrea_cpuimx25_init,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
@ -10,12 +10,29 @@
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include "common.h"
|
||||
#include "mx25.h"
|
||||
#include "hardware.h"
|
||||
|
||||
static void __init imx25_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX25);
|
||||
}
|
||||
|
||||
static void __init mx25_init_irq(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *avic_base;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,avic");
|
||||
avic_base = of_iomap(np, 0);
|
||||
BUG_ON(!avic_base);
|
||||
mxc_init_irq(avic_base);
|
||||
}
|
||||
|
||||
static const char * const imx25_dt_board_compat[] __initconst = {
|
||||
"fsl,imx25",
|
||||
@ -23,7 +40,6 @@ static const char * const imx25_dt_board_compat[] __initconst = {
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
|
||||
.map_io = mx25_map_io,
|
||||
.init_early = imx25_init_early,
|
||||
.init_irq = mx25_init_irq,
|
||||
.dt_compat = imx25_dt_board_compat,
|
@ -1,270 +0,0 @@
|
||||
/*
|
||||
* Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This machine is known as:
|
||||
* - i.MX25 3-Stack Development System
|
||||
* - i.MX25 Platform Development Kit (i.MX25 PDK)
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/usb/otg.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx25.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx25.h"
|
||||
#include "mx25.h"
|
||||
|
||||
#define MX25PDK_CAN_PWDN IMX_GPIO_NR(4, 6)
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t mx25pdk_pads[] = {
|
||||
MX25_PAD_FEC_MDC__FEC_MDC,
|
||||
MX25_PAD_FEC_MDIO__FEC_MDIO,
|
||||
MX25_PAD_FEC_TDATA0__FEC_TDATA0,
|
||||
MX25_PAD_FEC_TDATA1__FEC_TDATA1,
|
||||
MX25_PAD_FEC_TX_EN__FEC_TX_EN,
|
||||
MX25_PAD_FEC_RDATA0__FEC_RDATA0,
|
||||
MX25_PAD_FEC_RDATA1__FEC_RDATA1,
|
||||
MX25_PAD_FEC_RX_DV__FEC_RX_DV,
|
||||
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
|
||||
MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
|
||||
MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
|
||||
|
||||
/* LCD */
|
||||
MX25_PAD_LD0__LD0,
|
||||
MX25_PAD_LD1__LD1,
|
||||
MX25_PAD_LD2__LD2,
|
||||
MX25_PAD_LD3__LD3,
|
||||
MX25_PAD_LD4__LD4,
|
||||
MX25_PAD_LD5__LD5,
|
||||
MX25_PAD_LD6__LD6,
|
||||
MX25_PAD_LD7__LD7,
|
||||
MX25_PAD_LD8__LD8,
|
||||
MX25_PAD_LD9__LD9,
|
||||
MX25_PAD_LD10__LD10,
|
||||
MX25_PAD_LD11__LD11,
|
||||
MX25_PAD_LD12__LD12,
|
||||
MX25_PAD_LD13__LD13,
|
||||
MX25_PAD_LD14__LD14,
|
||||
MX25_PAD_LD15__LD15,
|
||||
MX25_PAD_GPIO_E__LD16,
|
||||
MX25_PAD_GPIO_F__LD17,
|
||||
MX25_PAD_HSYNC__HSYNC,
|
||||
MX25_PAD_VSYNC__VSYNC,
|
||||
MX25_PAD_LSCLK__LSCLK,
|
||||
MX25_PAD_OE_ACD__OE_ACD,
|
||||
MX25_PAD_CONTRAST__CONTRAST,
|
||||
|
||||
/* Keypad */
|
||||
MX25_PAD_KPP_ROW0__KPP_ROW0,
|
||||
MX25_PAD_KPP_ROW1__KPP_ROW1,
|
||||
MX25_PAD_KPP_ROW2__KPP_ROW2,
|
||||
MX25_PAD_KPP_ROW3__KPP_ROW3,
|
||||
MX25_PAD_KPP_COL0__KPP_COL0,
|
||||
MX25_PAD_KPP_COL1__KPP_COL1,
|
||||
MX25_PAD_KPP_COL2__KPP_COL2,
|
||||
MX25_PAD_KPP_COL3__KPP_COL3,
|
||||
|
||||
/* SD1 */
|
||||
MX25_PAD_SD1_CMD__SD1_CMD,
|
||||
MX25_PAD_SD1_CLK__SD1_CLK,
|
||||
MX25_PAD_SD1_DATA0__SD1_DATA0,
|
||||
MX25_PAD_SD1_DATA1__SD1_DATA1,
|
||||
MX25_PAD_SD1_DATA2__SD1_DATA2,
|
||||
MX25_PAD_SD1_DATA3__SD1_DATA3,
|
||||
MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
|
||||
MX25_PAD_A15__GPIO_2_1, /* CardDetect */
|
||||
|
||||
/* I2C1 */
|
||||
MX25_PAD_I2C1_CLK__I2C1_CLK,
|
||||
MX25_PAD_I2C1_DAT__I2C1_DAT,
|
||||
|
||||
/* CAN1 */
|
||||
MX25_PAD_GPIO_A__CAN1_TX,
|
||||
MX25_PAD_GPIO_B__CAN1_RX,
|
||||
MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */
|
||||
};
|
||||
|
||||
static const struct fec_platform_data mx25_fec_pdata __initconst = {
|
||||
.phy = PHY_INTERFACE_MODE_RMII,
|
||||
};
|
||||
|
||||
#define FEC_ENABLE_GPIO IMX_GPIO_NR(2, 3)
|
||||
#define FEC_RESET_B_GPIO IMX_GPIO_NR(4, 8)
|
||||
|
||||
static void __init mx25pdk_fec_reset(void)
|
||||
{
|
||||
gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
|
||||
gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
|
||||
|
||||
gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */
|
||||
gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
|
||||
udelay(2);
|
||||
|
||||
/* turn on PHY power and lift reset */
|
||||
gpio_set_value(FEC_ENABLE_GPIO, 1);
|
||||
gpio_set_value(FEC_RESET_B_GPIO, 1);
|
||||
}
|
||||
|
||||
static const struct mxc_nand_platform_data
|
||||
mx25pdk_nand_board_info __initconst = {
|
||||
.width = 1,
|
||||
.hw_ecc = 1,
|
||||
.flash_bbt = 1,
|
||||
};
|
||||
|
||||
static struct imx_fb_videomode mx25pdk_modes[] = {
|
||||
{
|
||||
.mode = {
|
||||
.name = "CRT-VGA",
|
||||
.refresh = 60,
|
||||
.xres = 640,
|
||||
.yres = 480,
|
||||
.pixclock = 39683,
|
||||
.left_margin = 45,
|
||||
.right_margin = 114,
|
||||
.upper_margin = 33,
|
||||
.lower_margin = 11,
|
||||
.hsync_len = 1,
|
||||
.vsync_len = 1,
|
||||
},
|
||||
.bpp = 16,
|
||||
.pcr = 0xFA208B80,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
|
||||
.mode = mx25pdk_modes,
|
||||
.num_modes = ARRAY_SIZE(mx25pdk_modes),
|
||||
.pwmr = 0x00A903FF,
|
||||
.lscr1 = 0x00120300,
|
||||
.dmacr = 0x00020010,
|
||||
};
|
||||
|
||||
static const uint32_t mx25pdk_keymap[] = {
|
||||
KEY(0, 0, KEY_UP),
|
||||
KEY(0, 1, KEY_DOWN),
|
||||
KEY(0, 2, KEY_VOLUMEDOWN),
|
||||
KEY(0, 3, KEY_HOME),
|
||||
KEY(1, 0, KEY_RIGHT),
|
||||
KEY(1, 1, KEY_LEFT),
|
||||
KEY(1, 2, KEY_ENTER),
|
||||
KEY(1, 3, KEY_VOLUMEUP),
|
||||
KEY(2, 0, KEY_F6),
|
||||
KEY(2, 1, KEY_F8),
|
||||
KEY(2, 2, KEY_F9),
|
||||
KEY(2, 3, KEY_F10),
|
||||
KEY(3, 0, KEY_F1),
|
||||
KEY(3, 1, KEY_F2),
|
||||
KEY(3, 2, KEY_F3),
|
||||
KEY(3, 3, KEY_POWER),
|
||||
};
|
||||
|
||||
static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
|
||||
.keymap = mx25pdk_keymap,
|
||||
.keymap_size = ARRAY_SIZE(mx25pdk_keymap),
|
||||
};
|
||||
|
||||
static int mx25pdk_usbh2_init(struct platform_device *pdev)
|
||||
{
|
||||
return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
|
||||
}
|
||||
|
||||
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
|
||||
.init = mx25pdk_usbh2_init,
|
||||
.portsc = MXC_EHCI_MODE_SERIAL,
|
||||
};
|
||||
|
||||
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
|
||||
.operating_mode = FSL_USB2_DR_DEVICE,
|
||||
.phy_mode = FSL_USB2_PHY_UTMI,
|
||||
};
|
||||
|
||||
static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
|
||||
.bitrate = 100000,
|
||||
};
|
||||
|
||||
#define SD1_GPIO_WP IMX_GPIO_NR(2, 0)
|
||||
#define SD1_GPIO_CD IMX_GPIO_NR(2, 1)
|
||||
|
||||
static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
|
||||
.wp_gpio = SD1_GPIO_WP,
|
||||
.cd_gpio = SD1_GPIO_CD,
|
||||
.wp_type = ESDHC_WP_GPIO,
|
||||
.cd_type = ESDHC_CD_GPIO,
|
||||
};
|
||||
|
||||
static void __init mx25pdk_init(void)
|
||||
{
|
||||
imx25_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
|
||||
ARRAY_SIZE(mx25pdk_pads));
|
||||
|
||||
imx25_add_imx_uart0(&uart_pdata);
|
||||
imx25_add_fsl_usb2_udc(&otg_device_pdata);
|
||||
imx25_add_mxc_ehci_hs(&usbh2_pdata);
|
||||
imx25_add_mxc_nand(&mx25pdk_nand_board_info);
|
||||
imx25_add_imxdi_rtc();
|
||||
imx25_add_imx_fb(&mx25pdk_fb_pdata);
|
||||
imx25_add_imx2_wdt();
|
||||
|
||||
mx25pdk_fec_reset();
|
||||
imx25_add_fec(&mx25_fec_pdata);
|
||||
imx25_add_imx_keypad(&mx25pdk_keymap_data);
|
||||
|
||||
imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
|
||||
imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
|
||||
|
||||
gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn");
|
||||
imx25_add_flexcan0();
|
||||
}
|
||||
|
||||
static void __init mx25pdk_timer_init(void)
|
||||
{
|
||||
mx25_clocks_init();
|
||||
}
|
||||
|
||||
MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
|
||||
/* Maintainer: Freescale Semiconductor, Inc. */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = mx25_map_io,
|
||||
.init_early = imx25_init_early,
|
||||
.init_irq = mx25_init_irq,
|
||||
.init_time = mx25pdk_timer_init,
|
||||
.init_machine = mx25pdk_init,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
@ -166,7 +166,7 @@ static struct platform_device *devices[] __initdata = {
|
||||
&mx35pdk_flash,
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t mx35pdk_pads[] = {
|
||||
static const iomux_v3_cfg_t mx35pdk_pads[] __initconst = {
|
||||
/* UART1 */
|
||||
MX35_PAD_CTS1__UART1_CTS,
|
||||
MX35_PAD_RTS1__UART1_RTS,
|
||||
|
@ -129,7 +129,7 @@ static struct platform_device *devices[] __initdata = {
|
||||
&pcm043_flash,
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t pcm043_pads[] = {
|
||||
static const iomux_v3_cfg_t pcm043_pads[] __initconst = {
|
||||
/* UART1 */
|
||||
MX35_PAD_CTS1__UART1_CTS,
|
||||
MX35_PAD_RTS1__UART1_RTS,
|
||||
|
@ -161,7 +161,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
|
||||
}
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t vpr200_pads[] = {
|
||||
static const iomux_v3_cfg_t vpr200_pads[] __initconst = {
|
||||
/* UART1 */
|
||||
MX35_PAD_TXD1__UART1_TXD_MUX,
|
||||
MX35_PAD_RXD1__UART1_RXD_MUX,
|
||||
|
@ -1,89 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 1999,2000 Arm Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
|
||||
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* - add MX31 specific definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "devices/devices-common.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-v3.h"
|
||||
#include "mx25.h"
|
||||
|
||||
/*
|
||||
* This table defines static virtual address mappings for I/O regions.
|
||||
* These are the mappings common across all MX25 boards.
|
||||
*/
|
||||
static struct map_desc mx25_io_desc[] __initdata = {
|
||||
imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
|
||||
imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
|
||||
};
|
||||
|
||||
/*
|
||||
* This function initializes the memory map. It is called during the
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx25_map_io(void)
|
||||
{
|
||||
iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
|
||||
}
|
||||
|
||||
void __init imx25_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX25);
|
||||
mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx25_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct sdma_platform_data imx25_sdma_pdata __initdata = {
|
||||
.fw_name = "sdma-imx25.bin",
|
||||
};
|
||||
|
||||
static const struct resource imx25_audmux_res[] __initconst = {
|
||||
DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
|
||||
};
|
||||
|
||||
void __init imx25_soc_init(void)
|
||||
{
|
||||
mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
|
||||
mxc_device_init();
|
||||
|
||||
/* i.mx25 has the i.mx35 type gpio */
|
||||
mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
|
||||
mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
|
||||
mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
/* i.mx25 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
|
||||
/* i.mx25 has the i.mx31 type audmux */
|
||||
platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
|
||||
ARRAY_SIZE(imx25_audmux_res));
|
||||
}
|
@ -1,117 +0,0 @@
|
||||
#ifndef __MACH_MX25_H__
|
||||
#define __MACH_MX25_H__
|
||||
|
||||
#define MX25_AIPS1_BASE_ADDR 0x43f00000
|
||||
#define MX25_AIPS1_SIZE SZ_1M
|
||||
#define MX25_AIPS2_BASE_ADDR 0x53f00000
|
||||
#define MX25_AIPS2_SIZE SZ_1M
|
||||
#define MX25_AVIC_BASE_ADDR 0x68000000
|
||||
#define MX25_AVIC_SIZE SZ_1M
|
||||
|
||||
#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
|
||||
#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
|
||||
#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
|
||||
#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
|
||||
#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
|
||||
#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
|
||||
#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
|
||||
|
||||
#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
|
||||
#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
|
||||
#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
|
||||
#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
|
||||
#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
|
||||
#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
|
||||
#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
|
||||
#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
|
||||
#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
|
||||
#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
|
||||
#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
|
||||
|
||||
#define MX25_UART1_BASE_ADDR 0x43f90000
|
||||
#define MX25_UART2_BASE_ADDR 0x43f94000
|
||||
#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
|
||||
#define MX25_UART3_BASE_ADDR 0x5000c000
|
||||
#define MX25_UART4_BASE_ADDR 0x50008000
|
||||
#define MX25_UART5_BASE_ADDR 0x5002c000
|
||||
|
||||
#define MX25_CSPI3_BASE_ADDR 0x50004000
|
||||
#define MX25_CSPI2_BASE_ADDR 0x50010000
|
||||
#define MX25_FEC_BASE_ADDR 0x50038000
|
||||
#define MX25_SSI2_BASE_ADDR 0x50014000
|
||||
#define MX25_SSI1_BASE_ADDR 0x50034000
|
||||
#define MX25_NFC_BASE_ADDR 0xbb000000
|
||||
#define MX25_IIM_BASE_ADDR 0x53ff0000
|
||||
#define MX25_DRYICE_BASE_ADDR 0x53ffc000
|
||||
#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
|
||||
#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
|
||||
#define MX25_LCDC_BASE_ADDR 0x53fbc000
|
||||
#define MX25_KPP_BASE_ADDR 0x43fa8000
|
||||
#define MX25_SDMA_BASE_ADDR 0x53fd4000
|
||||
#define MX25_USB_BASE_ADDR 0x53ff4000
|
||||
#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
|
||||
/*
|
||||
* The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
|
||||
* for the host controller. Early documentation drafts specified 0x400 and
|
||||
* Freescale internal sources confirm only the latter value to work.
|
||||
*/
|
||||
#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
|
||||
#define MX25_CSI_BASE_ADDR 0x53ff8000
|
||||
|
||||
#define MX25_IO_P2V(x) IMX_IO_P2V(x)
|
||||
#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
|
||||
|
||||
/*
|
||||
* Interrupt numbers
|
||||
*/
|
||||
#include <asm/irq.h>
|
||||
#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
|
||||
#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
|
||||
#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
|
||||
#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
|
||||
#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
|
||||
#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
|
||||
#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
|
||||
#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
|
||||
#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
|
||||
#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
|
||||
#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
|
||||
#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
|
||||
#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
|
||||
#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
|
||||
#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
|
||||
#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
|
||||
#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
|
||||
#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
|
||||
#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
|
||||
#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
|
||||
#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
|
||||
#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
|
||||
#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
|
||||
#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
|
||||
#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
|
||||
#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
|
||||
#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
|
||||
#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
|
||||
#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
|
||||
#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
|
||||
#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
|
||||
#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
|
||||
#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
|
||||
#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
|
||||
#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
|
||||
|
||||
#define MX25_DMA_REQ_SSI2_RX1 22
|
||||
#define MX25_DMA_REQ_SSI2_TX1 23
|
||||
#define MX25_DMA_REQ_SSI2_RX0 24
|
||||
#define MX25_DMA_REQ_SSI2_TX0 25
|
||||
#define MX25_DMA_REQ_SSI1_RX1 26
|
||||
#define MX25_DMA_REQ_SSI1_TX1 27
|
||||
#define MX25_DMA_REQ_SSI1_RX0 28
|
||||
#define MX25_DMA_REQ_SSI1_TX0 29
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern int mx25_revision(void);
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __MACH_MX25_H__ */
|
@ -1,109 +0,0 @@
|
||||
if ARCH_MSM
|
||||
|
||||
choice
|
||||
prompt "Qualcomm MSM SoC Type"
|
||||
default ARCH_MSM7X00A
|
||||
depends on ARCH_MSM
|
||||
|
||||
config ARCH_MSM7X00A
|
||||
bool "MSM7x00A / MSM7x01A"
|
||||
select ARCH_MSM_ARM11
|
||||
select CPU_V6
|
||||
select GPIO_MSM_V1
|
||||
select MACH_TROUT if !MACH_HALIBUT
|
||||
select MSM_PROC_COMM
|
||||
select MSM_SMD
|
||||
select CLKSRC_QCOM
|
||||
select MSM_SMD_PKG3
|
||||
|
||||
config ARCH_MSM7X30
|
||||
bool "MSM7x30"
|
||||
select ARCH_MSM_SCORPION
|
||||
select CPU_V7
|
||||
select GPIO_MSM_V1
|
||||
select MACH_MSM7X30_SURF # if !
|
||||
select MSM_GPIOMUX
|
||||
select MSM_PROC_COMM
|
||||
select MSM_SMD
|
||||
select CLKSRC_QCOM
|
||||
select MSM_VIC
|
||||
|
||||
config ARCH_QSD8X50
|
||||
bool "QSD8X50"
|
||||
select ARCH_MSM_SCORPION
|
||||
select CPU_V7
|
||||
select GPIO_MSM_V1
|
||||
select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5
|
||||
select MSM_GPIOMUX
|
||||
select MSM_PROC_COMM
|
||||
select MSM_SMD
|
||||
select CLKSRC_QCOM
|
||||
select MSM_VIC
|
||||
|
||||
endchoice
|
||||
|
||||
config MSM_SOC_REV_A
|
||||
bool
|
||||
|
||||
config ARCH_MSM_ARM11
|
||||
bool
|
||||
|
||||
config ARCH_MSM_SCORPION
|
||||
bool
|
||||
|
||||
config MSM_VIC
|
||||
bool
|
||||
|
||||
menu "Qualcomm MSM Board Type"
|
||||
depends on ARCH_MSM
|
||||
|
||||
config MACH_HALIBUT
|
||||
depends on ARCH_MSM
|
||||
depends on ARCH_MSM7X00A
|
||||
bool "Halibut Board (QCT SURF7201A)"
|
||||
help
|
||||
Support for the Qualcomm SURF7201A eval board.
|
||||
|
||||
config MACH_TROUT
|
||||
depends on ARCH_MSM
|
||||
depends on ARCH_MSM7X00A
|
||||
bool "HTC Dream (aka trout)"
|
||||
help
|
||||
Support for the HTC Dream, T-Mobile G1, Android ADP1 devices.
|
||||
|
||||
config MACH_MSM7X30_SURF
|
||||
depends on ARCH_MSM7X30
|
||||
bool "MSM7x30 SURF"
|
||||
help
|
||||
Support for the Qualcomm MSM7x30 SURF eval board.
|
||||
|
||||
config MACH_QSD8X50_SURF
|
||||
depends on ARCH_QSD8X50
|
||||
bool "QSD8x50 SURF"
|
||||
help
|
||||
Support for the Qualcomm QSD8x50 SURF eval board.
|
||||
|
||||
config MACH_QSD8X50A_ST1_5
|
||||
depends on ARCH_QSD8X50
|
||||
bool "QSD8x50A ST1.5"
|
||||
select MSM_SOC_REV_A
|
||||
help
|
||||
Support for the Qualcomm ST1.5.
|
||||
|
||||
endmenu
|
||||
|
||||
config MSM_SMD_PKG3
|
||||
bool
|
||||
|
||||
config MSM_PROC_COMM
|
||||
bool
|
||||
|
||||
config MSM_SMD
|
||||
bool
|
||||
|
||||
config MSM_GPIOMUX
|
||||
bool
|
||||
help
|
||||
Support for MSM V1 TLMM GPIOMUX architecture.
|
||||
|
||||
endif
|
@ -1,23 +0,0 @@
|
||||
obj-$(CONFIG_MSM_PROC_COMM) += clock.o
|
||||
|
||||
obj-$(CONFIG_MSM_VIC) += irq-vic.o
|
||||
|
||||
obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
|
||||
|
||||
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
|
||||
|
||||
obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
|
||||
|
||||
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
|
||||
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
|
||||
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
|
||||
obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
|
||||
obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
|
@ -1,3 +0,0 @@
|
||||
zreladdr-y += 0x10008000
|
||||
params_phys-y := 0x10000100
|
||||
initrd_phys-y := 0x10800000
|
@ -1,110 +0,0 @@
|
||||
/* linux/arch/arm/mach-msm/board-halibut.c
|
||||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Author: Brian Swetland <swetland@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/flash.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "common.h"
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x9C004300,
|
||||
.end = 0x9C004400,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = MSM_GPIO_TO_INT(49),
|
||||
.end = MSM_GPIO_TO_INT(49),
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smc91x_platdata smc91x_platdata = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
.dev.platform_data = &smc91x_platdata,
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&msm_clock_7x01a,
|
||||
&msm_device_gpio_7201,
|
||||
&msm_device_uart3,
|
||||
&msm_device_smd,
|
||||
&msm_device_nand,
|
||||
&msm_device_hsusb,
|
||||
&msm_device_i2c,
|
||||
&smc91x_device,
|
||||
};
|
||||
|
||||
static void __init halibut_init_early(void)
|
||||
{
|
||||
arch_ioremap_caller = __msm_ioremap_caller;
|
||||
}
|
||||
|
||||
static void __init halibut_init_irq(void)
|
||||
{
|
||||
msm_init_irq();
|
||||
}
|
||||
|
||||
static void __init halibut_init(void)
|
||||
{
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
||||
static void __init halibut_map_io(void)
|
||||
{
|
||||
msm_map_common_io();
|
||||
}
|
||||
|
||||
static void __init halibut_init_late(void)
|
||||
{
|
||||
smd_debugfs_init();
|
||||
}
|
||||
|
||||
MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = halibut_map_io,
|
||||
.init_early = halibut_init_early,
|
||||
.init_irq = halibut_init_irq,
|
||||
.init_machine = halibut_init,
|
||||
.init_late = halibut_init_late,
|
||||
.init_time = msm7x01_timer_init,
|
||||
MACHINE_END
|
@ -1,191 +0,0 @@
|
||||
/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/usb/msm_hsusb.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#include <mach/clk.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <mach/vreg.h>
|
||||
#include "devices.h"
|
||||
#include "gpiomux.h"
|
||||
#include "proc_comm.h"
|
||||
#include "common.h"
|
||||
|
||||
static void __init msm7x30_fixup(struct tag *tag, char **cmdline)
|
||||
{
|
||||
for (; tag->hdr.size; tag = tag_next(tag))
|
||||
if (tag->hdr.tag == ATAG_MEM && tag->u.mem.start == 0x200000) {
|
||||
tag->u.mem.start = 0;
|
||||
tag->u.mem.size += SZ_2M;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init msm7x30_reserve(void)
|
||||
{
|
||||
memblock_remove(0x0, SZ_2M);
|
||||
}
|
||||
|
||||
static int hsusb_phy_init_seq[] = {
|
||||
0x30, 0x32, /* Enable and set Pre-Emphasis Depth to 20% */
|
||||
0x02, 0x36, /* Disable CDR Auto Reset feature */
|
||||
-1
|
||||
};
|
||||
|
||||
static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (assert) {
|
||||
ret = clk_reset(link_clk, CLK_RESET_ASSERT);
|
||||
if (ret)
|
||||
pr_err("usb hs_clk assert failed\n");
|
||||
} else {
|
||||
ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
|
||||
if (ret)
|
||||
pr_err("usb hs_clk deassert failed\n");
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hsusb_phy_clk_reset(struct clk *phy_clk)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
|
||||
if (ret) {
|
||||
pr_err("usb phy clk assert failed\n");
|
||||
return ret;
|
||||
}
|
||||
usleep_range(10000, 12000);
|
||||
ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
|
||||
if (ret)
|
||||
pr_err("usb phy clk deassert failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct msm_otg_platform_data msm_otg_pdata = {
|
||||
.phy_init_seq = hsusb_phy_init_seq,
|
||||
.mode = USB_DR_MODE_PERIPHERAL,
|
||||
.otg_control = OTG_PHY_CONTROL,
|
||||
.link_clk_reset = hsusb_link_clk_reset,
|
||||
.phy_clk_reset = hsusb_phy_clk_reset,
|
||||
};
|
||||
|
||||
struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
|
||||
#ifdef CONFIG_SERIAL_MSM_CONSOLE
|
||||
[49] = { /* UART2 RFR */
|
||||
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
|
||||
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
|
||||
},
|
||||
[50] = { /* UART2 CTS */
|
||||
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
|
||||
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
|
||||
},
|
||||
[51] = { /* UART2 RX */
|
||||
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
|
||||
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
|
||||
},
|
||||
[52] = { /* UART2 TX */
|
||||
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
|
||||
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&msm_clock_7x30,
|
||||
&msm_device_gpio_7x30,
|
||||
#if defined(CONFIG_SERIAL_MSM)
|
||||
&msm_device_uart2,
|
||||
#endif
|
||||
&msm_device_smd,
|
||||
&msm_device_otg,
|
||||
&msm_device_hsusb,
|
||||
&msm_device_hsusb_host,
|
||||
};
|
||||
|
||||
static void __init msm7x30_init_irq(void)
|
||||
{
|
||||
msm_init_irq();
|
||||
}
|
||||
|
||||
static void __init msm7x30_init(void)
|
||||
{
|
||||
msm_device_otg.dev.platform_data = &msm_otg_pdata;
|
||||
msm_device_hsusb.dev.parent = &msm_device_otg.dev;
|
||||
msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
|
||||
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
||||
static void __init msm7x30_map_io(void)
|
||||
{
|
||||
msm_map_msm7x30_io();
|
||||
}
|
||||
|
||||
static void __init msm7x30_init_late(void)
|
||||
{
|
||||
smd_debugfs_init();
|
||||
}
|
||||
|
||||
MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
|
||||
.atag_offset = 0x100,
|
||||
.fixup = msm7x30_fixup,
|
||||
.reserve = msm7x30_reserve,
|
||||
.map_io = msm7x30_map_io,
|
||||
.init_irq = msm7x30_init_irq,
|
||||
.init_machine = msm7x30_init,
|
||||
.init_late = msm7x30_init_late,
|
||||
.init_time = msm7x30_timer_init,
|
||||
MACHINE_END
|
||||
|
||||
MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
|
||||
.atag_offset = 0x100,
|
||||
.fixup = msm7x30_fixup,
|
||||
.reserve = msm7x30_reserve,
|
||||
.map_io = msm7x30_map_io,
|
||||
.init_irq = msm7x30_init_irq,
|
||||
.init_machine = msm7x30_init,
|
||||
.init_late = msm7x30_init_late,
|
||||
.init_time = msm7x30_timer_init,
|
||||
MACHINE_END
|
||||
|
||||
MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
|
||||
.atag_offset = 0x100,
|
||||
.fixup = msm7x30_fixup,
|
||||
.reserve = msm7x30_reserve,
|
||||
.map_io = msm7x30_map_io,
|
||||
.init_irq = msm7x30_init_irq,
|
||||
.init_machine = msm7x30_init,
|
||||
.init_late = msm7x30_init_late,
|
||||
.init_time = msm7x30_timer_init,
|
||||
MACHINE_END
|
@ -1,254 +0,0 @@
|
||||
/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/usb/msm_hsusb.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/sirc.h>
|
||||
#include <mach/vreg.h>
|
||||
#include <mach/clk.h>
|
||||
#include <linux/platform_data/mmc-msm_sdcc.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "common.h"
|
||||
|
||||
static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
|
||||
static const unsigned qsd8x50_surf_smc91x_gpio __initconst = 156;
|
||||
|
||||
/* Leave smc91x resources empty here, as we'll fill them in
|
||||
* at run-time: they vary from board to board, and the true
|
||||
* configuration won't be known until boot.
|
||||
*/
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smc91x_platdata smc91x_platdata = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
.dev.platform_data = &smc91x_platdata,
|
||||
};
|
||||
|
||||
static int __init msm_init_smc91x(void)
|
||||
{
|
||||
if (machine_is_qsd8x50_surf()) {
|
||||
smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
|
||||
smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
|
||||
smc91x_resources[1].start =
|
||||
gpio_to_irq(qsd8x50_surf_smc91x_gpio);
|
||||
smc91x_resources[1].end =
|
||||
gpio_to_irq(qsd8x50_surf_smc91x_gpio);
|
||||
platform_device_register(&smc91x_device);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
module_init(msm_init_smc91x);
|
||||
|
||||
static int hsusb_phy_init_seq[] = {
|
||||
0x08, 0x31, /* Increase HS Driver Amplitude */
|
||||
0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */
|
||||
-1
|
||||
};
|
||||
|
||||
static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (assert) {
|
||||
ret = clk_reset(link_clk, CLK_RESET_ASSERT);
|
||||
if (ret)
|
||||
pr_err("usb hs_clk assert failed\n");
|
||||
} else {
|
||||
ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
|
||||
if (ret)
|
||||
pr_err("usb hs_clk deassert failed\n");
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hsusb_phy_clk_reset(struct clk *phy_clk)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
|
||||
if (ret) {
|
||||
pr_err("usb phy clk assert failed\n");
|
||||
return ret;
|
||||
}
|
||||
usleep_range(10000, 12000);
|
||||
ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
|
||||
if (ret)
|
||||
pr_err("usb phy clk deassert failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct msm_otg_platform_data msm_otg_pdata = {
|
||||
.phy_init_seq = hsusb_phy_init_seq,
|
||||
.mode = USB_DR_MODE_PERIPHERAL,
|
||||
.otg_control = OTG_PHY_CONTROL,
|
||||
.link_clk_reset = hsusb_link_clk_reset,
|
||||
.phy_clk_reset = hsusb_phy_clk_reset,
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&msm_clock_8x50,
|
||||
&msm_device_gpio_8x50,
|
||||
&msm_device_uart3,
|
||||
&msm_device_smd,
|
||||
&msm_device_otg,
|
||||
&msm_device_hsusb,
|
||||
&msm_device_hsusb_host,
|
||||
};
|
||||
|
||||
static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
|
||||
{51, "sdc1_dat_3"},
|
||||
{52, "sdc1_dat_2"},
|
||||
{53, "sdc1_dat_1"},
|
||||
{54, "sdc1_dat_0"},
|
||||
{55, "sdc1_cmd"},
|
||||
{56, "sdc1_clk"}
|
||||
};
|
||||
|
||||
static struct vreg *vreg_mmc;
|
||||
static unsigned long vreg_sts;
|
||||
|
||||
static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
|
||||
{
|
||||
int rc = 0;
|
||||
struct platform_device *pdev;
|
||||
|
||||
pdev = container_of(dv, struct platform_device, dev);
|
||||
|
||||
if (vdd == 0) {
|
||||
if (!vreg_sts)
|
||||
return 0;
|
||||
|
||||
clear_bit(pdev->id, &vreg_sts);
|
||||
|
||||
if (!vreg_sts) {
|
||||
rc = vreg_disable(vreg_mmc);
|
||||
if (rc)
|
||||
pr_err("vreg_mmc disable failed for slot "
|
||||
"%d: %d\n", pdev->id, rc);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!vreg_sts) {
|
||||
rc = vreg_set_level(vreg_mmc, 2900);
|
||||
if (rc)
|
||||
pr_err("vreg_mmc set level failed for slot %d: %d\n",
|
||||
pdev->id, rc);
|
||||
rc = vreg_enable(vreg_mmc);
|
||||
if (rc)
|
||||
pr_err("vreg_mmc enable failed for slot %d: %d\n",
|
||||
pdev->id, rc);
|
||||
}
|
||||
set_bit(pdev->id, &vreg_sts);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct msm_mmc_gpio_data sdc1_gpio = {
|
||||
.gpio = sdc1_gpio_cfg,
|
||||
.size = ARRAY_SIZE(sdc1_gpio_cfg),
|
||||
};
|
||||
|
||||
static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.translate_vdd = msm_sdcc_setup_power,
|
||||
.gpio_data = &sdc1_gpio,
|
||||
};
|
||||
|
||||
static void __init qsd8x50_init_mmc(void)
|
||||
{
|
||||
vreg_mmc = vreg_get(NULL, "gp5");
|
||||
|
||||
if (IS_ERR(vreg_mmc)) {
|
||||
pr_err("vreg get for vreg_mmc failed (%ld)\n",
|
||||
PTR_ERR(vreg_mmc));
|
||||
return;
|
||||
}
|
||||
|
||||
msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
|
||||
}
|
||||
|
||||
static void __init qsd8x50_map_io(void)
|
||||
{
|
||||
msm_map_qsd8x50_io();
|
||||
}
|
||||
|
||||
static void __init qsd8x50_init_irq(void)
|
||||
{
|
||||
msm_init_irq();
|
||||
msm_init_sirc();
|
||||
}
|
||||
|
||||
static void __init qsd8x50_init(void)
|
||||
{
|
||||
msm_device_otg.dev.platform_data = &msm_otg_pdata;
|
||||
msm_device_hsusb.dev.parent = &msm_device_otg.dev;
|
||||
msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
qsd8x50_init_mmc();
|
||||
}
|
||||
|
||||
static void __init qsd8x50_init_late(void)
|
||||
{
|
||||
smd_debugfs_init();
|
||||
}
|
||||
|
||||
MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = qsd8x50_map_io,
|
||||
.init_irq = qsd8x50_init_irq,
|
||||
.init_machine = qsd8x50_init,
|
||||
.init_late = qsd8x50_init_late,
|
||||
.init_time = qsd8x50_timer_init,
|
||||
MACHINE_END
|
||||
|
||||
MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = qsd8x50_map_io,
|
||||
.init_irq = qsd8x50_init_irq,
|
||||
.init_machine = qsd8x50_init,
|
||||
.init_late = qsd8x50_init_late,
|
||||
.init_time = qsd8x50_timer_init,
|
||||
MACHINE_END
|
@ -1,114 +0,0 @@
|
||||
/* linux/arch/arm/mach-msm/board-sapphire.c
|
||||
* Copyright (C) 2007-2009 HTC Corporation.
|
||||
* Author: Thomas Tsai <thomas_tsai@htc.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/flash.h>
|
||||
#include <mach/vreg.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/delay.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
#include "gpio_chip.h"
|
||||
#include "board-sapphire.h"
|
||||
#include "proc_comm.h"
|
||||
#include "devices.h"
|
||||
#include "common.h"
|
||||
|
||||
void msm_init_irq(void);
|
||||
void msm_init_gpio(void);
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&msm_device_smd,
|
||||
&msm_device_dmov,
|
||||
&msm_device_nand,
|
||||
&msm_device_uart1,
|
||||
&msm_device_uart3,
|
||||
};
|
||||
|
||||
void msm_timer_init(void);
|
||||
|
||||
static void __init sapphire_init_irq(void)
|
||||
{
|
||||
msm_init_irq();
|
||||
}
|
||||
|
||||
static void __init sapphire_init(void)
|
||||
{
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
||||
static struct map_desc sapphire_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = SAPPHIRE_CPLD_BASE,
|
||||
.pfn = __phys_to_pfn(SAPPHIRE_CPLD_START),
|
||||
.length = SAPPHIRE_CPLD_SIZE,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
}
|
||||
};
|
||||
|
||||
static void __init sapphire_fixup(struct tag *tags, char **cmdline)
|
||||
{
|
||||
int smi_sz = parse_tag_smi((const struct tag *)tags);
|
||||
|
||||
if (smi_sz == 32) {
|
||||
memblock_add(PHYS_OFFSET, 84*SZ_1M);
|
||||
} else if (smi_sz == 64) {
|
||||
memblock_add(PHYS_OFFSET, 101*SZ_1M);
|
||||
} else {
|
||||
memblock_add(PHYS_OFFSET, 101*SZ_1M);
|
||||
/* Give a default value when not get smi size */
|
||||
smi_sz = 64;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init sapphire_map_io(void)
|
||||
{
|
||||
msm_map_common_io();
|
||||
iotable_init(sapphire_io_desc, ARRAY_SIZE(sapphire_io_desc));
|
||||
msm_clock_init();
|
||||
}
|
||||
|
||||
static void __init sapphire_init_late(void)
|
||||
{
|
||||
smd_debugfs_init();
|
||||
}
|
||||
|
||||
MACHINE_START(SAPPHIRE, "sapphire")
|
||||
/* Maintainer: Brian Swetland <swetland@google.com> */
|
||||
.atag_offset = 0x100,
|
||||
.fixup = sapphire_fixup,
|
||||
.map_io = sapphire_map_io,
|
||||
.init_irq = sapphire_init_irq,
|
||||
.init_machine = sapphire_init,
|
||||
.init_late = sapphire_init_late,
|
||||
.init_time = msm_timer_init,
|
||||
MACHINE_END
|
@ -1,233 +0,0 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-msm/gpio.c
|
||||
*
|
||||
* Copyright (C) 2005 HP Labs
|
||||
* Copyright (C) 2008 Google, Inc.
|
||||
* Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include "board-trout.h"
|
||||
|
||||
static uint8_t trout_int_mask[2] = {
|
||||
[0] = 0xff, /* mask all interrupts */
|
||||
[1] = 0xff,
|
||||
};
|
||||
static uint8_t trout_sleep_int_mask[] = {
|
||||
[0] = 0xff,
|
||||
[1] = 0xff,
|
||||
};
|
||||
|
||||
struct msm_gpio_chip {
|
||||
struct gpio_chip chip;
|
||||
void __iomem *reg; /* Base of register bank */
|
||||
u8 shadow;
|
||||
};
|
||||
|
||||
#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
|
||||
|
||||
static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
|
||||
unsigned mask = 1 << offset;
|
||||
|
||||
return !!(readb(msm_gpio->reg) & mask);
|
||||
}
|
||||
|
||||
static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
|
||||
{
|
||||
struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
|
||||
unsigned mask = 1 << offset;
|
||||
|
||||
if (val)
|
||||
msm_gpio->shadow |= mask;
|
||||
else
|
||||
msm_gpio->shadow &= ~mask;
|
||||
|
||||
writeb(msm_gpio->shadow, msm_gpio->reg);
|
||||
}
|
||||
|
||||
static int msm_gpiolib_direction_input(struct gpio_chip *chip,
|
||||
unsigned offset)
|
||||
{
|
||||
msm_gpiolib_set(chip, offset, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int msm_gpiolib_direction_output(struct gpio_chip *chip,
|
||||
unsigned offset, int val)
|
||||
{
|
||||
msm_gpiolib_set(chip, offset, val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return TROUT_GPIO_TO_INT(offset + chip->base);
|
||||
}
|
||||
|
||||
#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \
|
||||
{ \
|
||||
.chip = { \
|
||||
.label = name, \
|
||||
.direction_input = msm_gpiolib_direction_input,\
|
||||
.direction_output = msm_gpiolib_direction_output, \
|
||||
.get = msm_gpiolib_get, \
|
||||
.set = msm_gpiolib_set, \
|
||||
.to_irq = trout_gpio_to_irq, \
|
||||
.base = base_gpio, \
|
||||
.ngpio = 8, \
|
||||
}, \
|
||||
.reg = reg_num + TROUT_CPLD_BASE, \
|
||||
.shadow = shadow_val, \
|
||||
}
|
||||
|
||||
static struct msm_gpio_chip msm_gpio_banks[] = {
|
||||
#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9a00000)
|
||||
/* H2W pins <-> UART1 */
|
||||
TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40),
|
||||
#else
|
||||
/* H2W pins <-> UART3, Bluetooth <-> UART1 */
|
||||
TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x80),
|
||||
#endif
|
||||
/* I2C pull */
|
||||
TROUT_GPIO_BANK("MISC3", 0x02, TROUT_GPIO_MISC3_BASE, 0x04),
|
||||
TROUT_GPIO_BANK("MISC4", 0x04, TROUT_GPIO_MISC4_BASE, 0),
|
||||
/* mmdi 32k en */
|
||||
TROUT_GPIO_BANK("MISC5", 0x06, TROUT_GPIO_MISC5_BASE, 0x04),
|
||||
TROUT_GPIO_BANK("INT2", 0x08, TROUT_GPIO_INT2_BASE, 0),
|
||||
TROUT_GPIO_BANK("MISC1", 0x0a, TROUT_GPIO_MISC1_BASE, 0),
|
||||
TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
|
||||
};
|
||||
|
||||
static void trout_gpio_irq_ack(struct irq_data *d)
|
||||
{
|
||||
int bank = TROUT_INT_TO_BANK(d->irq);
|
||||
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
|
||||
int reg = TROUT_BANK_TO_STAT_REG(bank);
|
||||
/*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", d->irq);*/
|
||||
writeb(mask, TROUT_CPLD_BASE + reg);
|
||||
}
|
||||
|
||||
static void trout_gpio_irq_mask(struct irq_data *d)
|
||||
{
|
||||
unsigned long flags;
|
||||
uint8_t reg_val;
|
||||
int bank = TROUT_INT_TO_BANK(d->irq);
|
||||
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
|
||||
int reg = TROUT_BANK_TO_MASK_REG(bank);
|
||||
|
||||
local_irq_save(flags);
|
||||
reg_val = trout_int_mask[bank] |= mask;
|
||||
/*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n",
|
||||
d->irq, bank, reg_val);*/
|
||||
writeb(reg_val, TROUT_CPLD_BASE + reg);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void trout_gpio_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
unsigned long flags;
|
||||
uint8_t reg_val;
|
||||
int bank = TROUT_INT_TO_BANK(d->irq);
|
||||
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
|
||||
int reg = TROUT_BANK_TO_MASK_REG(bank);
|
||||
|
||||
local_irq_save(flags);
|
||||
reg_val = trout_int_mask[bank] &= ~mask;
|
||||
/*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n",
|
||||
d->irq, bank, reg_val);*/
|
||||
writeb(reg_val, TROUT_CPLD_BASE + reg);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
int trout_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
|
||||
{
|
||||
unsigned long flags;
|
||||
int bank = TROUT_INT_TO_BANK(d->irq);
|
||||
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
|
||||
|
||||
local_irq_save(flags);
|
||||
if(on)
|
||||
trout_sleep_int_mask[bank] &= ~mask;
|
||||
else
|
||||
trout_sleep_int_mask[bank] |= mask;
|
||||
local_irq_restore(flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
int j, m;
|
||||
unsigned v;
|
||||
int bank;
|
||||
int stat_reg;
|
||||
int int_base = TROUT_INT_START;
|
||||
uint8_t int_mask;
|
||||
|
||||
for (bank = 0; bank < 2; bank++) {
|
||||
stat_reg = TROUT_BANK_TO_STAT_REG(bank);
|
||||
v = readb(TROUT_CPLD_BASE + stat_reg);
|
||||
int_mask = trout_int_mask[bank];
|
||||
if (v & int_mask) {
|
||||
writeb(v & int_mask, TROUT_CPLD_BASE + stat_reg);
|
||||
printk(KERN_ERR "trout_gpio_irq_handler: got masked "
|
||||
"interrupt: %d:%02x\n", bank, v & int_mask);
|
||||
}
|
||||
v &= ~int_mask;
|
||||
while (v) {
|
||||
m = v & -v;
|
||||
j = fls(m) - 1;
|
||||
/*printk(KERN_INFO "msm_gpio_irq_handler %d:%02x %02x b"
|
||||
"it %d irq %d\n", bank, v, m, j, int_base + j);*/
|
||||
v &= ~m;
|
||||
generic_handle_irq(int_base + j);
|
||||
}
|
||||
int_base += TROUT_INT_BANK0_COUNT;
|
||||
}
|
||||
desc->irq_data.chip->irq_ack(&desc->irq_data);
|
||||
}
|
||||
|
||||
static struct irq_chip trout_gpio_irq_chip = {
|
||||
.name = "troutgpio",
|
||||
.irq_ack = trout_gpio_irq_ack,
|
||||
.irq_mask = trout_gpio_irq_mask,
|
||||
.irq_unmask = trout_gpio_irq_unmask,
|
||||
.irq_set_wake = trout_gpio_irq_set_wake,
|
||||
};
|
||||
|
||||
/*
|
||||
* Called from the processor-specific init to enable GPIO pin support.
|
||||
*/
|
||||
int __init trout_init_gpio(void)
|
||||
{
|
||||
int i;
|
||||
for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
|
||||
irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
|
||||
handle_edge_irq);
|
||||
set_irq_flags(i, IRQF_VALID);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
|
||||
gpiochip_add(&msm_gpio_banks[i].chip);
|
||||
|
||||
irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
|
||||
irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
|
||||
irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
postcore_initcall(trout_init_gpio);
|
||||
|
@ -1,185 +0,0 @@
|
||||
/* linux/arch/arm/mach-msm/board-trout-mmc.c
|
||||
** Author: Brian Swetland <swetland@google.com>
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/sdio_ids.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/debugfs.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <mach/vreg.h>
|
||||
|
||||
#include <linux/platform_data/mmc-msm_sdcc.h>
|
||||
|
||||
#include "devices.h"
|
||||
|
||||
#include "board-trout.h"
|
||||
|
||||
#include "proc_comm.h"
|
||||
|
||||
#define DEBUG_SDSLOT_VDD 1
|
||||
|
||||
/* ---- COMMON ---- */
|
||||
static void config_gpio_table(uint32_t *table, int len)
|
||||
{
|
||||
int n;
|
||||
unsigned id;
|
||||
for(n = 0; n < len; n++) {
|
||||
id = table[n];
|
||||
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &id, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* ---- SDCARD ---- */
|
||||
|
||||
static uint32_t sdcard_on_gpio_table[] = {
|
||||
PCOM_GPIO_CFG(62, 2, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA), /* CLK */
|
||||
PCOM_GPIO_CFG(63, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* CMD */
|
||||
PCOM_GPIO_CFG(64, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT3 */
|
||||
PCOM_GPIO_CFG(65, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT2 */
|
||||
PCOM_GPIO_CFG(66, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT1 */
|
||||
PCOM_GPIO_CFG(67, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT0 */
|
||||
};
|
||||
|
||||
static uint32_t sdcard_off_gpio_table[] = {
|
||||
PCOM_GPIO_CFG(62, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CLK */
|
||||
PCOM_GPIO_CFG(63, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CMD */
|
||||
PCOM_GPIO_CFG(64, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT3 */
|
||||
PCOM_GPIO_CFG(65, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT2 */
|
||||
PCOM_GPIO_CFG(66, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT1 */
|
||||
PCOM_GPIO_CFG(67, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT0 */
|
||||
};
|
||||
|
||||
static uint opt_disable_sdcard;
|
||||
|
||||
static int __init trout_disablesdcard_setup(char *str)
|
||||
{
|
||||
int cal = simple_strtol(str, NULL, 0);
|
||||
|
||||
opt_disable_sdcard = cal;
|
||||
return 1;
|
||||
}
|
||||
|
||||
__setup("board_trout.disable_sdcard=", trout_disablesdcard_setup);
|
||||
|
||||
static struct vreg *vreg_sdslot; /* SD slot power */
|
||||
|
||||
struct mmc_vdd_xlat {
|
||||
int mask;
|
||||
int level;
|
||||
};
|
||||
|
||||
static struct mmc_vdd_xlat mmc_vdd_table[] = {
|
||||
{ MMC_VDD_165_195, 1800 },
|
||||
{ MMC_VDD_20_21, 2050 },
|
||||
{ MMC_VDD_21_22, 2150 },
|
||||
{ MMC_VDD_22_23, 2250 },
|
||||
{ MMC_VDD_23_24, 2350 },
|
||||
{ MMC_VDD_24_25, 2450 },
|
||||
{ MMC_VDD_25_26, 2550 },
|
||||
{ MMC_VDD_26_27, 2650 },
|
||||
{ MMC_VDD_27_28, 2750 },
|
||||
{ MMC_VDD_28_29, 2850 },
|
||||
{ MMC_VDD_29_30, 2950 },
|
||||
};
|
||||
|
||||
static unsigned int sdslot_vdd = 0xffffffff;
|
||||
static unsigned int sdslot_vreg_enabled;
|
||||
|
||||
static uint32_t trout_sdslot_switchvdd(struct device *dev, unsigned int vdd)
|
||||
{
|
||||
int i, rc;
|
||||
|
||||
BUG_ON(!vreg_sdslot);
|
||||
|
||||
if (vdd == sdslot_vdd)
|
||||
return 0;
|
||||
|
||||
sdslot_vdd = vdd;
|
||||
|
||||
if (vdd == 0) {
|
||||
#if DEBUG_SDSLOT_VDD
|
||||
printk("%s: Disabling SD slot power\n", __func__);
|
||||
#endif
|
||||
config_gpio_table(sdcard_off_gpio_table,
|
||||
ARRAY_SIZE(sdcard_off_gpio_table));
|
||||
vreg_disable(vreg_sdslot);
|
||||
sdslot_vreg_enabled = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!sdslot_vreg_enabled) {
|
||||
rc = vreg_enable(vreg_sdslot);
|
||||
if (rc) {
|
||||
printk(KERN_ERR "%s: Error enabling vreg (%d)\n",
|
||||
__func__, rc);
|
||||
}
|
||||
config_gpio_table(sdcard_on_gpio_table,
|
||||
ARRAY_SIZE(sdcard_on_gpio_table));
|
||||
sdslot_vreg_enabled = 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mmc_vdd_table); i++) {
|
||||
if (mmc_vdd_table[i].mask == (1 << vdd)) {
|
||||
#if DEBUG_SDSLOT_VDD
|
||||
printk("%s: Setting level to %u\n",
|
||||
__func__, mmc_vdd_table[i].level);
|
||||
#endif
|
||||
rc = vreg_set_level(vreg_sdslot,
|
||||
mmc_vdd_table[i].level);
|
||||
if (rc) {
|
||||
printk(KERN_ERR
|
||||
"%s: Error setting vreg level (%d)\n",
|
||||
__func__, rc);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
printk(KERN_ERR "%s: Invalid VDD %d specified\n", __func__, vdd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int trout_sdslot_status(struct device *dev)
|
||||
{
|
||||
unsigned int status;
|
||||
|
||||
status = (unsigned int) gpio_get_value(TROUT_GPIO_SDMC_CD_N);
|
||||
return (!status);
|
||||
}
|
||||
|
||||
#define TROUT_MMC_VDD MMC_VDD_165_195 | MMC_VDD_20_21 | MMC_VDD_21_22 \
|
||||
| MMC_VDD_22_23 | MMC_VDD_23_24 | MMC_VDD_24_25 \
|
||||
| MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 \
|
||||
| MMC_VDD_28_29 | MMC_VDD_29_30
|
||||
|
||||
static struct msm_mmc_platform_data trout_sdslot_data = {
|
||||
.ocr_mask = TROUT_MMC_VDD,
|
||||
.status = trout_sdslot_status,
|
||||
.translate_vdd = trout_sdslot_switchvdd,
|
||||
};
|
||||
|
||||
int __init trout_init_mmc(unsigned int sys_rev)
|
||||
{
|
||||
sdslot_vreg_enabled = 0;
|
||||
|
||||
vreg_sdslot = vreg_get(0, "gp6");
|
||||
if (IS_ERR(vreg_sdslot))
|
||||
return PTR_ERR(vreg_sdslot);
|
||||
|
||||
irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
|
||||
|
||||
if (!opt_disable_sdcard)
|
||||
msm_add_sdcc(2, &trout_sdslot_data,
|
||||
TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 0);
|
||||
else
|
||||
printk(KERN_INFO "trout: SD-Card interface disabled\n");
|
||||
return 0;
|
||||
}
|
||||
|
@ -1,292 +0,0 @@
|
||||
/* linux/arch/arm/mach-msm/board-trout-mddi.c
|
||||
** Author: Brian Swetland <swetland@google.com>
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/system_info.h>
|
||||
|
||||
#include <linux/platform_data/video-msm_fb.h>
|
||||
#include <mach/vreg.h>
|
||||
|
||||
#include "board-trout.h"
|
||||
#include "proc_comm.h"
|
||||
#include "clock-pcom.h"
|
||||
#include "devices.h"
|
||||
|
||||
#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
|
||||
|
||||
#define MDDI_CLIENT_CORE_BASE 0x108000
|
||||
#define LCD_CONTROL_BLOCK_BASE 0x110000
|
||||
#define SPI_BLOCK_BASE 0x120000
|
||||
#define I2C_BLOCK_BASE 0x130000
|
||||
#define PWM_BLOCK_BASE 0x140000
|
||||
#define GPIO_BLOCK_BASE 0x150000
|
||||
#define SYSTEM_BLOCK1_BASE 0x160000
|
||||
#define SYSTEM_BLOCK2_BASE 0x170000
|
||||
|
||||
|
||||
#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
|
||||
#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C)
|
||||
#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
|
||||
|
||||
#define V_VDDE2E_VDD2_GPIO 0
|
||||
#define MDDI_RST_N 82
|
||||
|
||||
#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
|
||||
#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
|
||||
#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
|
||||
#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
|
||||
#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
|
||||
#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
|
||||
#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
|
||||
#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
|
||||
#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
|
||||
#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
|
||||
#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
|
||||
#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
|
||||
#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
|
||||
#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
|
||||
#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
|
||||
#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
|
||||
#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
|
||||
#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
|
||||
#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
|
||||
#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
|
||||
#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
|
||||
#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
|
||||
|
||||
#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
|
||||
#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
|
||||
#define START (LCD_CONTROL_BLOCK_BASE|0x08)
|
||||
#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
|
||||
#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
|
||||
#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
|
||||
#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
|
||||
#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
|
||||
#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
|
||||
#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
|
||||
#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
|
||||
#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
|
||||
#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
|
||||
#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
|
||||
#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
|
||||
#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
|
||||
#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
|
||||
#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
|
||||
#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
|
||||
#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
|
||||
#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
|
||||
#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
|
||||
#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
|
||||
#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
|
||||
#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
|
||||
#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
|
||||
#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
|
||||
#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
|
||||
#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
|
||||
#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
|
||||
#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
|
||||
#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
|
||||
#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
|
||||
#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
|
||||
#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
|
||||
|
||||
#define SSICTL (SPI_BLOCK_BASE|0x00)
|
||||
#define SSITIME (SPI_BLOCK_BASE|0x04)
|
||||
#define SSITX (SPI_BLOCK_BASE|0x08)
|
||||
#define SSIRX (SPI_BLOCK_BASE|0x0C)
|
||||
#define SSIINTC (SPI_BLOCK_BASE|0x10)
|
||||
#define SSIINTS (SPI_BLOCK_BASE|0x14)
|
||||
#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
|
||||
#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
|
||||
#define SSIID (SPI_BLOCK_BASE|0x20)
|
||||
|
||||
#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
|
||||
#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
|
||||
#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
|
||||
#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
|
||||
#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
|
||||
|
||||
#define GPIODATA (GPIO_BLOCK_BASE|0x00)
|
||||
#define GPIODIR (GPIO_BLOCK_BASE|0x04)
|
||||
#define GPIOIS (GPIO_BLOCK_BASE|0x08)
|
||||
#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
|
||||
#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
|
||||
#define GPIOIE (GPIO_BLOCK_BASE|0x14)
|
||||
#define GPIORIS (GPIO_BLOCK_BASE|0x18)
|
||||
#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
|
||||
#define GPIOIC (GPIO_BLOCK_BASE|0x20)
|
||||
#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
|
||||
#define GPIOPC (GPIO_BLOCK_BASE|0x28)
|
||||
#define GPIOID (GPIO_BLOCK_BASE|0x30)
|
||||
|
||||
#define SPI_WRITE(reg, val) \
|
||||
{ SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
|
||||
{ 0, 5 },
|
||||
|
||||
#define SPI_WRITE1(reg) \
|
||||
{ SSITX, (reg) & 0xff }, \
|
||||
{ 0, 5 },
|
||||
|
||||
struct mddi_table {
|
||||
uint32_t reg;
|
||||
uint32_t value;
|
||||
};
|
||||
static struct mddi_table mddi_toshiba_init_table[] = {
|
||||
{ DPSET0, 0x09e90046 },
|
||||
{ DPSET1, 0x00000118 },
|
||||
{ DPSUS, 0x00000000 },
|
||||
{ DPRUN, 0x00000001 },
|
||||
{ 1, 14 }, /* msleep 14 */
|
||||
{ SYSCKENA, 0x00000001 },
|
||||
{ CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */
|
||||
|
||||
{ GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
|
||||
{ GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */
|
||||
{ GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */
|
||||
{ GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */
|
||||
{ WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */
|
||||
|
||||
{ GPIOIBE, 0x000003FF },
|
||||
{ GPIOIS, 0x00000000 },
|
||||
{ GPIOIC, 0x000003FF },
|
||||
{ GPIOIE, 0x00000000 },
|
||||
|
||||
{ GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
|
||||
{ 1, 1 }, /* msleep 1 */
|
||||
{ GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
|
||||
{ DRAMPWR, 0x00000001 }, /* eDRAM power */
|
||||
};
|
||||
|
||||
#define GPIOSEL_VWAKEINT (1U << 0)
|
||||
#define INTMASK_VWAKEOUT (1U << 0)
|
||||
|
||||
|
||||
static int trout_new_backlight = 1;
|
||||
static struct vreg *vreg_mddi_1v5;
|
||||
static struct vreg *vreg_lcm_2v85;
|
||||
|
||||
static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
|
||||
struct mddi_table *table, size_t count)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < count; i++) {
|
||||
uint32_t reg = table[i].reg;
|
||||
uint32_t value = table[i].value;
|
||||
|
||||
if (reg == 0)
|
||||
udelay(value);
|
||||
else if (reg == 1)
|
||||
msleep(value);
|
||||
else
|
||||
client_data->remote_write(client_data, value, reg);
|
||||
}
|
||||
}
|
||||
|
||||
static int trout_mddi_toshiba_client_init(
|
||||
struct msm_mddi_bridge_platform_data *bridge_data,
|
||||
struct msm_mddi_client_data *client_data)
|
||||
{
|
||||
int panel_id;
|
||||
|
||||
client_data->auto_hibernate(client_data, 0);
|
||||
trout_process_mddi_table(client_data, mddi_toshiba_init_table,
|
||||
ARRAY_SIZE(mddi_toshiba_init_table));
|
||||
client_data->auto_hibernate(client_data, 1);
|
||||
panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
|
||||
if (panel_id > 1) {
|
||||
printk(KERN_WARNING "unknown panel id at mddi_enable\n");
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int trout_mddi_toshiba_client_uninit(
|
||||
struct msm_mddi_bridge_platform_data *bridge_data,
|
||||
struct msm_mddi_client_data *client_data)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct resource resources_msm_fb[] = {
|
||||
{
|
||||
.start = MSM_FB_BASE,
|
||||
.end = MSM_FB_BASE + MSM_FB_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
struct msm_mddi_bridge_platform_data toshiba_client_data = {
|
||||
.init = trout_mddi_toshiba_client_init,
|
||||
.uninit = trout_mddi_toshiba_client_uninit,
|
||||
.fb_data = {
|
||||
.xres = 320,
|
||||
.yres = 480,
|
||||
.width = 45,
|
||||
.height = 67,
|
||||
.output_format = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mddi_platform_data mddi_pdata = {
|
||||
.clk_rate = 122880000,
|
||||
.fb_resource = resources_msm_fb,
|
||||
.num_clients = 1,
|
||||
.client_platform_data = {
|
||||
{
|
||||
.product_id = (0xd263 << 16 | 0),
|
||||
.name = "mddi_c_d263_0000",
|
||||
.id = 0,
|
||||
.client_data = &toshiba_client_data,
|
||||
.clk_rate = 0,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
int __init trout_init_panel(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!machine_is_trout())
|
||||
return 0;
|
||||
vreg_mddi_1v5 = vreg_get(0, "gp2");
|
||||
if (IS_ERR(vreg_mddi_1v5))
|
||||
return PTR_ERR(vreg_mddi_1v5);
|
||||
vreg_lcm_2v85 = vreg_get(0, "gp4");
|
||||
if (IS_ERR(vreg_lcm_2v85))
|
||||
return PTR_ERR(vreg_lcm_2v85);
|
||||
|
||||
trout_new_backlight = system_rev >= 5;
|
||||
if (trout_new_backlight) {
|
||||
uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
|
||||
GPIO_NO_PULL, GPIO_8MA);
|
||||
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
|
||||
} else {
|
||||
uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
|
||||
GPIO_NO_PULL, GPIO_8MA);
|
||||
uint32_t id = P_GP_CLK;
|
||||
uint32_t rate = 19200000;
|
||||
|
||||
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
|
||||
|
||||
msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
|
||||
if (id < 0)
|
||||
pr_err("trout_init_panel: set clock rate failed\n");
|
||||
}
|
||||
|
||||
rc = platform_device_register(&msm_device_mdp);
|
||||
if (rc)
|
||||
return rc;
|
||||
msm_device_mddi0.dev.platform_data = &mddi_pdata;
|
||||
return platform_device_register(&msm_device_mddi0);
|
||||
}
|
||||
|
||||
device_initcall(trout_init_panel);
|
@ -1,111 +0,0 @@
|
||||
/* linux/arch/arm/mach-msm/board-trout.c
|
||||
*
|
||||
* Copyright (C) 2009 Google, Inc.
|
||||
* Author: Brian Swetland <swetland@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
#include <asm/system_info.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "board-trout.h"
|
||||
#include "common.h"
|
||||
|
||||
extern int trout_init_mmc(unsigned int);
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&msm_clock_7x01a,
|
||||
&msm_device_gpio_7201,
|
||||
&msm_device_uart3,
|
||||
&msm_device_smd,
|
||||
&msm_device_nand,
|
||||
&msm_device_hsusb,
|
||||
&msm_device_i2c,
|
||||
};
|
||||
|
||||
static void __init trout_init_early(void)
|
||||
{
|
||||
arch_ioremap_caller = __msm_ioremap_caller;
|
||||
}
|
||||
|
||||
static void __init trout_init_irq(void)
|
||||
{
|
||||
msm_init_irq();
|
||||
}
|
||||
|
||||
static void __init trout_fixup(struct tag *tags, char **cmdline)
|
||||
{
|
||||
memblock_add(PHYS_OFFSET, 101*SZ_1M);
|
||||
}
|
||||
|
||||
static void __init trout_init(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
|
||||
if (IS_ENABLED(CONFIG_MMC)) {
|
||||
rc = trout_init_mmc(system_rev);
|
||||
if (rc)
|
||||
pr_crit("MMC init failure (%d)\n", rc);
|
||||
}
|
||||
}
|
||||
|
||||
static struct map_desc trout_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)TROUT_CPLD_BASE,
|
||||
.pfn = __phys_to_pfn(TROUT_CPLD_START),
|
||||
.length = TROUT_CPLD_SIZE,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
}
|
||||
};
|
||||
|
||||
static void __init trout_map_io(void)
|
||||
{
|
||||
msm_map_common_io();
|
||||
iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));
|
||||
|
||||
#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9c00000)
|
||||
/* route UART3 to the "H2W" extended usb connector */
|
||||
writeb(0x80, TROUT_CPLD_BASE + 0x00);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init trout_init_late(void)
|
||||
{
|
||||
smd_debugfs_init();
|
||||
}
|
||||
|
||||
MACHINE_START(TROUT, "HTC Dream")
|
||||
.atag_offset = 0x100,
|
||||
.fixup = trout_fixup,
|
||||
.map_io = trout_map_io,
|
||||
.init_early = trout_init_early,
|
||||
.init_irq = trout_init_irq,
|
||||
.init_machine = trout_init,
|
||||
.init_late = trout_init_late,
|
||||
.init_time = msm7x01_timer_init,
|
||||
MACHINE_END
|
@ -1,162 +0,0 @@
|
||||
/* linux/arch/arm/mach-msm/board-trout.h
|
||||
** Author: Brian Swetland <swetland@google.com>
|
||||
*/
|
||||
#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
|
||||
#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define MSM_SMI_BASE 0x00000000
|
||||
#define MSM_SMI_SIZE 0x00800000
|
||||
|
||||
#define MSM_EBI_BASE 0x10000000
|
||||
#define MSM_EBI_SIZE 0x06e00000
|
||||
|
||||
#define MSM_PMEM_GPU0_BASE 0x00000000
|
||||
#define MSM_PMEM_GPU0_SIZE 0x00700000
|
||||
|
||||
#define MSM_PMEM_MDP_BASE 0x02000000
|
||||
#define MSM_PMEM_MDP_SIZE 0x00800000
|
||||
|
||||
#define MSM_PMEM_ADSP_BASE 0x02800000
|
||||
#define MSM_PMEM_ADSP_SIZE 0x00800000
|
||||
|
||||
#define MSM_PMEM_CAMERA_BASE 0x03000000
|
||||
#define MSM_PMEM_CAMERA_SIZE 0x00800000
|
||||
|
||||
#define MSM_FB_BASE 0x03800000
|
||||
#define MSM_FB_SIZE 0x00100000
|
||||
|
||||
#define MSM_LINUX_BASE MSM_EBI_BASE
|
||||
#define MSM_LINUX_SIZE 0x06500000
|
||||
|
||||
#define MSM_PMEM_GPU1_SIZE 0x800000
|
||||
#define MSM_PMEM_GPU1_BASE (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
|
||||
|
||||
#define MSM_RAM_CONSOLE_BASE (MSM_EBI_BASE + 0x6d00000)
|
||||
#define MSM_RAM_CONSOLE_SIZE (128 * SZ_1K)
|
||||
|
||||
#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
|
||||
#error invalid memory map
|
||||
#endif
|
||||
|
||||
#define DECLARE_MSM_IOMAP
|
||||
#include <mach/msm_iomap.h>
|
||||
|
||||
#define TROUT_4_BALL_UP_0 1
|
||||
#define TROUT_4_BALL_LEFT_0 18
|
||||
#define TROUT_4_BALL_DOWN_0 57
|
||||
#define TROUT_4_BALL_RIGHT_0 91
|
||||
|
||||
#define TROUT_5_BALL_UP_0 94
|
||||
#define TROUT_5_BALL_LEFT_0 18
|
||||
#define TROUT_5_BALL_DOWN_0 90
|
||||
#define TROUT_5_BALL_RIGHT_0 19
|
||||
|
||||
#define TROUT_POWER_KEY 20
|
||||
|
||||
#define TROUT_4_TP_LS_EN 19
|
||||
#define TROUT_5_TP_LS_EN 1
|
||||
|
||||
#define TROUT_CPLD_BASE IOMEM(0xE8100000)
|
||||
#define TROUT_CPLD_START 0x98000000
|
||||
#define TROUT_CPLD_SIZE SZ_4K
|
||||
|
||||
#define TROUT_GPIO_CABLE_IN1 (83)
|
||||
#define TROUT_GPIO_CABLE_IN2 (49)
|
||||
|
||||
#define TROUT_GPIO_START (128)
|
||||
|
||||
#define TROUT_GPIO_INT_MASK0_REG (0x0c)
|
||||
#define TROUT_GPIO_INT_STAT0_REG (0x0e)
|
||||
#define TROUT_GPIO_INT_MASK1_REG (0x14)
|
||||
#define TROUT_GPIO_INT_STAT1_REG (0x10)
|
||||
|
||||
#define TROUT_GPIO_HAPTIC_PWM (28)
|
||||
#define TROUT_GPIO_PS_HOLD (25)
|
||||
|
||||
#define TROUT_GPIO_MISC2_BASE (TROUT_GPIO_START + 0x00)
|
||||
#define TROUT_GPIO_MISC3_BASE (TROUT_GPIO_START + 0x08)
|
||||
#define TROUT_GPIO_MISC4_BASE (TROUT_GPIO_START + 0x10)
|
||||
#define TROUT_GPIO_MISC5_BASE (TROUT_GPIO_START + 0x18)
|
||||
#define TROUT_GPIO_INT2_BASE (TROUT_GPIO_START + 0x20)
|
||||
#define TROUT_GPIO_MISC1_BASE (TROUT_GPIO_START + 0x28)
|
||||
#define TROUT_GPIO_VIRTUAL_BASE (TROUT_GPIO_START + 0x30)
|
||||
#define TROUT_GPIO_INT5_BASE (TROUT_GPIO_START + 0x48)
|
||||
|
||||
#define TROUT_GPIO_CHARGER_EN (TROUT_GPIO_MISC2_BASE + 0)
|
||||
#define TROUT_GPIO_ISET (TROUT_GPIO_MISC2_BASE + 1)
|
||||
#define TROUT_GPIO_H2W_DAT_DIR (TROUT_GPIO_MISC2_BASE + 2)
|
||||
#define TROUT_GPIO_H2W_CLK_DIR (TROUT_GPIO_MISC2_BASE + 3)
|
||||
#define TROUT_GPIO_H2W_DAT_GPO (TROUT_GPIO_MISC2_BASE + 4)
|
||||
#define TROUT_GPIO_H2W_CLK_GPO (TROUT_GPIO_MISC2_BASE + 5)
|
||||
#define TROUT_GPIO_H2W_SEL0 (TROUT_GPIO_MISC2_BASE + 6)
|
||||
#define TROUT_GPIO_H2W_SEL1 (TROUT_GPIO_MISC2_BASE + 7)
|
||||
|
||||
#define TROUT_GPIO_SPOTLIGHT_EN (TROUT_GPIO_MISC3_BASE + 0)
|
||||
#define TROUT_GPIO_FLASH_EN (TROUT_GPIO_MISC3_BASE + 1)
|
||||
#define TROUT_GPIO_I2C_PULL (TROUT_GPIO_MISC3_BASE + 2)
|
||||
#define TROUT_GPIO_TP_I2C_PULL (TROUT_GPIO_MISC3_BASE + 3)
|
||||
#define TROUT_GPIO_TP_EN (TROUT_GPIO_MISC3_BASE + 4)
|
||||
#define TROUT_GPIO_JOG_EN (TROUT_GPIO_MISC3_BASE + 5)
|
||||
#define TROUT_GPIO_UI_LED_EN (TROUT_GPIO_MISC3_BASE + 6)
|
||||
#define TROUT_GPIO_QTKEY_LED_EN (TROUT_GPIO_MISC3_BASE + 7)
|
||||
|
||||
#define TROUT_GPIO_VCM_PWDN (TROUT_GPIO_MISC4_BASE + 0)
|
||||
#define TROUT_GPIO_USB_H2W_SW (TROUT_GPIO_MISC4_BASE + 1)
|
||||
#define TROUT_GPIO_COMPASS_RST_N (TROUT_GPIO_MISC4_BASE + 2)
|
||||
#define TROUT_GPIO_HAPTIC_EN_UP (TROUT_GPIO_MISC4_BASE + 3)
|
||||
#define TROUT_GPIO_HAPTIC_EN_MAIN (TROUT_GPIO_MISC4_BASE + 4)
|
||||
#define TROUT_GPIO_USB_PHY_RST_N (TROUT_GPIO_MISC4_BASE + 5)
|
||||
#define TROUT_GPIO_WIFI_PA_RESETX (TROUT_GPIO_MISC4_BASE + 6)
|
||||
#define TROUT_GPIO_WIFI_EN (TROUT_GPIO_MISC4_BASE + 7)
|
||||
|
||||
#define TROUT_GPIO_BT_32K_EN (TROUT_GPIO_MISC5_BASE + 0)
|
||||
#define TROUT_GPIO_MAC_32K_EN (TROUT_GPIO_MISC5_BASE + 1)
|
||||
#define TROUT_GPIO_MDDI_32K_EN (TROUT_GPIO_MISC5_BASE + 2)
|
||||
#define TROUT_GPIO_COMPASS_32K_EN (TROUT_GPIO_MISC5_BASE + 3)
|
||||
|
||||
#define TROUT_GPIO_NAVI_ACT_N (TROUT_GPIO_INT2_BASE + 0)
|
||||
#define TROUT_GPIO_COMPASS_IRQ (TROUT_GPIO_INT2_BASE + 1)
|
||||
#define TROUT_GPIO_SLIDING_DET (TROUT_GPIO_INT2_BASE + 2)
|
||||
#define TROUT_GPIO_AUD_HSMIC_DET_N (TROUT_GPIO_INT2_BASE + 3)
|
||||
#define TROUT_GPIO_SD_DOOR_N (TROUT_GPIO_INT2_BASE + 4)
|
||||
#define TROUT_GPIO_CAM_BTN_STEP1_N (TROUT_GPIO_INT2_BASE + 5)
|
||||
#define TROUT_GPIO_CAM_BTN_STEP2_N (TROUT_GPIO_INT2_BASE + 6)
|
||||
#define TROUT_GPIO_TP_ATT_N (TROUT_GPIO_INT2_BASE + 7)
|
||||
#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE (TROUT_GPIO_NAVI_ACT_N)
|
||||
#define TROUT_GPIO_BANK0_LAST_INT_SOURCE (TROUT_GPIO_TP_ATT_N)
|
||||
|
||||
#define TROUT_GPIO_H2W_DAT_GPI (TROUT_GPIO_MISC1_BASE + 0)
|
||||
#define TROUT_GPIO_H2W_CLK_GPI (TROUT_GPIO_MISC1_BASE + 1)
|
||||
#define TROUT_GPIO_CPLD128_VER_0 (TROUT_GPIO_MISC1_BASE + 4)
|
||||
#define TROUT_GPIO_CPLD128_VER_1 (TROUT_GPIO_MISC1_BASE + 5)
|
||||
#define TROUT_GPIO_CPLD128_VER_2 (TROUT_GPIO_MISC1_BASE + 6)
|
||||
#define TROUT_GPIO_CPLD128_VER_3 (TROUT_GPIO_MISC1_BASE + 7)
|
||||
|
||||
#define TROUT_GPIO_SDMC_CD_N (TROUT_GPIO_VIRTUAL_BASE + 0)
|
||||
#define TROUT_GPIO_END (TROUT_GPIO_SDMC_CD_N)
|
||||
#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
|
||||
#define TROUT_GPIO_BANK1_LAST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
|
||||
|
||||
#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
|
||||
(TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
|
||||
|
||||
#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
|
||||
#define TROUT_INT_BANK0_COUNT (8)
|
||||
#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
|
||||
#define TROUT_INT_BANK1_COUNT (1)
|
||||
#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
|
||||
TROUT_INT_BANK1_COUNT - 1)
|
||||
#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
|
||||
(TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
|
||||
(TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
|
||||
|
||||
#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
|
||||
#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
|
||||
#define TROUT_BANK_TO_MASK_REG(bank) \
|
||||
(bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
|
||||
#define TROUT_BANK_TO_STAT_REG(bank) \
|
||||
(bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
|
||||
|
||||
#endif /* GUARD */
|
@ -1,176 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
#include <mach/clk.h>
|
||||
|
||||
#include "proc_comm.h"
|
||||
#include "clock.h"
|
||||
#include "clock-pcom.h"
|
||||
|
||||
struct clk_pcom {
|
||||
unsigned id;
|
||||
unsigned long flags;
|
||||
struct msm_clk msm_clk;
|
||||
};
|
||||
|
||||
static inline struct clk_pcom *to_clk_pcom(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(to_msm_clk(hw), struct clk_pcom, msm_clk);
|
||||
}
|
||||
|
||||
static int pc_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
unsigned id = to_clk_pcom(hw)->id;
|
||||
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
else
|
||||
return (int)id < 0 ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static void pc_clk_disable(struct clk_hw *hw)
|
||||
{
|
||||
unsigned id = to_clk_pcom(hw)->id;
|
||||
msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
|
||||
}
|
||||
|
||||
static int pc_clk_reset(struct clk_hw *hw, enum clk_reset_action action)
|
||||
{
|
||||
int rc;
|
||||
unsigned id = to_clk_pcom(hw)->id;
|
||||
|
||||
if (action == CLK_RESET_ASSERT)
|
||||
rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
|
||||
else
|
||||
rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_DEASSERT, &id, NULL);
|
||||
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
else
|
||||
return (int)id < 0 ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static int pc_clk_set_rate(struct clk_hw *hw, unsigned long new_rate,
|
||||
unsigned long p_rate)
|
||||
{
|
||||
struct clk_pcom *p = to_clk_pcom(hw);
|
||||
unsigned id = p->id, rate = new_rate;
|
||||
int rc;
|
||||
|
||||
/*
|
||||
* The rate _might_ be rounded off to the nearest KHz value by the
|
||||
* remote function. So a return value of 0 doesn't necessarily mean
|
||||
* that the exact rate was set successfully.
|
||||
*/
|
||||
if (p->flags & CLKFLAG_MIN)
|
||||
rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
|
||||
else
|
||||
rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
else
|
||||
return (int)id < 0 ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static unsigned long pc_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
|
||||
{
|
||||
unsigned id = to_clk_pcom(hw)->id;
|
||||
if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
|
||||
return 0;
|
||||
else
|
||||
return id;
|
||||
}
|
||||
|
||||
static int pc_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
unsigned id = to_clk_pcom(hw)->id;
|
||||
if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
|
||||
return 0;
|
||||
else
|
||||
return id;
|
||||
}
|
||||
|
||||
static long pc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *p_rate)
|
||||
{
|
||||
/* Not really supported; pc_clk_set_rate() does rounding on it's own. */
|
||||
return rate;
|
||||
}
|
||||
|
||||
static struct clk_ops clk_ops_pcom = {
|
||||
.enable = pc_clk_enable,
|
||||
.disable = pc_clk_disable,
|
||||
.set_rate = pc_clk_set_rate,
|
||||
.recalc_rate = pc_clk_recalc_rate,
|
||||
.is_enabled = pc_clk_is_enabled,
|
||||
.round_rate = pc_clk_round_rate,
|
||||
};
|
||||
|
||||
static int msm_clock_pcom_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct pcom_clk_pdata *pdata = pdev->dev.platform_data;
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < pdata->num_lookups; i++) {
|
||||
const struct clk_pcom_desc *desc = &pdata->lookup[i];
|
||||
struct clk *c;
|
||||
struct clk_pcom *p;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
|
||||
p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
|
||||
if (!p)
|
||||
return -ENOMEM;
|
||||
|
||||
p->id = desc->id;
|
||||
p->flags = desc->flags;
|
||||
p->msm_clk.reset = pc_clk_reset;
|
||||
|
||||
hw = &p->msm_clk.hw;
|
||||
hw->init = &init;
|
||||
|
||||
init.name = desc->name;
|
||||
init.ops = &clk_ops_pcom;
|
||||
init.num_parents = 0;
|
||||
init.flags = CLK_IS_ROOT;
|
||||
|
||||
if (!(p->flags & CLKFLAG_AUTO_OFF))
|
||||
init.flags |= CLK_IGNORE_UNUSED;
|
||||
|
||||
c = devm_clk_register(&pdev->dev, hw);
|
||||
ret = clk_register_clkdev(c, desc->con, desc->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver msm_clock_pcom_driver = {
|
||||
.probe = msm_clock_pcom_probe,
|
||||
.driver = {
|
||||
.name = "msm-clock-pcom",
|
||||
},
|
||||
};
|
||||
module_platform_driver(msm_clock_pcom_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
@ -1,145 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
|
||||
#define __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
|
||||
|
||||
/* clock IDs used by the modem processor */
|
||||
|
||||
#define P_ACPU_CLK 0 /* Applications processor clock */
|
||||
#define P_ADM_CLK 1 /* Applications data mover clock */
|
||||
#define P_ADSP_CLK 2 /* ADSP clock */
|
||||
#define P_EBI1_CLK 3 /* External bus interface 1 clock */
|
||||
#define P_EBI2_CLK 4 /* External bus interface 2 clock */
|
||||
#define P_ECODEC_CLK 5 /* External CODEC clock */
|
||||
#define P_EMDH_CLK 6 /* External MDDI host clock */
|
||||
#define P_GP_CLK 7 /* General purpose clock */
|
||||
#define P_GRP_3D_CLK 8 /* Graphics clock */
|
||||
#define P_I2C_CLK 9 /* I2C clock */
|
||||
#define P_ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
|
||||
#define P_ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
|
||||
#define P_IMEM_CLK 12 /* Internal graphics memory clock */
|
||||
#define P_MDC_CLK 13 /* MDDI client clock */
|
||||
#define P_MDP_CLK 14 /* Mobile display processor clock */
|
||||
#define P_PBUS_CLK 15 /* Peripheral bus clock */
|
||||
#define P_PCM_CLK 16 /* PCM clock */
|
||||
#define P_PMDH_CLK 17 /* Primary MDDI host clock */
|
||||
#define P_SDAC_CLK 18 /* Stereo DAC clock */
|
||||
#define P_SDC1_CLK 19 /* Secure Digital Card clocks */
|
||||
#define P_SDC1_P_CLK 20
|
||||
#define P_SDC2_CLK 21
|
||||
#define P_SDC2_P_CLK 22
|
||||
#define P_SDC3_CLK 23
|
||||
#define P_SDC3_P_CLK 24
|
||||
#define P_SDC4_CLK 25
|
||||
#define P_SDC4_P_CLK 26
|
||||
#define P_TSIF_CLK 27 /* Transport Stream Interface clocks */
|
||||
#define P_TSIF_REF_CLK 28
|
||||
#define P_TV_DAC_CLK 29 /* TV clocks */
|
||||
#define P_TV_ENC_CLK 30
|
||||
#define P_UART1_CLK 31 /* UART clocks */
|
||||
#define P_UART2_CLK 32
|
||||
#define P_UART3_CLK 33
|
||||
#define P_UART1DM_CLK 34
|
||||
#define P_UART2DM_CLK 35
|
||||
#define P_USB_HS_CLK 36 /* High speed USB core clock */
|
||||
#define P_USB_HS_P_CLK 37 /* High speed USB pbus clock */
|
||||
#define P_USB_OTG_CLK 38 /* Full speed USB clock */
|
||||
#define P_VDC_CLK 39 /* Video controller clock */
|
||||
#define P_VFE_MDC_CLK 40 /* Camera / Video Front End clock */
|
||||
#define P_VFE_CLK 41 /* VFE MDDI client clock */
|
||||
#define P_MDP_LCDC_PCLK_CLK 42
|
||||
#define P_MDP_LCDC_PAD_PCLK_CLK 43
|
||||
#define P_MDP_VSYNC_CLK 44
|
||||
#define P_SPI_CLK 45
|
||||
#define P_VFE_AXI_CLK 46
|
||||
#define P_USB_HS2_CLK 47 /* High speed USB 2 core clock */
|
||||
#define P_USB_HS2_P_CLK 48 /* High speed USB 2 pbus clock */
|
||||
#define P_USB_HS3_CLK 49 /* High speed USB 3 core clock */
|
||||
#define P_USB_HS3_P_CLK 50 /* High speed USB 3 pbus clock */
|
||||
#define P_GRP_3D_P_CLK 51 /* Graphics pbus clock */
|
||||
#define P_USB_PHY_CLK 52 /* USB PHY clock */
|
||||
#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
|
||||
#define P_USB_HS2_CORE_CLK 54 /* High speed USB 2 core clock */
|
||||
#define P_USB_HS3_CORE_CLK 55 /* High speed USB 3 core clock */
|
||||
#define P_CAM_M_CLK 56
|
||||
#define P_CAMIF_PAD_P_CLK 57
|
||||
#define P_GRP_2D_CLK 58
|
||||
#define P_GRP_2D_P_CLK 59
|
||||
#define P_I2S_CLK 60
|
||||
#define P_JPEG_CLK 61
|
||||
#define P_JPEG_P_CLK 62
|
||||
#define P_LPA_CODEC_CLK 63
|
||||
#define P_LPA_CORE_CLK 64
|
||||
#define P_LPA_P_CLK 65
|
||||
#define P_MDC_IO_CLK 66
|
||||
#define P_MDC_P_CLK 67
|
||||
#define P_MFC_CLK 68
|
||||
#define P_MFC_DIV2_CLK 69
|
||||
#define P_MFC_P_CLK 70
|
||||
#define P_QUP_I2C_CLK 71
|
||||
#define P_ROTATOR_IMEM_CLK 72
|
||||
#define P_ROTATOR_P_CLK 73
|
||||
#define P_VFE_CAMIF_CLK 74
|
||||
#define P_VFE_P_CLK 75
|
||||
#define P_VPE_CLK 76
|
||||
#define P_I2C_2_CLK 77
|
||||
#define P_MI2S_CODEC_RX_S_CLK 78
|
||||
#define P_MI2S_CODEC_RX_M_CLK 79
|
||||
#define P_MI2S_CODEC_TX_S_CLK 80
|
||||
#define P_MI2S_CODEC_TX_M_CLK 81
|
||||
#define P_PMDH_P_CLK 82
|
||||
#define P_EMDH_P_CLK 83
|
||||
#define P_SPI_P_CLK 84
|
||||
#define P_TSIF_P_CLK 85
|
||||
#define P_MDP_P_CLK 86
|
||||
#define P_SDAC_M_CLK 87
|
||||
#define P_MI2S_S_CLK 88
|
||||
#define P_MI2S_M_CLK 89
|
||||
#define P_AXI_ROTATOR_CLK 90
|
||||
#define P_HDMI_CLK 91
|
||||
#define P_CSI0_CLK 92
|
||||
#define P_CSI0_VFE_CLK 93
|
||||
#define P_CSI0_P_CLK 94
|
||||
#define P_CSI1_CLK 95
|
||||
#define P_CSI1_VFE_CLK 96
|
||||
#define P_CSI1_P_CLK 97
|
||||
#define P_GSBI_CLK 98
|
||||
#define P_GSBI_P_CLK 99
|
||||
#define P_CE_CLK 100 /* Crypto engine */
|
||||
#define P_CODEC_SSBI_CLK 101
|
||||
|
||||
#define P_NR_CLKS 102
|
||||
|
||||
struct clk_pcom_desc {
|
||||
unsigned id;
|
||||
const char *name;
|
||||
const char *con;
|
||||
const char *dev;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
struct pcom_clk_pdata {
|
||||
struct clk_pcom_desc *lookup;
|
||||
u32 num_lookups;
|
||||
};
|
||||
|
||||
#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \
|
||||
.id = P_##clk_id, \
|
||||
.name = #clk_id, \
|
||||
.con = clk_name, \
|
||||
.dev = clk_dev, \
|
||||
.flags = clk_flags, \
|
||||
}
|
||||
|
||||
#endif
|
@ -1,28 +0,0 @@
|
||||
/* arch/arm/mach-msm/clock.c
|
||||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
int clk_reset(struct clk *clk, enum clk_reset_action action)
|
||||
{
|
||||
struct clk_hw *hw = __clk_get_hw(clk);
|
||||
struct msm_clk *m = to_msm_clk(hw);
|
||||
return m->reset(hw, action);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_reset);
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user