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mtd: rawnand: denali: convert to nand_scan()
Two helpers have been added to the core to do all kind of controller side configuration/initialization between the detection phase and the final NAND scan. Implement these hooks so that we can convert the driver to just use nand_scan() instead of the nand_scan_ident() + nand_scan_tail() pair. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Miquel Raynal
parent
b2342c1c80
commit
d03af162bb
@ -1205,6 +1205,115 @@ static int denali_multidev_fixup(struct denali_nand_info *denali)
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return 0;
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}
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static int denali_attach_chip(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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int ret;
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if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
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denali->dma_avail = 1;
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if (denali->dma_avail) {
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int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32;
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ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit));
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if (ret) {
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dev_info(denali->dev,
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"Failed to set DMA mask. Disabling DMA.\n");
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denali->dma_avail = 0;
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}
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}
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if (denali->dma_avail) {
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chip->options |= NAND_USE_BOUNCE_BUFFER;
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chip->buf_align = 16;
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if (denali->caps & DENALI_CAP_DMA_64BIT)
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denali->setup_dma = denali_setup_dma64;
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else
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denali->setup_dma = denali_setup_dma32;
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}
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chip->bbt_options |= NAND_BBT_USE_FLASH;
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chip->bbt_options |= NAND_BBT_NO_OOB;
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chip->ecc.mode = NAND_ECC_HW_SYNDROME;
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chip->options |= NAND_NO_SUBPAGE_WRITE;
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ret = nand_ecc_choose_conf(chip, denali->ecc_caps,
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mtd->oobsize - denali->oob_skip_bytes);
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if (ret) {
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dev_err(denali->dev, "Failed to setup ECC settings.\n");
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return ret;
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}
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dev_dbg(denali->dev,
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"chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
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chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
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iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
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FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
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denali->reg + ECC_CORRECTION);
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iowrite32(mtd->erasesize / mtd->writesize,
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denali->reg + PAGES_PER_BLOCK);
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iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
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denali->reg + DEVICE_WIDTH);
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iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
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denali->reg + TWO_ROW_ADDR_CYCLES);
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iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
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iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
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iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
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iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
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/* chip->ecc.steps is set by nand_scan_tail(); not available here */
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iowrite32(mtd->writesize / chip->ecc.size,
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denali->reg + CFG_NUM_DATA_BLOCKS);
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mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
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if (chip->options & NAND_BUSWIDTH_16) {
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chip->read_buf = denali_read_buf16;
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chip->write_buf = denali_write_buf16;
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} else {
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chip->read_buf = denali_read_buf;
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chip->write_buf = denali_write_buf;
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}
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chip->ecc.read_page = denali_read_page;
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chip->ecc.read_page_raw = denali_read_page_raw;
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chip->ecc.write_page = denali_write_page;
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chip->ecc.write_page_raw = denali_write_page_raw;
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chip->ecc.read_oob = denali_read_oob;
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chip->ecc.write_oob = denali_write_oob;
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chip->erase = denali_erase;
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ret = denali_multidev_fixup(denali);
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if (ret)
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return ret;
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/*
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* This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
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* use devm_kmalloc() because the memory allocated by devm_ does not
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* guarantee DMA-safe alignment.
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*/
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denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
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if (!denali->buf)
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return -ENOMEM;
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return 0;
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}
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static void denali_detach_chip(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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kfree(denali->buf);
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}
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static const struct nand_controller_ops denali_controller_ops = {
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.attach_chip = denali_attach_chip,
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.detach_chip = denali_detach_chip,
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};
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int denali_init(struct denali_nand_info *denali)
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{
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struct nand_chip *chip = &denali->nand;
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@ -1257,114 +1366,21 @@ int denali_init(struct denali_nand_info *denali)
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if (denali->clk_rate && denali->clk_x_rate)
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chip->setup_data_interface = denali_setup_data_interface;
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ret = nand_scan_ident(mtd, denali->max_banks, NULL);
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chip->dummy_controller.ops = &denali_controller_ops;
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ret = nand_scan(mtd, denali->max_banks);
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if (ret)
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goto disable_irq;
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if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
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denali->dma_avail = 1;
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if (denali->dma_avail) {
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int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32;
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ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit));
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if (ret) {
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dev_info(denali->dev,
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"Failed to set DMA mask. Disabling DMA.\n");
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denali->dma_avail = 0;
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}
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}
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if (denali->dma_avail) {
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chip->options |= NAND_USE_BOUNCE_BUFFER;
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chip->buf_align = 16;
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if (denali->caps & DENALI_CAP_DMA_64BIT)
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denali->setup_dma = denali_setup_dma64;
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else
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denali->setup_dma = denali_setup_dma32;
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}
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chip->bbt_options |= NAND_BBT_USE_FLASH;
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chip->bbt_options |= NAND_BBT_NO_OOB;
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chip->ecc.mode = NAND_ECC_HW_SYNDROME;
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chip->options |= NAND_NO_SUBPAGE_WRITE;
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ret = nand_ecc_choose_conf(chip, denali->ecc_caps,
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mtd->oobsize - denali->oob_skip_bytes);
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if (ret) {
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dev_err(denali->dev, "Failed to setup ECC settings.\n");
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goto disable_irq;
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}
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dev_dbg(denali->dev,
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"chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
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chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
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iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
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FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
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denali->reg + ECC_CORRECTION);
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iowrite32(mtd->erasesize / mtd->writesize,
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denali->reg + PAGES_PER_BLOCK);
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iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
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denali->reg + DEVICE_WIDTH);
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iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
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denali->reg + TWO_ROW_ADDR_CYCLES);
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iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
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iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
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iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
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iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
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/* chip->ecc.steps is set by nand_scan_tail(); not available here */
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iowrite32(mtd->writesize / chip->ecc.size,
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denali->reg + CFG_NUM_DATA_BLOCKS);
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mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
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if (chip->options & NAND_BUSWIDTH_16) {
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chip->read_buf = denali_read_buf16;
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chip->write_buf = denali_write_buf16;
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} else {
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chip->read_buf = denali_read_buf;
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chip->write_buf = denali_write_buf;
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}
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chip->ecc.read_page = denali_read_page;
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chip->ecc.read_page_raw = denali_read_page_raw;
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chip->ecc.write_page = denali_write_page;
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chip->ecc.write_page_raw = denali_write_page_raw;
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chip->ecc.read_oob = denali_read_oob;
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chip->ecc.write_oob = denali_write_oob;
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chip->erase = denali_erase;
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ret = denali_multidev_fixup(denali);
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if (ret)
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goto disable_irq;
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/*
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* This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
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* use devm_kmalloc() because the memory allocated by devm_ does not
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* guarantee DMA-safe alignment.
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*/
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denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
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if (!denali->buf) {
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ret = -ENOMEM;
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goto disable_irq;
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}
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ret = nand_scan_tail(mtd);
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if (ret)
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goto free_buf;
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ret = mtd_device_register(mtd, NULL, 0);
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if (ret) {
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dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
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goto cleanup_nand;
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}
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return 0;
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cleanup_nand:
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nand_cleanup(chip);
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free_buf:
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kfree(denali->buf);
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disable_irq:
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denali_disable_irq(denali);
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@ -1377,7 +1393,6 @@ void denali_remove(struct denali_nand_info *denali)
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struct mtd_info *mtd = nand_to_mtd(&denali->nand);
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nand_release(mtd);
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kfree(denali->buf);
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denali_disable_irq(denali);
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}
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EXPORT_SYMBOL(denali_remove);
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