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usb: musb: Change end point selection to use new IO access
This allows the endpoints to work when multiple MUSB glue layers are built in. Cc: Fabio Baltieri <fabio.baltieri@linaro.org> Cc: Lee Jones <lee.jones@linaro.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Apelete Seketeli <apelete@seketeli.net> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -438,6 +438,7 @@ static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
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}
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static const struct musb_platform_ops am35x_ops = {
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.quirks = MUSB_INDEXED_EP,
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.init = am35x_musb_init,
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.exit = am35x_musb_exit,
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@ -458,6 +458,7 @@ static int da8xx_musb_exit(struct musb *musb)
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}
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static const struct musb_platform_ops da8xx_ops = {
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.quirks = MUSB_INDEXED_EP,
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.init = da8xx_musb_init,
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.exit = da8xx_musb_exit,
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@ -106,6 +106,7 @@ static int jz4740_musb_exit(struct musb *musb)
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}
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static const struct musb_platform_ops jz4740_musb_ops = {
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.quirks = MUSB_INDEXED_EP,
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.init = jz4740_musb_init,
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.exit = jz4740_musb_exit,
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};
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@ -229,6 +229,27 @@ static u32 musb_default_fifo_offset(u8 epnum)
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return 0x20 + (epnum * 4);
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}
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/* "flat" mapping: each endpoint has its own i/o address */
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static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
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{
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}
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static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
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{
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return 0x100 + (0x10 * epnum) + offset;
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}
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/* "indexed" mapping: INDEX register controls register bank select */
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static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
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{
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musb_writeb(mbase, MUSB_INDEX, epnum);
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}
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static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
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{
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return 0x10 + offset;
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}
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static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
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{
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return __raw_readb(addr + offset);
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@ -1537,7 +1558,7 @@ static int musb_core_init(u16 musb_type, struct musb *musb)
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}
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#endif
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hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
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hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
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hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
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hw_ep->rx_reinit = 1;
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hw_ep->tx_reinit = 1;
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@ -2007,6 +2028,21 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
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if (musb->ops->quirks)
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musb->io.quirks = musb->ops->quirks;
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/* At least tusb6010 has it's own offsets.. */
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if (musb->ops->ep_offset)
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musb->io.ep_offset = musb->ops->ep_offset;
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if (musb->ops->ep_select)
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musb->io.ep_select = musb->ops->ep_select;
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/* ..and some devices use indexed offset or flat offset */
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if (musb->io.quirks & MUSB_INDEXED_EP) {
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musb->io.ep_offset = musb_indexed_ep_offset;
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musb->io.ep_select = musb_indexed_ep_select;
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} else {
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musb->io.ep_offset = musb_flat_ep_offset;
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musb->io.ep_select = musb_flat_ep_select;
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}
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if (musb->ops->fifo_offset)
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musb->io.fifo_offset = musb->ops->fifo_offset;
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else
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@ -124,41 +124,6 @@ enum musb_g_ep0_state {
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#define OTG_TIME_A_AIDL_BDIS 200 /* min 200 msec */
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#define OTG_TIME_B_ASE0_BRST 100 /* min 3.125 ms */
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/*************************** REGISTER ACCESS ********************************/
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/* Endpoint registers (other than dynfifo setup) can be accessed either
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* directly with the "flat" model, or after setting up an index register.
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*/
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#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
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|| defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
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|| defined(CONFIG_ARCH_OMAP4)
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/* REVISIT indexed access seemed to
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* misbehave (on DaVinci) for at least peripheral IN ...
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*/
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#define MUSB_FLAT_REG
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#endif
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/* TUSB mapping: "flat" plus ep0 special cases */
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#if defined(CONFIG_USB_MUSB_TUSB6010) || \
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defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
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#define musb_ep_select(_mbase, _epnum) \
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musb_writeb((_mbase), MUSB_INDEX, (_epnum))
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#define MUSB_EP_OFFSET MUSB_TUSB_OFFSET
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/* "flat" mapping: each endpoint has its own i/o address */
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#elif defined(MUSB_FLAT_REG)
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#define musb_ep_select(_mbase, _epnum) (((void)(_mbase)), ((void)(_epnum)))
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#define MUSB_EP_OFFSET MUSB_FLAT_OFFSET
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/* "indexed" mapping: INDEX register controls register bank select */
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#else
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#define musb_ep_select(_mbase, _epnum) \
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musb_writeb((_mbase), MUSB_INDEX, (_epnum))
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#define MUSB_EP_OFFSET MUSB_INDEXED_OFFSET
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#endif
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/****************************** FUNCTIONS ********************************/
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#define MUSB_HST_MODE(_musb)\
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@ -515,7 +480,7 @@ static inline int musb_read_fifosize(struct musb *musb,
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u8 reg = 0;
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/* read from core using indexed model */
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reg = musb_readb(mbase, MUSB_EP_OFFSET(epnum, MUSB_FIFOSIZE));
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reg = musb_readb(mbase, musb->io.ep_offset(epnum, MUSB_FIFOSIZE));
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/* 0's returned when no more endpoints */
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if (!reg)
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return -ENODEV;
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@ -633,6 +633,7 @@ static int dsps_musb_reset(struct musb *musb)
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}
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static struct musb_platform_ops dsps_ops = {
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.quirks = MUSB_INDEXED_EP,
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.init = dsps_musb_init,
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.exit = dsps_musb_exit,
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@ -37,6 +37,8 @@
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#include <linux/io.h>
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#define musb_ep_select(_mbase, _epnum) musb->io.ep_select((_mbase), (_epnum))
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/**
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* struct musb_io - IO functions for MUSB
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* @quirks: platform specific flags
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@ -287,19 +287,8 @@
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#define MUSB_FIFOSIZE 0x0F
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#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
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/* Offsets to endpoint registers in indexed model (using INDEX register) */
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#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
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(0x10 + (_offset))
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/* Offsets to endpoint registers in flat models */
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#define MUSB_FLAT_OFFSET(_epnum, _offset) \
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(0x100 + (0x10*(_epnum)) + (_offset))
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#if defined(CONFIG_USB_MUSB_TUSB6010) || \
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defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
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/* TUSB6010 EP0 configuration register is special */
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#define MUSB_TUSB_OFFSET(_epnum, _offset) \
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(0x10 + _offset)
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#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
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#endif
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@ -195,6 +195,7 @@ static int dma_channel_abort(struct dma_channel *channel)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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void __iomem *mbase = musb_channel->controller->base;
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struct musb *musb = musb_channel->controller->private_data;
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u8 bchannel = musb_channel->idx;
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int offset;
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@ -202,7 +203,7 @@ static int dma_channel_abort(struct dma_channel *channel)
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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if (musb_channel->transmit) {
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offset = MUSB_EP_OFFSET(musb_channel->epnum,
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offset = musb->io.ep_offset(musb_channel->epnum,
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MUSB_TXCSR);
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/*
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@ -215,7 +216,7 @@ static int dma_channel_abort(struct dma_channel *channel)
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csr &= ~MUSB_TXCSR_DMAMODE;
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musb_writew(mbase, offset, csr);
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} else {
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offset = MUSB_EP_OFFSET(musb_channel->epnum,
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offset = musb->io.ep_offset(musb_channel->epnum,
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MUSB_RXCSR);
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csr = musb_readw(mbase, offset);
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@ -326,7 +327,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
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(musb_channel->max_packet_sz - 1)))
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) {
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u8 epnum = musb_channel->epnum;
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int offset = MUSB_EP_OFFSET(epnum,
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int offset = musb->io.ep_offset(epnum,
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MUSB_TXCSR);
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u16 txcsr;
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@ -131,6 +131,17 @@ static u32 tusb_fifo_offset(u8 epnum)
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return 0x200 + (epnum * 0x20);
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}
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static u32 tusb_ep_offset(u8 epnum, u16 offset)
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{
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return 0x10 + offset;
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}
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/* TUSB mapping: "flat" plus ep0 special cases */
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static void tusb_ep_select(void __iomem *mbase, u8 epnum)
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{
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musb_writeb(mbase, MUSB_INDEX, epnum);
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}
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/*
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* TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
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*/
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@ -1174,6 +1185,8 @@ static const struct musb_platform_ops tusb_ops = {
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.init = tusb_musb_init,
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.exit = tusb_musb_exit,
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.ep_offset = tusb_ep_offset,
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.ep_select = tusb_ep_select,
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.fifo_offset = tusb_fifo_offset,
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.readb = tusb_readb,
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.writeb = tusb_writeb,
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@ -188,6 +188,7 @@ static int ux500_musb_exit(struct musb *musb)
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}
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static const struct musb_platform_ops ux500_ops = {
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.quirks = MUSB_INDEXED_EP,
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.init = ux500_musb_init,
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.exit = ux500_musb_exit,
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