mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-27 08:05:27 +08:00
Merge branches 'clk-sifive' and 'clk-visconti' into clk-next
* clk-sifive: clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being * clk-visconti: clk: visconti: prevent array overflow in visconti_clk_register_gates()
This commit is contained in:
Stephen Boyd
commit
cf683abd39
@ -80,7 +80,7 @@ examples:
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interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>,
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<17>, <18>, <19>, <20>, <21>, <22>;
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reg = <0x10060000 0x1000>;
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clocks = <&tlclk PRCI_CLK_TLCLK>;
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clocks = <&tlclk FU540_PRCI_CLK_TLCLK>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -104,7 +104,7 @@ examples:
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<0x0 0x0 0x0 0x2 &plic0 58>,
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<0x0 0x0 0x0 0x3 &plic0 59>,
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<0x0 0x0 0x0 0x4 &plic0 60>;
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clocks = <&prci PRCI_CLK_PCIE_AUX>;
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clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
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resets = <&prci 4>;
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pwren-gpios = <&gpio 5 0>;
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reset-gpios = <&gpio 8 0>;
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@ -59,7 +59,7 @@ examples:
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interrupt-parent = <&plic0>;
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interrupts = <80>;
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reg = <0x10010000 0x1000>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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};
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...
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@ -164,7 +164,7 @@
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reg = <0x0 0x10010000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <4>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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status = "disabled";
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};
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dma: dma@3000000 {
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@ -180,7 +180,7 @@
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reg = <0x0 0x10011000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <5>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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status = "disabled";
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};
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i2c0: i2c@10030000 {
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@ -188,7 +188,7 @@
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reg = <0x0 0x10030000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <50>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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reg-shift = <2>;
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reg-io-width = <1>;
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#address-cells = <1>;
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@ -201,7 +201,7 @@
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<0x0 0x20000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <51>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -212,7 +212,7 @@
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<0x0 0x30000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <52>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -222,7 +222,7 @@
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reg = <0x0 0x10050000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <6>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -235,8 +235,8 @@
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<0x0 0x100a0000 0x0 0x1000>;
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local-mac-address = [00 00 00 00 00 00];
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clock-names = "pclk", "hclk";
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clocks = <&prci PRCI_CLK_GEMGXLPLL>,
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<&prci PRCI_CLK_GEMGXLPLL>;
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clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>,
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<&prci FU540_PRCI_CLK_GEMGXLPLL>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -246,7 +246,7 @@
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reg = <0x0 0x10020000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <42>, <43>, <44>, <45>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -255,7 +255,7 @@
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reg = <0x0 0x10021000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <46>, <47>, <48>, <49>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -281,7 +281,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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status = "disabled";
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};
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};
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@ -166,7 +166,7 @@
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reg = <0x0 0x10010000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <39>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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status = "disabled";
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};
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uart1: serial@10011000 {
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@ -174,7 +174,7 @@
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reg = <0x0 0x10011000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <40>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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status = "disabled";
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};
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i2c0: i2c@10030000 {
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@ -182,7 +182,7 @@
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reg = <0x0 0x10030000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <52>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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reg-shift = <2>;
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reg-io-width = <1>;
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#address-cells = <1>;
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@ -194,7 +194,7 @@
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reg = <0x0 0x10031000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <53>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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reg-shift = <2>;
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reg-io-width = <1>;
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#address-cells = <1>;
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@ -207,7 +207,7 @@
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<0x0 0x20000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <41>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -218,7 +218,7 @@
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<0x0 0x30000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <42>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -228,7 +228,7 @@
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reg = <0x0 0x10050000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <43>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -241,8 +241,8 @@
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<0x0 0x100a0000 0x0 0x1000>;
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local-mac-address = [00 00 00 00 00 00];
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clock-names = "pclk", "hclk";
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clocks = <&prci PRCI_CLK_GEMGXLPLL>,
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<&prci PRCI_CLK_GEMGXLPLL>;
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clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
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<&prci FU740_PRCI_CLK_GEMGXLPLL>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -252,7 +252,7 @@
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reg = <0x0 0x10020000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <44>, <45>, <46>, <47>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -261,7 +261,7 @@
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reg = <0x0 0x10021000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <48>, <49>, <50>, <51>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -287,7 +287,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&prci PRCI_CLK_PCLK>;
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clocks = <&prci FU740_PRCI_CLK_PCLK>;
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status = "disabled";
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};
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pcie@e00000000 {
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@ -316,7 +316,7 @@
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<0x0 0x0 0x0 0x3 &plic0 59>,
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<0x0 0x0 0x0 0x4 &plic0 60>;
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clock-names = "pcie_aux";
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clocks = <&prci PRCI_CLK_PCIE_AUX>;
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clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
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pwren-gpios = <&gpio 5 0>;
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reset-gpios = <&gpio 8 0>;
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resets = <&prci 4>;
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@ -1,2 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o fu740-prci.o
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obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o
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@ -1,89 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2019 SiFive, Inc.
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* Copyright (C) 2018-2019 Wesley Terpstra
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* Copyright (C) 2018-2019 Paul Walmsley
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* Copyright (C) 2020 Zong Li
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*
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* The FU540 PRCI implements clock and reset control for the SiFive
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* FU540-C000 chip. This driver assumes that it has sole control
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* over all PRCI resources.
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*
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* This driver is based on the PRCI driver written by Wesley Terpstra:
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* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
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*
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* References:
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* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
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*/
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#include <linux/module.h>
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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#include "fu540-prci.h"
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#include "sifive-prci.h"
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/* PRCI integration data for each WRPLL instance */
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static struct __prci_wrpll_data __prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_corepll,
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};
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static struct __prci_wrpll_data __prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data __prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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};
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/* Linux clock framework integration */
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static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
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.set_rate = sifive_prci_wrpll_set_rate,
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.round_rate = sifive_prci_wrpll_round_rate,
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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.enable = sifive_prci_clock_enable,
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.disable = sifive_prci_clock_disable,
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.is_enabled = sifive_clk_is_enabled,
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};
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static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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};
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static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
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.recalc_rate = sifive_prci_tlclksel_recalc_rate,
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};
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/* List of clock controls provided by the PRCI */
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struct __prci_clock __prci_init_clocks_fu540[] = {
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[PRCI_CLK_COREPLL] = {
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.name = "corepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &__prci_corepll_data,
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},
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[PRCI_CLK_DDRPLL] = {
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.name = "ddrpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
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.pwd = &__prci_ddrpll_data,
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},
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[PRCI_CLK_GEMGXLPLL] = {
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.name = "gemgxlpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &__prci_gemgxlpll_data,
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},
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[PRCI_CLK_TLCLK] = {
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.name = "tlclk",
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.parent_name = "corepll",
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.ops = &sifive_fu540_prci_tlclksel_clk_ops,
|
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},
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};
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@ -1,16 +1,99 @@
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/* SPDX-License-Identifier: GPL-2.0 */
|
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/*
|
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* Copyright (C) 2020 SiFive, Inc.
|
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* Zong Li
|
||||
* Copyright (C) 2018-2021 SiFive, Inc.
|
||||
* Copyright (C) 2018-2019 Wesley Terpstra
|
||||
* Copyright (C) 2018-2019 Paul Walmsley
|
||||
* Copyright (C) 2020-2021 Zong Li
|
||||
*
|
||||
* The FU540 PRCI implements clock and reset control for the SiFive
|
||||
* FU540-C000 chip. This driver assumes that it has sole control
|
||||
* over all PRCI resources.
|
||||
*
|
||||
* This driver is based on the PRCI driver written by Wesley Terpstra:
|
||||
* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
|
||||
*
|
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* References:
|
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* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
|
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*/
|
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|
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#ifndef __SIFIVE_CLK_FU540_PRCI_H
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#define __SIFIVE_CLK_FU540_PRCI_H
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#include <linux/module.h>
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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|
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#include "sifive-prci.h"
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|
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#define NUM_CLOCK_FU540 4
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/* PRCI integration data for each WRPLL instance */
|
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|
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extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
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static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
|
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_corepll,
|
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};
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|
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static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = {
|
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
|
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
|
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};
|
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|
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static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
|
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
|
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};
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|
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/* Linux clock framework integration */
|
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|
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static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
|
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.set_rate = sifive_prci_wrpll_set_rate,
|
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.round_rate = sifive_prci_wrpll_round_rate,
|
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
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.enable = sifive_prci_clock_enable,
|
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.disable = sifive_prci_clock_disable,
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.is_enabled = sifive_clk_is_enabled,
|
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};
|
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static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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};
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static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
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.recalc_rate = sifive_prci_tlclksel_recalc_rate,
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};
|
||||
|
||||
/* List of clock controls provided by the PRCI */
|
||||
static struct __prci_clock __prci_init_clocks_fu540[] = {
|
||||
[FU540_PRCI_CLK_COREPLL] = {
|
||||
.name = "corepll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu540_prci_corepll_data,
|
||||
},
|
||||
[FU540_PRCI_CLK_DDRPLL] = {
|
||||
.name = "ddrpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
|
||||
.pwd = &sifive_fu540_prci_ddrpll_data,
|
||||
},
|
||||
[FU540_PRCI_CLK_GEMGXLPLL] = {
|
||||
.name = "gemgxlpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu540_prci_gemgxlpll_data,
|
||||
},
|
||||
[FU540_PRCI_CLK_TLCLK] = {
|
||||
.name = "tlclk",
|
||||
.parent_name = "corepll",
|
||||
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct prci_clk_desc prci_clk_fu540 = {
|
||||
.clks = __prci_init_clocks_fu540,
|
||||
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
|
||||
};
|
||||
|
||||
#endif /* __SIFIVE_CLK_FU540_PRCI_H */
|
||||
|
||||
@ -1,134 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020 SiFive, Inc.
|
||||
* Copyright (C) 2020 Zong Li
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <dt-bindings/clock/sifive-fu740-prci.h>
|
||||
|
||||
#include "fu540-prci.h"
|
||||
#include "sifive-prci.h"
|
||||
|
||||
/* PRCI integration data for each WRPLL instance */
|
||||
|
||||
static struct __prci_wrpll_data __prci_corepll_data = {
|
||||
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
|
||||
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
|
||||
.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data __prci_ddrpll_data = {
|
||||
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
|
||||
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data __prci_dvfscorepll_data = {
|
||||
.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
|
||||
.enable_bypass = sifive_prci_corepllsel_use_corepll,
|
||||
.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data __prci_hfpclkpll_data = {
|
||||
.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
|
||||
.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
|
||||
.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data __prci_cltxpll_data = {
|
||||
.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
|
||||
};
|
||||
|
||||
/* Linux clock framework integration */
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
|
||||
.set_rate = sifive_prci_wrpll_set_rate,
|
||||
.round_rate = sifive_prci_wrpll_round_rate,
|
||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||
.enable = sifive_prci_clock_enable,
|
||||
.disable = sifive_prci_clock_disable,
|
||||
.is_enabled = sifive_clk_is_enabled,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
|
||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
|
||||
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
|
||||
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
|
||||
.enable = sifive_prci_pcie_aux_clock_enable,
|
||||
.disable = sifive_prci_pcie_aux_clock_disable,
|
||||
.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
|
||||
};
|
||||
|
||||
/* List of clock controls provided by the PRCI */
|
||||
struct __prci_clock __prci_init_clocks_fu740[] = {
|
||||
[PRCI_CLK_COREPLL] = {
|
||||
.name = "corepll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &__prci_corepll_data,
|
||||
},
|
||||
[PRCI_CLK_DDRPLL] = {
|
||||
.name = "ddrpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
|
||||
.pwd = &__prci_ddrpll_data,
|
||||
},
|
||||
[PRCI_CLK_GEMGXLPLL] = {
|
||||
.name = "gemgxlpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &__prci_gemgxlpll_data,
|
||||
},
|
||||
[PRCI_CLK_DVFSCOREPLL] = {
|
||||
.name = "dvfscorepll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &__prci_dvfscorepll_data,
|
||||
},
|
||||
[PRCI_CLK_HFPCLKPLL] = {
|
||||
.name = "hfpclkpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &__prci_hfpclkpll_data,
|
||||
},
|
||||
[PRCI_CLK_CLTXPLL] = {
|
||||
.name = "cltxpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &__prci_cltxpll_data,
|
||||
},
|
||||
[PRCI_CLK_TLCLK] = {
|
||||
.name = "tlclk",
|
||||
.parent_name = "corepll",
|
||||
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
|
||||
},
|
||||
[PRCI_CLK_PCLK] = {
|
||||
.name = "pclk",
|
||||
.parent_name = "hfpclkpll",
|
||||
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
|
||||
},
|
||||
[PRCI_CLK_PCIE_AUX] = {
|
||||
.name = "pcie_aux",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
|
||||
},
|
||||
};
|
||||
@ -1,17 +1,139 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020 SiFive, Inc.
|
||||
* Zong Li
|
||||
* Copyright (C) 2020-2021 SiFive, Inc.
|
||||
* Copyright (C) 2020-2021 Zong Li
|
||||
*/
|
||||
|
||||
#ifndef __SIFIVE_CLK_FU740_PRCI_H
|
||||
#define __SIFIVE_CLK_FU740_PRCI_H
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <dt-bindings/clock/sifive-fu740-prci.h>
|
||||
|
||||
#include "sifive-prci.h"
|
||||
|
||||
#define NUM_CLOCK_FU740 9
|
||||
/* PRCI integration data for each WRPLL instance */
|
||||
|
||||
extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
|
||||
static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = {
|
||||
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
|
||||
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
|
||||
.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = {
|
||||
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = {
|
||||
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = {
|
||||
.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
|
||||
.enable_bypass = sifive_prci_corepllsel_use_corepll,
|
||||
.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = {
|
||||
.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
|
||||
.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
|
||||
.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = {
|
||||
.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
|
||||
};
|
||||
|
||||
/* Linux clock framework integration */
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
|
||||
.set_rate = sifive_prci_wrpll_set_rate,
|
||||
.round_rate = sifive_prci_wrpll_round_rate,
|
||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||
.enable = sifive_prci_clock_enable,
|
||||
.disable = sifive_prci_clock_disable,
|
||||
.is_enabled = sifive_clk_is_enabled,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
|
||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
|
||||
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
|
||||
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
|
||||
.enable = sifive_prci_pcie_aux_clock_enable,
|
||||
.disable = sifive_prci_pcie_aux_clock_disable,
|
||||
.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
|
||||
};
|
||||
|
||||
/* List of clock controls provided by the PRCI */
|
||||
static struct __prci_clock __prci_init_clocks_fu740[] = {
|
||||
[FU740_PRCI_CLK_COREPLL] = {
|
||||
.name = "corepll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_corepll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_DDRPLL] = {
|
||||
.name = "ddrpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_ddrpll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_GEMGXLPLL] = {
|
||||
.name = "gemgxlpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_gemgxlpll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_DVFSCOREPLL] = {
|
||||
.name = "dvfscorepll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_dvfscorepll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_HFPCLKPLL] = {
|
||||
.name = "hfpclkpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_hfpclkpll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_CLTXPLL] = {
|
||||
.name = "cltxpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_cltxpll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_TLCLK] = {
|
||||
.name = "tlclk",
|
||||
.parent_name = "corepll",
|
||||
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
|
||||
},
|
||||
[FU740_PRCI_CLK_PCLK] = {
|
||||
.name = "pclk",
|
||||
.parent_name = "hfpclkpll",
|
||||
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
|
||||
},
|
||||
[FU740_PRCI_CLK_PCIE_AUX] = {
|
||||
.name = "pcie_aux",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct prci_clk_desc prci_clk_fu740 = {
|
||||
.clks = __prci_init_clocks_fu740,
|
||||
|
||||
@ -12,11 +12,6 @@
|
||||
#include "fu540-prci.h"
|
||||
#include "fu740-prci.h"
|
||||
|
||||
static const struct prci_clk_desc prci_clk_fu540 = {
|
||||
.clks = __prci_init_clocks_fu540,
|
||||
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
|
||||
};
|
||||
|
||||
/*
|
||||
* Private functions
|
||||
*/
|
||||
|
||||
@ -176,7 +176,7 @@ static const struct visconti_clk_gate_table clk_gate_tables[] = {
|
||||
{ TMPV770X_CLK_WRCK, "wrck",
|
||||
clks_parent_data, ARRAY_SIZE(clks_parent_data),
|
||||
0, 0x68, 0x168, 9, 32,
|
||||
-1, }, /* No reset */
|
||||
NO_RESET, },
|
||||
{ TMPV770X_CLK_PICKMON, "pickmon",
|
||||
clks_parent_data, ARRAY_SIZE(clks_parent_data),
|
||||
0, 0x10, 0x110, 8, 4,
|
||||
|
||||
@ -147,7 +147,7 @@ int visconti_clk_register_gates(struct visconti_clk_provider *ctx,
|
||||
if (!dev_name)
|
||||
return -ENOMEM;
|
||||
|
||||
if (clks[i].rs_id >= 0) {
|
||||
if (clks[i].rs_id != NO_RESET) {
|
||||
rson_offset = reset[clks[i].rs_id].rson_offset;
|
||||
rsoff_offset = reset[clks[i].rs_id].rsoff_offset;
|
||||
rs_idx = reset[clks[i].rs_id].rs_idx;
|
||||
|
||||
@ -73,4 +73,7 @@ int visconti_clk_register_gates(struct visconti_clk_provider *data,
|
||||
int num_gate,
|
||||
const struct visconti_reset_data *reset,
|
||||
spinlock_t *lock);
|
||||
|
||||
#define NO_RESET 0xFF
|
||||
|
||||
#endif /* _VISCONTI_CLKC_H_ */
|
||||
|
||||
@ -10,9 +10,9 @@
|
||||
|
||||
/* Clock indexes for use by Device Tree data and the PRCI driver */
|
||||
|
||||
#define PRCI_CLK_COREPLL 0
|
||||
#define PRCI_CLK_DDRPLL 1
|
||||
#define PRCI_CLK_GEMGXLPLL 2
|
||||
#define PRCI_CLK_TLCLK 3
|
||||
#define FU540_PRCI_CLK_COREPLL 0
|
||||
#define FU540_PRCI_CLK_DDRPLL 1
|
||||
#define FU540_PRCI_CLK_GEMGXLPLL 2
|
||||
#define FU540_PRCI_CLK_TLCLK 3
|
||||
|
||||
#endif
|
||||
|
||||
@ -11,14 +11,14 @@
|
||||
|
||||
/* Clock indexes for use by Device Tree data and the PRCI driver */
|
||||
|
||||
#define PRCI_CLK_COREPLL 0
|
||||
#define PRCI_CLK_DDRPLL 1
|
||||
#define PRCI_CLK_GEMGXLPLL 2
|
||||
#define PRCI_CLK_DVFSCOREPLL 3
|
||||
#define PRCI_CLK_HFPCLKPLL 4
|
||||
#define PRCI_CLK_CLTXPLL 5
|
||||
#define PRCI_CLK_TLCLK 6
|
||||
#define PRCI_CLK_PCLK 7
|
||||
#define PRCI_CLK_PCIE_AUX 8
|
||||
#define FU740_PRCI_CLK_COREPLL 0
|
||||
#define FU740_PRCI_CLK_DDRPLL 1
|
||||
#define FU740_PRCI_CLK_GEMGXLPLL 2
|
||||
#define FU740_PRCI_CLK_DVFSCOREPLL 3
|
||||
#define FU740_PRCI_CLK_HFPCLKPLL 4
|
||||
#define FU740_PRCI_CLK_CLTXPLL 5
|
||||
#define FU740_PRCI_CLK_TLCLK 6
|
||||
#define FU740_PRCI_CLK_PCLK 7
|
||||
#define FU740_PRCI_CLK_PCIE_AUX 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user