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ath9k_hw: Fill few hw cap for edma
HP & LP queue depth and rx status length. Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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drivers/net/wireless/ath/ath9k/ar9003_mac.h
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35
drivers/net/wireless/ath/ath9k/ar9003_mac.h
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@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef AR9003_MAC_H
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#define AR9003_MAC_H
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struct ar9003_rxs {
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u32 ds_info;
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u32 status1;
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u32 status2;
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u32 status3;
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u32 status4;
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u32 status5;
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u32 status6;
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u32 status7;
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u32 status8;
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u32 status9;
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u32 status10;
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u32 status11;
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} __packed;
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#endif
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@ -2873,8 +2873,12 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
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btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
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}
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if (AR_SREV_9300_20_OR_LATER(ah))
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
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pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
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pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
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pCap->rx_status_len = sizeof(struct ar9003_rxs);
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}
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return 0;
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}
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@ -28,6 +28,7 @@
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#include "reg.h"
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#include "phy.h"
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#include "btcoex.h"
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#include "ar9003_mac.h"
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#include "../regd.h"
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#include "../debug.h"
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@ -135,6 +136,9 @@
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#define TU_TO_USEC(_tu) ((_tu) << 10)
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#define ATH9K_HW_RX_HP_QDEPTH 16
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#define ATH9K_HW_RX_LP_QDEPTH 128
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enum wireless_mode {
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ATH9K_MODE_11A = 0,
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ATH9K_MODE_11G,
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@ -192,6 +196,9 @@ struct ath9k_hw_capabilities {
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u8 num_gpio_pins;
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u8 num_antcfg_2ghz;
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u8 num_antcfg_5ghz;
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u8 rx_hp_qdepth;
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u8 rx_lp_qdepth;
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u8 rx_status_len;
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};
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struct ath9k_ops_config {
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