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ARC: switch to generic bitops
- !LLSC now only needs a single spinlock for atomics and bitops
- Some codegen changes (slight bloat) with generic bitops
1. code increase due to LD-check-atomic paradigm vs. unconditonal
atomic (but dirty'ing the cache line even if set already).
So despite increase, generic is right thing to do.
2. code decrease (but use of costlier instructions such as DIV vs.
shifts based math) due to signed arithmetic.
This needs to be revisited seperately.
arc:
static inline int test_bit(unsigned int nr, const volatile unsigned long *addr)
^^^^^^^^^^^^
generic:
static inline int test_bit(int nr, const volatile unsigned long *addr)
^^^
Link: https://lore.kernel.org/r/20180830135749.GA13005@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
[vgupta: wrote patch based on Will's poc, analysed codegen diffs]
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
This commit is contained in:
Vineet Gupta
parent
b64be68369
commit
cea4314790
@ -14,188 +14,6 @@
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#include <linux/types.h>
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#include <linux/compiler.h>
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#include <asm/barrier.h>
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#ifndef CONFIG_ARC_HAS_LLSC
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#include <asm/smp.h>
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#endif
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#ifdef CONFIG_ARC_HAS_LLSC
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/*
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* Hardware assisted Atomic-R-M-W
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*/
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#define BIT_OP(op, c_op, asm_op) \
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static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
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{ \
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unsigned int temp; \
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\
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m += nr >> 5; \
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\
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nr &= 0x1f; \
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\
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__asm__ __volatile__( \
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"1: llock %0, [%1] \n" \
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" " #asm_op " %0, %0, %2 \n" \
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" scond %0, [%1] \n" \
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" bnz 1b \n" \
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: "=&r"(temp) /* Early clobber, to prevent reg reuse */ \
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: "r"(m), /* Not "m": llock only supports reg direct addr mode */ \
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"ir"(nr) \
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: "cc"); \
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}
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/*
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* Semantically:
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* Test the bit
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* if clear
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* set it and return 0 (old value)
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* else
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* return 1 (old value).
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*
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* Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
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* and the old value of bit is returned
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*/
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#define TEST_N_BIT_OP(op, c_op, asm_op) \
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static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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{ \
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unsigned long old, temp; \
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\
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m += nr >> 5; \
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\
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nr &= 0x1f; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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* LLOCK/SCOND themselves don't provide any such smenatic \
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*/ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: llock %0, [%2] \n" \
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" " #asm_op " %1, %0, %3 \n" \
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" scond %1, [%2] \n" \
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" bnz 1b \n" \
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: "=&r"(old), "=&r"(temp) \
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: "r"(m), "ir"(nr) \
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: "cc"); \
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\
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smp_mb(); \
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\
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return (old & (1 << nr)) != 0; \
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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/*
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* Non hardware assisted Atomic-R-M-W
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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*
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* There's "significant" micro-optimization in writing our own variants of
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* bitops (over generic variants)
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*
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* (1) The generic APIs have "signed" @nr while we have it "unsigned"
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* This avoids extra code to be generated for pointer arithmatic, since
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* is "not sure" that index is NOT -ve
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* (2) Utilize the fact that ARCompact bit fidding insn (BSET/BCLR/ASL) etc
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* only consider bottom 5 bits of @nr, so NO need to mask them off.
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* (GCC Quirk: however for constant @nr we still need to do the masking
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* at compile time)
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*/
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#define BIT_OP(op, c_op, asm_op) \
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static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
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{ \
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unsigned long temp, flags; \
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m += nr >> 5; \
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\
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/* \
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* spin lock/unlock provide the needed smp_mb() before/after \
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*/ \
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bitops_lock(flags); \
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\
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temp = *m; \
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*m = temp c_op (1UL << (nr & 0x1f)); \
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\
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bitops_unlock(flags); \
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}
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#define TEST_N_BIT_OP(op, c_op, asm_op) \
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static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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{ \
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unsigned long old, flags; \
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m += nr >> 5; \
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\
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bitops_lock(flags); \
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\
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old = *m; \
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*m = old c_op (1UL << (nr & 0x1f)); \
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\
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bitops_unlock(flags); \
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\
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return (old & (1UL << (nr & 0x1f))) != 0; \
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}
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#endif
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/***************************************
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* Non atomic variants
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**************************************/
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#define __BIT_OP(op, c_op, asm_op) \
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static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \
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{ \
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unsigned long temp; \
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m += nr >> 5; \
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\
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temp = *m; \
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*m = temp c_op (1UL << (nr & 0x1f)); \
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}
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#define __TEST_N_BIT_OP(op, c_op, asm_op) \
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static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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{ \
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unsigned long old; \
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m += nr >> 5; \
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\
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old = *m; \
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*m = old c_op (1UL << (nr & 0x1f)); \
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\
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return (old & (1UL << (nr & 0x1f))) != 0; \
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}
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#define BIT_OPS(op, c_op, asm_op) \
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\
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/* set_bit(), clear_bit(), change_bit() */ \
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BIT_OP(op, c_op, asm_op) \
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\
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/* test_and_set_bit(), test_and_clear_bit(), test_and_change_bit() */\
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TEST_N_BIT_OP(op, c_op, asm_op) \
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\
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/* __set_bit(), __clear_bit(), __change_bit() */ \
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__BIT_OP(op, c_op, asm_op) \
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\
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/* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
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__TEST_N_BIT_OP(op, c_op, asm_op)
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BIT_OPS(set, |, bset)
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BIT_OPS(clear, & ~, bclr)
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BIT_OPS(change, ^, bxor)
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/*
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* This routine doesn't need to be atomic.
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*/
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static inline int
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test_bit(unsigned int nr, const volatile unsigned long *addr)
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{
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unsigned long mask;
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addr += nr >> 5;
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mask = 1UL << (nr & 0x1f);
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return ((mask & *addr) != 0);
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}
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#ifdef CONFIG_ISA_ARCOMPACT
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@ -368,6 +186,8 @@ static inline __attribute__ ((const)) unsigned long __ffs(unsigned long x)
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/lock.h>
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#include <asm-generic/bitops/atomic.h>
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#include <asm-generic/bitops/non-atomic.h>
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/le.h>
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@ -105,7 +105,6 @@ static inline const char *arc_platform_smp_cpuinfo(void)
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#include <asm/spinlock.h>
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extern arch_spinlock_t smp_atomic_ops_lock;
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extern arch_spinlock_t smp_bitops_lock;
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#define atomic_ops_lock(flags) do { \
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local_irq_save(flags); \
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@ -117,24 +116,11 @@ extern arch_spinlock_t smp_bitops_lock;
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local_irq_restore(flags); \
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} while (0)
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#define bitops_lock(flags) do { \
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local_irq_save(flags); \
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arch_spin_lock(&smp_bitops_lock); \
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} while (0)
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#define bitops_unlock(flags) do { \
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arch_spin_unlock(&smp_bitops_lock); \
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local_irq_restore(flags); \
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} while (0)
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#else /* !CONFIG_SMP */
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#define atomic_ops_lock(flags) local_irq_save(flags)
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#define atomic_ops_unlock(flags) local_irq_restore(flags)
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#define bitops_lock(flags) local_irq_save(flags)
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#define bitops_unlock(flags) local_irq_restore(flags)
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#endif /* !CONFIG_SMP */
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#endif /* !CONFIG_ARC_HAS_LLSC */
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@ -29,10 +29,8 @@
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#ifndef CONFIG_ARC_HAS_LLSC
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arch_spinlock_t smp_atomic_ops_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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arch_spinlock_t smp_bitops_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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EXPORT_SYMBOL_GPL(smp_atomic_ops_lock);
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EXPORT_SYMBOL_GPL(smp_bitops_lock);
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#endif
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struct plat_smp_ops __weak plat_smp_ops;
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