mirror of
https://github.com/edk2-porting/linux-next.git
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Merge tag 'drm-intel-fixes-2017-10-26' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
One fix for stable: - fix perf enable/disable ioctls for 32bits (Lionel) Plus GVT fixes: - Fix per_ctx_bb check (Zhenyu) - Fix GPU hang of Linux guest (Xion) - Refine MMIO_RING_F to check for presence of VCS2 ring (Zhi) * tag 'drm-intel-fixes-2017-10-26' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915/gvt: Adding ACTHD mmio read handler drm/i915/gvt: Extract mmio_read_from_hw() common function drm/i915/gvt: Refine MMIO_RING_F() drm/i915/gvt: properly check per_ctx bb valid state
This commit is contained in:
commit
ce485df43d
@ -2723,6 +2723,9 @@ static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
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uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
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unsigned char *bb_start_sva;
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unsigned char *bb_start_sva;
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if (!wa_ctx->per_ctx.valid)
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return 0;
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per_ctx_start[0] = 0x18800001;
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per_ctx_start[0] = 0x18800001;
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per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
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per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
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@ -701,8 +701,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
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CACHELINE_BYTES;
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CACHELINE_BYTES;
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workload->wa_ctx.per_ctx.guest_gma =
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workload->wa_ctx.per_ctx.guest_gma =
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per_ctx & PER_CTX_ADDR_MASK;
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per_ctx & PER_CTX_ADDR_MASK;
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workload->wa_ctx.per_ctx.valid = per_ctx & 1;
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WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));
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}
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}
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if (emulate_schedule_in)
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if (emulate_schedule_in)
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@ -1429,18 +1429,7 @@ static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
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return 0;
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return 0;
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}
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}
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static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
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static int mmio_read_from_hw(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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mmio_hw_access_pre(dev_priv);
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vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
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mmio_hw_access_post(dev_priv);
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return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
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}
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static int instdone_mmio_read(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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@ -1589,6 +1578,8 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
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MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
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MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
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MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
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MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
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MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
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MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
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if (HAS_BSD2(dev_priv)) \
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MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
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} while (0)
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} while (0)
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#define MMIO_RING_D(prefix, d) \
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#define MMIO_RING_D(prefix, d) \
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@ -1635,10 +1626,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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#undef RING_REG
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#undef RING_REG
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#define RING_REG(base) (base + 0x6c)
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#define RING_REG(base) (base + 0x6c)
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MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL);
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MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
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MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL);
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#undef RING_REG
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#undef RING_REG
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MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL);
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MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
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MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
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MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
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MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
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MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
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@ -1648,7 +1638,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
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MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
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MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
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/* RING MODE */
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/* RING MODE */
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@ -1662,9 +1652,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
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MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
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NULL, NULL);
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NULL, NULL);
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MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
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MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
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ring_timestamp_mmio_read, NULL);
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mmio_read_from_hw, NULL);
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MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
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MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
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ring_timestamp_mmio_read, NULL);
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mmio_read_from_hw, NULL);
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MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
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MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
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@ -2411,9 +2401,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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int ret;
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int ret;
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MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL,
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intel_vgpu_reg_imr_handler);
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MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
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MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
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MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
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MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
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MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
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MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
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@ -2476,68 +2463,34 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
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MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
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MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
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intel_vgpu_reg_master_irq_handler);
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intel_vgpu_reg_master_irq_handler);
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MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
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MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
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F_CMD_ACCESS, NULL, NULL);
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mmio_read_from_hw, NULL);
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MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
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NULL, NULL);
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MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
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F_CMD_ACCESS, NULL, NULL);
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MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
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MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
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NULL, NULL);
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MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
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F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
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F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
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ring_mode_mmio_write);
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MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
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F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
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F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
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ring_timestamp_mmio_read, NULL);
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MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
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#define RING_REG(base) (base + 0xd0)
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#define RING_REG(base) (base + 0xd0)
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MMIO_RING_F(RING_REG, 4, F_RO, 0,
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MMIO_RING_F(RING_REG, 4, F_RO, 0,
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~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
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~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
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ring_reset_ctl_write);
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ring_reset_ctl_write);
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MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0,
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~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
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ring_reset_ctl_write);
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#undef RING_REG
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#undef RING_REG
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#define RING_REG(base) (base + 0x230)
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#define RING_REG(base) (base + 0x230)
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MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
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MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
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MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);
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#undef RING_REG
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#undef RING_REG
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#define RING_REG(base) (base + 0x234)
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#define RING_REG(base) (base + 0x234)
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MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
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MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
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NULL, NULL);
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NULL, NULL);
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MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0,
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~0LL, D_BDW_PLUS, NULL, NULL);
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#undef RING_REG
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#undef RING_REG
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#define RING_REG(base) (base + 0x244)
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#define RING_REG(base) (base + 0x244)
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MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
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MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
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NULL, NULL);
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#undef RING_REG
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#undef RING_REG
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#define RING_REG(base) (base + 0x370)
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#define RING_REG(base) (base + 0x370)
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MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
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MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
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MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,
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NULL, NULL);
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#undef RING_REG
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#undef RING_REG
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#define RING_REG(base) (base + 0x3a0)
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#define RING_REG(base) (base + 0x3a0)
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MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
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MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
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MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
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#undef RING_REG
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#undef RING_REG
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MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
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MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
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@ -2557,11 +2510,9 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
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#define RING_REG(base) (base + 0x270)
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#define RING_REG(base) (base + 0x270)
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MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
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MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
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MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
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#undef RING_REG
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#undef RING_REG
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MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
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MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
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MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
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MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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@ -2849,7 +2800,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
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MMIO_D(0x65f08, D_SKL | D_KBL);
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MMIO_D(0x65f08, D_SKL | D_KBL);
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MMIO_D(0x320f0, D_SKL | D_KBL);
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MMIO_D(0x320f0, D_SKL | D_KBL);
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MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
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MMIO_D(0x70034, D_SKL_PLUS);
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MMIO_D(0x70034, D_SKL_PLUS);
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MMIO_D(0x71034, D_SKL_PLUS);
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MMIO_D(0x71034, D_SKL_PLUS);
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MMIO_D(0x72034, D_SKL_PLUS);
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MMIO_D(0x72034, D_SKL_PLUS);
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@ -54,9 +54,6 @@
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#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
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#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
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#define _REG_VECS_EXCC 0x1A028
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#define _REG_VCS2_EXCC 0x1c028
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#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
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#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
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#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
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#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
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@ -68,6 +68,7 @@ struct shadow_indirect_ctx {
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struct shadow_per_ctx {
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struct shadow_per_ctx {
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unsigned long guest_gma;
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unsigned long guest_gma;
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unsigned long shadow_gma;
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unsigned long shadow_gma;
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unsigned valid;
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};
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};
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struct intel_shadow_wa_ctx {
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struct intel_shadow_wa_ctx {
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