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clk: exynos5420: fix cpll clock register offsets
Fixes cpll control and lock register offset values for Exynos5420 SoC. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -737,8 +737,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
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static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
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[apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
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APLL_CON0, NULL),
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[cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
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MPLL_CON0, NULL),
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[cpll] = PLL(pll_2550, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK,
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CPLL_CON0, NULL),
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[dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK,
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DPLL_CON0, NULL),
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[epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
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