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https://github.com/edk2-porting/linux-next.git
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[SCSI] SCSI: Support Type C RAID controller
1. To support Type C RAID controller, ACB_ADAPTER_TYPE_C, i.e. PCI device ID: 0x1880. Signed-off-by: Nick Cheng< nick.cheng@areca.com.tw > Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
Nick Cheng
James Bottomley
parent
a91c1be217
commit
cdd3cb156f
@ -43,12 +43,11 @@
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*******************************************************************************
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*/
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#include <linux/interrupt.h>
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struct device_attribute;
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/*The limit of outstanding scsi command that firmware can handle*/
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#define ARCMSR_MAX_OUTSTANDING_CMD 256
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#define ARCMSR_MAX_FREECCB_NUM 320
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#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2009/12/09"
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#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2010/02/02"
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#define ARCMSR_SCSI_INITIATOR_ID 255
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#define ARCMSR_MAX_XFER_SECTORS 512
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#define ARCMSR_MAX_XFER_SECTORS_B 4096
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@ -60,7 +59,8 @@ struct device_attribute;
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#define ARCMSR_DEFAULT_SG_ENTRIES 38
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#define ARCMSR_MAX_HBB_POSTQUEUE 264
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#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
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#define ARCMSR_CDB_SG_PAGE_LENGTH 256
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#define ARCMSR_CDB_SG_PAGE_LENGTH 256
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#define SCSI_CMD_ARECA_SPECIFIC 0xE1
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#ifndef PCI_DEVICE_ID_ARECA_1880
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#define PCI_DEVICE_ID_ARECA_1880 0x1880
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#endif
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@ -138,9 +138,9 @@ struct CMD_MESSAGE_FIELD
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#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
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ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
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/* ARECA IOCTL ReturnCode */
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#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
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#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
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#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
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#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
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#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
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#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
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#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
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/*
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*************************************************************
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@ -153,13 +153,13 @@ struct SG32ENTRY
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{
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__le32 length;
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__le32 address;
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} __attribute__ ((packed));
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}__attribute__ ((packed));
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struct SG64ENTRY
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{
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__le32 length;
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__le32 address;
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__le32 addresshigh;
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} __attribute__ ((packed));
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}__attribute__ ((packed));
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/*
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********************************************************************
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** Q Buffer of IOP Message Transfer
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@ -186,9 +186,9 @@ struct FIRMWARE_INFO
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char model[8]; /*15, 60-67*/
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char firmware_ver[16]; /*17, 68-83*/
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char device_map[16]; /*21, 84-99*/
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uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
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uint8_t cfgSerial[16]; /*26,104-119*/
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uint32_t cfgPicStatus; /*30,120-123*/
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uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
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uint8_t cfgSerial[16]; /*26,104-119*/
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uint32_t cfgPicStatus; /*30,120-123*/
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};
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/* signature of set and get firmware config */
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#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
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@ -212,11 +212,15 @@ struct FIRMWARE_INFO
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#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
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#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
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#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
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/* outbound firmware ok */
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#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
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/* ARC-1680 Bus Reset*/
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#define ARCMSR_ARC1680_BUS_RESET 0x00000003
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/* ARC-1880 Bus Reset*/
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#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
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#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
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/*
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************************************************************************
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@ -273,6 +277,61 @@ struct FIRMWARE_INFO
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#define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
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/* iop message_rwbuffer for message command */
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#define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
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/*
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************************************************************************
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** SPEC. for Areca HBC adapter
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************************************************************************
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*/
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#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
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#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
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/* Host Interrupt Mask */
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#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
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#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
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#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
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#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
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/* Host Interrupt Status */
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#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
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/*
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** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
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** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
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*/
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#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
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/*
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** Set if Outbound Doorbell register bits 30:1 have a non-zero
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** value. This bit clears only when Outbound Doorbell bits
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** 30:1 are ALL clear. Only a write to the Outbound Doorbell
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** Clear register clears bits in the Outbound Doorbell register.
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*/
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#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
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/*
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** Set whenever the Outbound Post List Producer/Consumer
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** Register (FIFO) is not empty. It clears when the Outbound
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** Post List FIFO is empty.
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*/
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#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
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/*
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** This bit indicates a SAS interrupt from a source external to
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** the PCIe core. This bit is not maskable.
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*/
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/* DoorBell*/
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#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
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#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
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/*inbound message 0 ready*/
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#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
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/*more than 12 request completed in a time*/
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#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
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#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
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/*outbound DATA WRITE isr door bell clear*/
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#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
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#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
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/*outbound DATA READ isr door bell clear*/
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#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
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/*outbound message 0 ready*/
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#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
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/*outbound message cmd isr door bell clear*/
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#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
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/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
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#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
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/*
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*******************************************************************************
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** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
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@ -310,7 +369,7 @@ struct ARCMSR_CDB
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struct SG32ENTRY sg32entry[1];
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struct SG64ENTRY sg64entry[1];
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} u;
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} __attribute__ ((packed));
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};
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/*
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*******************************************************************************
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** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
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@ -356,7 +415,81 @@ struct MessageUnit_B
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uint32_t __iomem *message_wbuffer;
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uint32_t __iomem *message_rbuffer;
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};
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/*
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*********************************************************************
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** LSI
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*********************************************************************
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*/
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struct MessageUnit_C{
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uint32_t message_unit_status; /*0000 0003*/
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uint32_t slave_error_attribute; /*0004 0007*/
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uint32_t slave_error_address; /*0008 000B*/
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uint32_t posted_outbound_doorbell; /*000C 000F*/
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uint32_t master_error_attribute; /*0010 0013*/
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uint32_t master_error_address_low; /*0014 0017*/
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uint32_t master_error_address_high; /*0018 001B*/
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uint32_t hcb_size; /*001C 001F*/
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uint32_t inbound_doorbell; /*0020 0023*/
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uint32_t diagnostic_rw_data; /*0024 0027*/
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uint32_t diagnostic_rw_address_low; /*0028 002B*/
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uint32_t diagnostic_rw_address_high; /*002C 002F*/
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uint32_t host_int_status; /*0030 0033*/
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uint32_t host_int_mask; /*0034 0037*/
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uint32_t dcr_data; /*0038 003B*/
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uint32_t dcr_address; /*003C 003F*/
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uint32_t inbound_queueport; /*0040 0043*/
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uint32_t outbound_queueport; /*0044 0047*/
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uint32_t hcb_pci_address_low; /*0048 004B*/
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uint32_t hcb_pci_address_high; /*004C 004F*/
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uint32_t iop_int_status; /*0050 0053*/
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uint32_t iop_int_mask; /*0054 0057*/
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uint32_t iop_inbound_queue_port; /*0058 005B*/
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uint32_t iop_outbound_queue_port; /*005C 005F*/
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uint32_t inbound_free_list_index; /*0060 0063*/
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uint32_t inbound_post_list_index; /*0064 0067*/
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uint32_t outbound_free_list_index; /*0068 006B*/
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uint32_t outbound_post_list_index; /*006C 006F*/
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uint32_t inbound_doorbell_clear; /*0070 0073*/
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uint32_t i2o_message_unit_control; /*0074 0077*/
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uint32_t last_used_message_source_address_low; /*0078 007B*/
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uint32_t last_used_message_source_address_high; /*007C 007F*/
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uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
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uint32_t message_dest_address_index; /*0090 0093*/
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uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
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uint32_t utility_A_int_counter_timer; /*0098 009B*/
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uint32_t outbound_doorbell; /*009C 009F*/
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uint32_t outbound_doorbell_clear; /*00A0 00A3*/
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uint32_t message_source_address_index; /*00A4 00A7*/
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uint32_t message_done_queue_index; /*00A8 00AB*/
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uint32_t reserved0; /*00AC 00AF*/
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uint32_t inbound_msgaddr0; /*00B0 00B3*/
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uint32_t inbound_msgaddr1; /*00B4 00B7*/
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uint32_t outbound_msgaddr0; /*00B8 00BB*/
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uint32_t outbound_msgaddr1; /*00BC 00BF*/
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uint32_t inbound_queueport_low; /*00C0 00C3*/
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uint32_t inbound_queueport_high; /*00C4 00C7*/
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uint32_t outbound_queueport_low; /*00C8 00CB*/
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uint32_t outbound_queueport_high; /*00CC 00CF*/
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uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
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uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
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uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
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uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
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uint32_t message_dest_queue_port_low; /*00E0 00E3*/
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uint32_t message_dest_queue_port_high; /*00E4 00E7*/
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uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
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uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
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uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
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uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
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uint32_t host_diagnostic; /*00F8 00FB*/
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uint32_t write_sequence; /*00FC 00FF*/
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uint32_t reserved1[34]; /*0100 0187*/
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uint32_t reserved2[1950]; /*0188 1FFF*/
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uint32_t message_wbuffer[32]; /*2000 207F*/
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uint32_t reserved3[32]; /*2080 20FF*/
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uint32_t message_rbuffer[32]; /*2100 217F*/
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uint32_t reserved4[32]; /*2180 21FF*/
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uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
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};
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/*
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*******************************************************************************
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** Adapter Control Block
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@ -374,11 +507,14 @@ struct AdapterControlBlock
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unsigned long vir2phy_offset;
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/* Offset is used in making arc cdb physical to virtual calculations */
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uint32_t outbound_int_enable;
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uint32_t cdb_phyaddr_hi32;
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uint32_t reg_mu_acc_handle0;
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spinlock_t eh_lock;
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spinlock_t ccblist_lock;
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union {
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struct MessageUnit_A __iomem * pmuA;
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struct MessageUnit_B * pmuB;
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struct MessageUnit_A __iomem *pmuA;
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struct MessageUnit_B *pmuB;
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struct MessageUnit_C __iomem *pmuC;
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};
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/* message unit ATU inbound base address0 */
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void __iomem *mem_base0;
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@ -399,6 +535,8 @@ struct AdapterControlBlock
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/* message clear rqbuffer */
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#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
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#define ACB_F_BUS_RESET 0x0080
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#define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */
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#define ACB_F_IOP_INITED 0x0100
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/* iop init */
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#define ACB_F_ABORT 0x0200
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@ -441,9 +579,9 @@ struct AdapterControlBlock
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uint32_t firm_numbers_queue;
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uint32_t firm_sdram_size;
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uint32_t firm_hd_channels;
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uint32_t firm_cfg_version;
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char firm_model[12];
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char firm_version[20];
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uint32_t firm_cfg_version;
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char firm_model[12];
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char firm_version[20];
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char device_map[20]; /*21,84-99*/
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struct work_struct arcmsr_do_message_isr_bh;
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struct timer_list eternal_timer;
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@ -460,31 +598,31 @@ struct AdapterControlBlock
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** this CCB length must be 32 bytes boundary
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*******************************************************************************
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*/
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struct CommandControlBlock
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{
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struct CommandControlBlock{
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/*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
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struct list_head list; /*x32: 8byte, x64: 16byte*/
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struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
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struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
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uint32_t shifted_cdb_phyaddr; /*x32: 4byte, x64: 4byte*/
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uint32_t cdb_phyaddr_pattern; /*x32: 4byte, x64: 4byte*/
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uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
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uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
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#define CCB_FLAG_READ 0x0000
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#define CCB_FLAG_WRITE 0x0001
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#define CCB_FLAG_ERROR 0x0002
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#define CCB_FLAG_FLUSHCACHE 0x0004
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#define CCB_FLAG_MASTER_ABORTED 0x0008
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#define CCB_FLAG_READ 0x0000
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#define CCB_FLAG_WRITE 0x0001
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#define CCB_FLAG_ERROR 0x0002
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#define CCB_FLAG_FLUSHCACHE 0x0004
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#define CCB_FLAG_MASTER_ABORTED 0x0008
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uint16_t startdone; /*x32:2byte,x32:2byte*/
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#define ARCMSR_CCB_DONE 0x0000
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#define ARCMSR_CCB_START 0x55AA
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#define ARCMSR_CCB_ABORTED 0xAA55
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#define ARCMSR_CCB_ILLEGAL 0xFFFF
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#define ARCMSR_CCB_DONE 0x0000
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#define ARCMSR_CCB_START 0x55AA
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#define ARCMSR_CCB_ABORTED 0xAA55
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#define ARCMSR_CCB_ILLEGAL 0xFFFF
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#if BITS_PER_LONG == 64
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/* ======================512+64 bytes======================== */
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uint32_t reserved[6]; /*24 byte*/
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#else
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uint32_t reserved[5]; /*24 byte*/
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#else
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/* ======================512+32 bytes======================== */
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uint32_t reserved[2]; /*8 byte*/
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#endif
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uint32_t reserved; /*8 byte*/
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#endif
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/* ======================================================= */
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struct ARCMSR_CDB arcmsr_cdb;
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};
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@ -59,8 +59,7 @@
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struct device_attribute *arcmsr_host_attrs[];
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static ssize_t arcmsr_sysfs_iop_message_read(struct file *filp,
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struct kobject *kobj,
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static ssize_t arcmsr_sysfs_iop_message_read(struct kobject *kobj,
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struct bin_attribute *bin,
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char *buf, loff_t off,
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size_t count)
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@ -106,8 +105,7 @@ static ssize_t arcmsr_sysfs_iop_message_read(struct file *filp,
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return (allxfer_len);
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}
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static ssize_t arcmsr_sysfs_iop_message_write(struct file *filp,
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struct kobject *kobj,
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static ssize_t arcmsr_sysfs_iop_message_write(struct kobject *kobj,
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struct bin_attribute *bin,
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char *buf, loff_t off,
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size_t count)
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@ -155,8 +153,7 @@ static ssize_t arcmsr_sysfs_iop_message_write(struct file *filp,
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}
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}
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static ssize_t arcmsr_sysfs_iop_message_clear(struct file *filp,
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struct kobject *kobj,
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static ssize_t arcmsr_sysfs_iop_message_clear(struct kobject *kobj,
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struct bin_attribute *bin,
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char *buf, loff_t off,
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size_t count)
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