mirror of
https://github.com/edk2-porting/linux-next.git
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drm/radeon/dce8: add support for display watermark setup
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
bc19f59704
commit
cd84a27d18
@ -5017,3 +5017,540 @@ void cik_fini(struct radeon_device *rdev)
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kfree(rdev->bios);
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rdev->bios = NULL;
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}
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/* display watermark setup */
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/**
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* dce8_line_buffer_adjust - Set up the line buffer
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*
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* @rdev: radeon_device pointer
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* @radeon_crtc: the selected display controller
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* @mode: the current display mode on the selected display
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* controller
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*
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* Setup up the line buffer allocation for
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* the selected display controller (CIK).
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* Returns the line buffer size in pixels.
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*/
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static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
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struct radeon_crtc *radeon_crtc,
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struct drm_display_mode *mode)
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{
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u32 tmp;
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/*
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* Line Buffer Setup
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* There are 6 line buffers, one for each display controllers.
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* There are 3 partitions per LB. Select the number of partitions
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* to enable based on the display width. For display widths larger
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* than 4096, you need use to use 2 display controllers and combine
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* them using the stereo blender.
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*/
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if (radeon_crtc->base.enabled && mode) {
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if (mode->crtc_hdisplay < 1920)
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tmp = 1;
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else if (mode->crtc_hdisplay < 2560)
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tmp = 2;
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else if (mode->crtc_hdisplay < 4096)
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tmp = 0;
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else {
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DRM_DEBUG_KMS("Mode too big for LB!\n");
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tmp = 0;
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}
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} else
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tmp = 1;
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WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
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LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
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if (radeon_crtc->base.enabled && mode) {
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switch (tmp) {
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case 0:
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default:
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return 4096 * 2;
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case 1:
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return 1920 * 2;
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case 2:
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return 2560 * 2;
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}
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}
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/* controller not enabled, so no lb used */
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return 0;
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}
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/**
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* cik_get_number_of_dram_channels - get the number of dram channels
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*
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* @rdev: radeon_device pointer
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*
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* Look up the number of video ram channels (CIK).
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* Used for display watermark bandwidth calculations
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* Returns the number of dram channels
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*/
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static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)
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{
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u32 tmp = RREG32(MC_SHARED_CHMAP);
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switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
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case 0:
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default:
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return 1;
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case 1:
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return 2;
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case 2:
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return 4;
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case 3:
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return 8;
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case 4:
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return 3;
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case 5:
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return 6;
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case 6:
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return 10;
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case 7:
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return 12;
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case 8:
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return 16;
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}
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}
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struct dce8_wm_params {
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u32 dram_channels; /* number of dram channels */
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u32 yclk; /* bandwidth per dram data pin in kHz */
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u32 sclk; /* engine clock in kHz */
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u32 disp_clk; /* display clock in kHz */
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u32 src_width; /* viewport width */
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u32 active_time; /* active display time in ns */
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u32 blank_time; /* blank time in ns */
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bool interlaced; /* mode is interlaced */
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fixed20_12 vsc; /* vertical scale ratio */
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u32 num_heads; /* number of active crtcs */
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u32 bytes_per_pixel; /* bytes per pixel display + overlay */
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u32 lb_size; /* line buffer allocated to pipe */
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u32 vtaps; /* vertical scaler taps */
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};
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/**
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* dce8_dram_bandwidth - get the dram bandwidth
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*
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* @wm: watermark calculation data
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*
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* Calculate the raw dram bandwidth (CIK).
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* Used for display watermark bandwidth calculations
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* Returns the dram bandwidth in MBytes/s
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*/
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static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)
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{
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/* Calculate raw DRAM Bandwidth */
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fixed20_12 dram_efficiency; /* 0.7 */
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fixed20_12 yclk, dram_channels, bandwidth;
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fixed20_12 a;
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a.full = dfixed_const(1000);
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yclk.full = dfixed_const(wm->yclk);
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yclk.full = dfixed_div(yclk, a);
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dram_channels.full = dfixed_const(wm->dram_channels * 4);
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a.full = dfixed_const(10);
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dram_efficiency.full = dfixed_const(7);
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dram_efficiency.full = dfixed_div(dram_efficiency, a);
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bandwidth.full = dfixed_mul(dram_channels, yclk);
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bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
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return dfixed_trunc(bandwidth);
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}
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/**
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* dce8_dram_bandwidth_for_display - get the dram bandwidth for display
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*
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* @wm: watermark calculation data
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*
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* Calculate the dram bandwidth used for display (CIK).
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* Used for display watermark bandwidth calculations
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* Returns the dram bandwidth for display in MBytes/s
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*/
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static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm)
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{
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/* Calculate DRAM Bandwidth and the part allocated to display. */
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fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
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fixed20_12 yclk, dram_channels, bandwidth;
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fixed20_12 a;
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a.full = dfixed_const(1000);
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yclk.full = dfixed_const(wm->yclk);
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yclk.full = dfixed_div(yclk, a);
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dram_channels.full = dfixed_const(wm->dram_channels * 4);
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a.full = dfixed_const(10);
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disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
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disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
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bandwidth.full = dfixed_mul(dram_channels, yclk);
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bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
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return dfixed_trunc(bandwidth);
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}
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/**
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* dce8_data_return_bandwidth - get the data return bandwidth
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*
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* @wm: watermark calculation data
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*
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* Calculate the data return bandwidth used for display (CIK).
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* Used for display watermark bandwidth calculations
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* Returns the data return bandwidth in MBytes/s
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*/
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static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm)
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{
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/* Calculate the display Data return Bandwidth */
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fixed20_12 return_efficiency; /* 0.8 */
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fixed20_12 sclk, bandwidth;
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fixed20_12 a;
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a.full = dfixed_const(1000);
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sclk.full = dfixed_const(wm->sclk);
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sclk.full = dfixed_div(sclk, a);
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a.full = dfixed_const(10);
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return_efficiency.full = dfixed_const(8);
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return_efficiency.full = dfixed_div(return_efficiency, a);
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a.full = dfixed_const(32);
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bandwidth.full = dfixed_mul(a, sclk);
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bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
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return dfixed_trunc(bandwidth);
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}
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/**
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* dce8_dmif_request_bandwidth - get the dmif bandwidth
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*
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* @wm: watermark calculation data
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*
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* Calculate the dmif bandwidth used for display (CIK).
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* Used for display watermark bandwidth calculations
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* Returns the dmif bandwidth in MBytes/s
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*/
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static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm)
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{
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/* Calculate the DMIF Request Bandwidth */
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fixed20_12 disp_clk_request_efficiency; /* 0.8 */
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fixed20_12 disp_clk, bandwidth;
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fixed20_12 a, b;
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a.full = dfixed_const(1000);
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disp_clk.full = dfixed_const(wm->disp_clk);
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disp_clk.full = dfixed_div(disp_clk, a);
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a.full = dfixed_const(32);
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b.full = dfixed_mul(a, disp_clk);
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a.full = dfixed_const(10);
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disp_clk_request_efficiency.full = dfixed_const(8);
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disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
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bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
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return dfixed_trunc(bandwidth);
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}
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/**
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* dce8_available_bandwidth - get the min available bandwidth
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*
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* @wm: watermark calculation data
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*
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* Calculate the min available bandwidth used for display (CIK).
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* Used for display watermark bandwidth calculations
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* Returns the min available bandwidth in MBytes/s
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*/
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static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)
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{
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/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
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u32 dram_bandwidth = dce8_dram_bandwidth(wm);
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u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);
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u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);
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return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
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}
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/**
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* dce8_average_bandwidth - get the average available bandwidth
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*
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* @wm: watermark calculation data
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*
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* Calculate the average available bandwidth used for display (CIK).
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* Used for display watermark bandwidth calculations
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* Returns the average available bandwidth in MBytes/s
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*/
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static u32 dce8_average_bandwidth(struct dce8_wm_params *wm)
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{
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/* Calculate the display mode Average Bandwidth
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* DisplayMode should contain the source and destination dimensions,
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* timing, etc.
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*/
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fixed20_12 bpp;
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fixed20_12 line_time;
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fixed20_12 src_width;
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fixed20_12 bandwidth;
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fixed20_12 a;
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a.full = dfixed_const(1000);
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line_time.full = dfixed_const(wm->active_time + wm->blank_time);
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line_time.full = dfixed_div(line_time, a);
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bpp.full = dfixed_const(wm->bytes_per_pixel);
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src_width.full = dfixed_const(wm->src_width);
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bandwidth.full = dfixed_mul(src_width, bpp);
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bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
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bandwidth.full = dfixed_div(bandwidth, line_time);
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return dfixed_trunc(bandwidth);
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}
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/**
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* dce8_latency_watermark - get the latency watermark
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*
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* @wm: watermark calculation data
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*
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* Calculate the latency watermark (CIK).
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* Used for display watermark bandwidth calculations
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* Returns the latency watermark in ns
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*/
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static u32 dce8_latency_watermark(struct dce8_wm_params *wm)
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{
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/* First calculate the latency in ns */
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u32 mc_latency = 2000; /* 2000 ns. */
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u32 available_bandwidth = dce8_available_bandwidth(wm);
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u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
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u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
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u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
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u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
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(wm->num_heads * cursor_line_pair_return_time);
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u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
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u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
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u32 tmp, dmif_size = 12288;
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fixed20_12 a, b, c;
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if (wm->num_heads == 0)
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return 0;
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a.full = dfixed_const(2);
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b.full = dfixed_const(1);
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if ((wm->vsc.full > a.full) ||
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((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
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(wm->vtaps >= 5) ||
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((wm->vsc.full >= a.full) && wm->interlaced))
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max_src_lines_per_dst_line = 4;
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else
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max_src_lines_per_dst_line = 2;
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a.full = dfixed_const(available_bandwidth);
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b.full = dfixed_const(wm->num_heads);
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a.full = dfixed_div(a, b);
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b.full = dfixed_const(mc_latency + 512);
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c.full = dfixed_const(wm->disp_clk);
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b.full = dfixed_div(b, c);
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c.full = dfixed_const(dmif_size);
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b.full = dfixed_div(c, b);
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tmp = min(dfixed_trunc(a), dfixed_trunc(b));
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b.full = dfixed_const(1000);
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c.full = dfixed_const(wm->disp_clk);
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b.full = dfixed_div(c, b);
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c.full = dfixed_const(wm->bytes_per_pixel);
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b.full = dfixed_mul(b, c);
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lb_fill_bw = min(tmp, dfixed_trunc(b));
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a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
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b.full = dfixed_const(1000);
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c.full = dfixed_const(lb_fill_bw);
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b.full = dfixed_div(c, b);
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a.full = dfixed_div(a, b);
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line_fill_time = dfixed_trunc(a);
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if (line_fill_time < wm->active_time)
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return latency;
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else
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return latency + (line_fill_time - wm->active_time);
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}
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/**
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* dce8_average_bandwidth_vs_dram_bandwidth_for_display - check
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* average and available dram bandwidth
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*
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* @wm: watermark calculation data
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*
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* Check if the display average bandwidth fits in the display
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* dram bandwidth (CIK).
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* Used for display watermark bandwidth calculations
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* Returns true if the display fits, false if not.
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*/
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static bool dce8_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
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{
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if (dce8_average_bandwidth(wm) <=
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(dce8_dram_bandwidth_for_display(wm) / wm->num_heads))
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return true;
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else
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return false;
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}
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/**
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* dce8_average_bandwidth_vs_available_bandwidth - check
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* average and available bandwidth
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*
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* @wm: watermark calculation data
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*
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* Check if the display average bandwidth fits in the display
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* available bandwidth (CIK).
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* Used for display watermark bandwidth calculations
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* Returns true if the display fits, false if not.
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*/
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static bool dce8_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
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{
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if (dce8_average_bandwidth(wm) <=
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(dce8_available_bandwidth(wm) / wm->num_heads))
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return true;
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else
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return false;
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}
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/**
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* dce8_check_latency_hiding - check latency hiding
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*
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* @wm: watermark calculation data
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*
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* Check latency hiding (CIK).
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* Used for display watermark bandwidth calculations
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* Returns true if the display fits, false if not.
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*/
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static bool dce8_check_latency_hiding(struct dce8_wm_params *wm)
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{
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u32 lb_partitions = wm->lb_size / wm->src_width;
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u32 line_time = wm->active_time + wm->blank_time;
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u32 latency_tolerant_lines;
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u32 latency_hiding;
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fixed20_12 a;
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a.full = dfixed_const(1);
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if (wm->vsc.full > a.full)
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latency_tolerant_lines = 1;
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else {
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if (lb_partitions <= (wm->vtaps + 1))
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latency_tolerant_lines = 1;
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else
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latency_tolerant_lines = 2;
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}
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latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
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if (dce8_latency_watermark(wm) <= latency_hiding)
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return true;
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else
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return false;
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}
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/**
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* dce8_program_watermarks - program display watermarks
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*
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* @rdev: radeon_device pointer
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* @radeon_crtc: the selected display controller
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* @lb_size: line buffer size
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* @num_heads: number of display controllers in use
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*
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* Calculate and program the display watermarks for the
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* selected display controller (CIK).
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*/
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static void dce8_program_watermarks(struct radeon_device *rdev,
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struct radeon_crtc *radeon_crtc,
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u32 lb_size, u32 num_heads)
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{
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struct drm_display_mode *mode = &radeon_crtc->base.mode;
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struct dce8_wm_params wm;
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u32 pixel_period;
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u32 line_time = 0;
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u32 latency_watermark_a = 0, latency_watermark_b = 0;
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u32 tmp, wm_mask;
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if (radeon_crtc->base.enabled && num_heads && mode) {
|
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pixel_period = 1000000 / (u32)mode->clock;
|
||||
line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
|
||||
|
||||
wm.yclk = rdev->pm.current_mclk * 10;
|
||||
wm.sclk = rdev->pm.current_sclk * 10;
|
||||
wm.disp_clk = mode->clock;
|
||||
wm.src_width = mode->crtc_hdisplay;
|
||||
wm.active_time = mode->crtc_hdisplay * pixel_period;
|
||||
wm.blank_time = line_time - wm.active_time;
|
||||
wm.interlaced = false;
|
||||
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
||||
wm.interlaced = true;
|
||||
wm.vsc = radeon_crtc->vsc;
|
||||
wm.vtaps = 1;
|
||||
if (radeon_crtc->rmx_type != RMX_OFF)
|
||||
wm.vtaps = 2;
|
||||
wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
|
||||
wm.lb_size = lb_size;
|
||||
wm.dram_channels = cik_get_number_of_dram_channels(rdev);
|
||||
wm.num_heads = num_heads;
|
||||
|
||||
/* set for high clocks */
|
||||
latency_watermark_a = min(dce8_latency_watermark(&wm), (u32)65535);
|
||||
/* set for low clocks */
|
||||
/* wm.yclk = low clk; wm.sclk = low clk */
|
||||
latency_watermark_b = min(dce8_latency_watermark(&wm), (u32)65535);
|
||||
|
||||
/* possibly force display priority to high */
|
||||
/* should really do this at mode validation time... */
|
||||
if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
|
||||
!dce8_average_bandwidth_vs_available_bandwidth(&wm) ||
|
||||
!dce8_check_latency_hiding(&wm) ||
|
||||
(rdev->disp_priority == 2)) {
|
||||
DRM_DEBUG_KMS("force priority to high\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* select wm A */
|
||||
wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
|
||||
tmp = wm_mask;
|
||||
tmp &= ~LATENCY_WATERMARK_MASK(3);
|
||||
tmp |= LATENCY_WATERMARK_MASK(1);
|
||||
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
|
||||
WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
|
||||
(LATENCY_LOW_WATERMARK(latency_watermark_a) |
|
||||
LATENCY_HIGH_WATERMARK(line_time)));
|
||||
/* select wm B */
|
||||
tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
|
||||
tmp &= ~LATENCY_WATERMARK_MASK(3);
|
||||
tmp |= LATENCY_WATERMARK_MASK(2);
|
||||
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
|
||||
WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
|
||||
(LATENCY_LOW_WATERMARK(latency_watermark_b) |
|
||||
LATENCY_HIGH_WATERMARK(line_time)));
|
||||
/* restore original selection */
|
||||
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* dce8_bandwidth_update - program display watermarks
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Calculate and program the display watermarks and line
|
||||
* buffer allocation (CIK).
|
||||
*/
|
||||
void dce8_bandwidth_update(struct radeon_device *rdev)
|
||||
{
|
||||
struct drm_display_mode *mode = NULL;
|
||||
u32 num_heads = 0, lb_size;
|
||||
int i;
|
||||
|
||||
radeon_update_display_priority(rdev);
|
||||
|
||||
for (i = 0; i < rdev->num_crtc; i++) {
|
||||
if (rdev->mode_info.crtcs[i]->base.enabled)
|
||||
num_heads++;
|
||||
}
|
||||
for (i = 0; i < rdev->num_crtc; i++) {
|
||||
mode = &rdev->mode_info.crtcs[i]->base.mode;
|
||||
lb_size = dce8_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode);
|
||||
dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
|
||||
}
|
||||
}
|
||||
|
||||
@ -259,6 +259,17 @@
|
||||
#define SDMA0 (1 << 10)
|
||||
#define SDMA1 (1 << 11)
|
||||
|
||||
/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
|
||||
#define LB_MEMORY_CTRL 0x6b04
|
||||
#define LB_MEMORY_SIZE(x) ((x) << 0)
|
||||
#define LB_MEMORY_CONFIG(x) ((x) << 20)
|
||||
|
||||
#define DPG_WATERMARK_MASK_CONTROL 0x6cc8
|
||||
# define LATENCY_WATERMARK_MASK(x) ((x) << 8)
|
||||
#define DPG_PIPE_LATENCY_CONTROL 0x6ccc
|
||||
# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
|
||||
# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
|
||||
|
||||
/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
|
||||
#define LB_VLINE_STATUS 0x6b24
|
||||
# define VLINE_OCCURRED (1 << 0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user