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clk: samsung: exynos4415: Move PLL rates data to init section

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The arrays with initialization data of PLLs can be moved to initconst
section because they are referenced only from other initconst-level
symbols.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Krzysztof Kozlowski 2016-05-11 14:02:03 +02:00 committed by Sylwester Nawrocki
parent ab7cc66dfa
commit ccd12b5cd6
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/samsung/clk-exynos4415.c
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@ -859,7 +859,7 @@ static const struct samsung_gate_clock exynos4415_gate_clks[] __initconst = {
/*
* APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
*/
static const struct samsung_pll_rate_table exynos4415_pll_rates[] = {
static const struct samsung_pll_rate_table exynos4415_pll_rates[] __initconst = {
PLL_35XX_RATE(1600000000, 400, 3, 1),
PLL_35XX_RATE(1500000000, 250, 2, 1),
PLL_35XX_RATE(1400000000, 175, 3, 0),
@ -891,7 +891,7 @@ static const struct samsung_pll_rate_table exynos4415_pll_rates[] = {
};
/* EPLL */
static const struct samsung_pll_rate_table exynos4415_epll_rates[] = {
static const struct samsung_pll_rate_table exynos4415_epll_rates[] __initconst = {
PLL_36XX_RATE(800000000, 200, 3, 1, 0),
PLL_36XX_RATE(288000000, 96, 2, 2, 0),
PLL_36XX_RATE(192000000, 128, 2, 3, 0),