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powerpc/8xx: Use M_TW instead of M_TWB
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires 4k aligned tables, which is only the case with 4k pages. Consequently, we have to calculate the level 1 table index by ourselves. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
LEROY Christophe
Scott Wood
parent
6cde2b6f39
commit
cbc130f120
@ -278,8 +278,8 @@ SystemCall:
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. = 0x1100
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/*
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* For the MPC8xx, this is a software tablewalk to load the instruction
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* TLB. It is modelled after the example in the Motorola manual. The task
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* switch loads the M_TWB register with the pointer to the first level table.
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* TLB. The task switch loads the M_TW register with the pointer to the first
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* level table.
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* If we discover there is no second level table (value is zero) or if there
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* is an invalid pte, we load that into the TLB, which causes another fault
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* into the TLB Error interrupt where we can handle such problems.
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@ -301,7 +301,6 @@ InstructionTLBMiss:
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#endif
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DO_8xx_CPU6(0x3780, r3)
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mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
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mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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@ -309,14 +308,17 @@ InstructionTLBMiss:
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#ifdef CONFIG_MODULES
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/* Only modules will cause ITLB Misses as we always
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* pin the first 8MB of kernel memory */
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andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
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andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
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#endif
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mfspr r11, SPRN_M_TW /* Get level 1 table base address */
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#ifdef CONFIG_MODULES
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beq 3f
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lis r11, swapper_pg_dir@h
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ori r11, r11, swapper_pg_dir@l
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rlwimi r10, r11, 0, 2, 19
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
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ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
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3:
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#endif
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lwz r11, 0(r10) /* Get the level 1 entry */
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rlwinm r10, r10, 12, 20, 29 /* Extract level 1 index */
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lwzx r11, r10, r11 /* Get the level 1 entry */
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rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
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beq 2f /* If zero, don't try to find a pte */
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@ -377,18 +379,19 @@ DataStoreTLBMiss:
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#endif
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EXCEPTION_PROLOG_0
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mtspr SPRN_SPRG_SCRATCH2, r10
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mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
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mfspr r10, SPRN_MD_EPN
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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andi. r11, r10, 0x0800
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andis. r11, r10, 0x8000
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mfspr r11, SPRN_M_TW /* Get level 1 table base address */
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beq 3f
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lis r11, swapper_pg_dir@h
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ori r11, r11, swapper_pg_dir@l
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rlwimi r10, r11, 0, 2, 19
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
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ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
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3:
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lwz r11, 0(r10) /* Get the level 1 entry */
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rlwinm r10, r10, 12, 20, 29 /* Extract level 1 index */
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lwzx r11, r10, r11 /* Get the level 1 entry */
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rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
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beq 2f /* If zero, don't try to find a pte */
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@ -527,12 +530,12 @@ FixupDAR:/* Entry point for dcbx workaround. */
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andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
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DO_8xx_CPU6(0x3780, r3)
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mtspr SPRN_MD_EPN, r10
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mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
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mfspr r11, SPRN_M_TW /* Get level 1 table base address */
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beq- 3f /* Branch if user space */
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
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ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
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rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */
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3: lwz r11, 0(r11) /* Get the level 1 entry */
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3: rlwinm r10, r10, 12, 20, 29 /* Extract level 1 index */
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lwzx r11, r10, r11 /* Get the level 1 entry */
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DO_8xx_CPU6(0x3b80, r3)
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mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
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mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
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@ -541,6 +544,7 @@ FixupDAR:/* Entry point for dcbx workaround. */
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lwz r3, 8(r0) /* restore r3 from memory */
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#endif
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/* concat physical page address(r11) and page offset(r10) */
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mfspr r10, SPRN_SRR0
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rlwimi r11, r10, 0, 20, 31
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lwz r11,0(r11)
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/* Check if it really is a dcbx instruction. */
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@ -696,11 +700,11 @@ start_here:
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#ifdef CONFIG_8xx_CPU6
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lis r4, cpu6_errata_word@h
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ori r4, r4, cpu6_errata_word@l
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li r3, 0x3980
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li r3, 0x3f80
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stw r3, 12(r4)
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lwz r3, 12(r4)
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#endif
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mtspr SPRN_M_TWB, r6
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mtspr SPRN_M_TW, r6
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lis r4,2f@h
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ori r4,r4,2f@l
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tophys(r4,r4)
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@ -874,10 +878,10 @@ _GLOBAL(set_context)
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lis r6, cpu6_errata_word@h
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ori r6, r6, cpu6_errata_word@l
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tophys (r4, r4)
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li r7, 0x3980
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li r7, 0x3f80
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stw r7, 12(r6)
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lwz r7, 12(r6)
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mtspr SPRN_M_TWB, r4 /* Update MMU base address */
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mtspr SPRN_M_TW, r4 /* Update MMU base address */
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li r7, 0x3380
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stw r7, 12(r6)
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lwz r7, 12(r6)
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@ -885,7 +889,7 @@ _GLOBAL(set_context)
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#else
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mtspr SPRN_M_CASID,r3 /* Update context */
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tophys (r4, r4)
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mtspr SPRN_M_TWB, r4 /* and pgd */
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mtspr SPRN_M_TW, r4 /* and pgd */
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#endif
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SYNC
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blr
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