mirror of
https://github.com/edk2-porting/linux-next.git
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drm/radeon/kms: add blit support for cayman (v2)
Allows us to use the 3D engine for memory management and allows us to use vram beyond the BAR aperture. v2: fix copy paste typo Reported-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
ac10f81d94
commit
cb92d452ba
@ -39,17 +39,335 @@
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const u32 cayman_default_state[] =
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{
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/* XXX fill in additional blit state */
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0xc0066900,
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0x00000000,
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0x00000060, /* DB_RENDER_CONTROL */
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0x00000000, /* DB_COUNT_CONTROL */
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0x00000000, /* DB_DEPTH_VIEW */
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0x0000002a, /* DB_RENDER_OVERRIDE */
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0x00000000, /* DB_RENDER_OVERRIDE2 */
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0x00000000, /* DB_HTILE_DATA_BASE */
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0xc0026900,
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0x00000316,
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0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
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0x00000010, /* */
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0x0000000a,
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0x00000000, /* DB_STENCIL_CLEAR */
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0x00000000, /* DB_DEPTH_CLEAR */
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0xc0036900,
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0x0000000f,
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0x00000000, /* DB_DEPTH_INFO */
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0x00000000, /* DB_Z_INFO */
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0x00000000, /* DB_STENCIL_INFO */
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0xc0016900,
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0x00000080,
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0x00000000, /* PA_SC_WINDOW_OFFSET */
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0xc00d6900,
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0x00000083,
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0x0000ffff, /* PA_SC_CLIPRECT_RULE */
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0x00000000, /* PA_SC_CLIPRECT_0_TL */
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0x20002000, /* PA_SC_CLIPRECT_0_BR */
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0x00000000,
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0x20002000,
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0x00000000,
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0x20002000,
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0x00000000,
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0x20002000,
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0xaaaaaaaa, /* PA_SC_EDGERULE */
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0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
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0x0000000f, /* CB_TARGET_MASK */
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0x0000000f, /* CB_SHADER_MASK */
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0xc0226900,
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0x00000094,
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0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
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0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x00000000, /* PA_SC_VPORT_ZMIN_0 */
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0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
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0xc0016900,
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0x000000d4,
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0x00000000, /* SX_MISC */
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0xc0026900,
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0x000000d9,
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0x00000000, /* CP_RINGID */
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0x00000000, /* CP_VMID */
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0xc0096900,
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0x00000100,
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0x00ffffff, /* VGT_MAX_VTX_INDX */
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0x00000000, /* VGT_MIN_VTX_INDX */
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0x00000000, /* VGT_INDX_OFFSET */
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0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
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0x00000000, /* SX_ALPHA_TEST_CONTROL */
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0x00000000, /* CB_BLEND_RED */
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0x00000000, /* CB_BLEND_GREEN */
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0x00000000, /* CB_BLEND_BLUE */
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0x00000000, /* CB_BLEND_ALPHA */
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0xc0016900,
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0x00000187,
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0x00000100, /* SPI_VS_OUT_ID_0 */
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0xc0026900,
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0x00000191,
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0x00000100, /* SPI_PS_INPUT_CNTL_0 */
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0x00000101, /* SPI_PS_INPUT_CNTL_1 */
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0xc0016900,
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0x000001b1,
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0x00000000, /* SPI_VS_OUT_CONFIG */
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0xc0106900,
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0x000001b3,
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0x20000001, /* SPI_PS_IN_CONTROL_0 */
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0x00000000, /* SPI_PS_IN_CONTROL_1 */
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0x00000000, /* SPI_INTERP_CONTROL_0 */
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0x00000000, /* SPI_INPUT_Z */
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0x00000000, /* SPI_FOG_CNTL */
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0x00100000, /* SPI_BARYC_CNTL */
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0x00000000, /* SPI_PS_IN_CONTROL_2 */
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0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
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0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
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0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
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0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
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0x00000000, /* SPI_GPR_MGMT */
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0x00000000, /* SPI_LDS_MGMT */
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0x00000000, /* SPI_STACK_MGMT */
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0x00000000, /* SPI_WAVE_MGMT_1 */
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0x00000000, /* SPI_WAVE_MGMT_2 */
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0xc0016900,
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0x000001e0,
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0x00000000, /* CB_BLEND0_CONTROL */
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0xc00e6900,
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0x00000200,
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0x00000000, /* DB_DEPTH_CONTROL */
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0x00000000, /* DB_EQAA */
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0x00cc0010, /* CB_COLOR_CONTROL */
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0x00000210, /* DB_SHADER_CONTROL */
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0x00010000, /* PA_CL_CLIP_CNTL */
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0x00000004, /* PA_SU_SC_MODE_CNTL */
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0x00000100, /* PA_CL_VTE_CNTL */
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0x00000000, /* PA_CL_VS_OUT_CNTL */
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0x00000000, /* PA_CL_NANINF_CNTL */
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0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
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0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
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0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
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0x00000000, /* */
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0x00000000, /* */
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0xc0026900,
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0x00000229,
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0x00000000, /* SQ_PGM_START_FS */
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0x00000000,
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0xc0016900,
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0x0000023b,
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0x00000000, /* SQ_LDS_ALLOC_PS */
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0xc0066900,
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0x00000240,
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0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xc0046900,
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0x00000247,
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0x00000000, /* SQ_GS_VERT_ITEMSIZE */
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0x00000000,
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0x00000000,
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0x00000000,
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0xc0116900,
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0x00000280,
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0x00000000, /* PA_SU_POINT_SIZE */
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0x00000000, /* PA_SU_POINT_MINMAX */
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0x00000008, /* PA_SU_LINE_CNTL */
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0x00000000, /* PA_SC_LINE_STIPPLE */
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0x00000000, /* VGT_OUTPUT_PATH_CNTL */
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0x00000000, /* VGT_HOS_CNTL */
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000, /* VGT_GS_MODE */
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0xc0026900,
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0x00000292,
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0x00000000, /* PA_SC_MODE_CNTL_0 */
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0x00000000, /* PA_SC_MODE_CNTL_1 */
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0xc0016900,
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0x000002a1,
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0x00000000, /* VGT_PRIMITIVEID_EN */
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0xc0016900,
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0x000002a5,
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0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
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0xc0026900,
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0x000002a8,
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0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
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0x00000000,
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0xc0026900,
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0x000002ad,
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0x00000000, /* VGT_REUSE_OFF */
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0x00000000,
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0xc0016900,
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0x000002d5,
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0x00000000, /* VGT_SHADER_STAGES_EN */
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0xc0016900,
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0x000002dc,
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0x0000aa00, /* DB_ALPHA_TO_MASK */
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0xc0066900,
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0x000002de,
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0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xc0026900,
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0x000002e5,
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0x00000000, /* VGT_STRMOUT_CONFIG */
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0x00000000,
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0xc01b6900,
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0x000002f5,
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0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
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0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
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0x00000000, /* PA_SC_LINE_CNTL */
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0x00000000, /* PA_SC_AA_CONFIG */
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0x00000005, /* PA_SU_VTX_CNTL */
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0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
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0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
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0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
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0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
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0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
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0xffffffff,
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0xc0026900,
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0x00000316,
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0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
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0x00000010, /* */
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};
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const u32 cayman_vs[] =
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{
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0x00000004,
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0x80400400,
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0x0000a03c,
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0x95000688,
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0x00004000,
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0x15000688,
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0x00000000,
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0x88000000,
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0x04000000,
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0x67961001,
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#ifdef __BIG_ENDIAN
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0x00020000,
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#else
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0x00000000,
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#endif
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0x00000000,
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0x04000000,
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0x67961000,
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#ifdef __BIG_ENDIAN
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0x00020008,
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#else
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0x00000008,
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#endif
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0x00000000,
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};
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const u32 cayman_ps[] =
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{
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0x00000004,
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0xa00c0000,
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0x00000008,
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0x80400000,
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0x00000000,
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0x95000688,
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0x00000000,
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0x88000000,
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0x00380400,
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0x00146b10,
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0x00380000,
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0x20146b10,
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0x00380400,
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0x40146b00,
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0x80380000,
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0x60146b00,
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0x00000010,
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0x000d1000,
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0xb0800000,
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0x00000000,
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};
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const u32 cayman_ps_size = ARRAY_SIZE(cayman_ps);
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const u32 cayman_vs_size = ARRAY_SIZE(cayman_vs);
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const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
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@ -25,8 +25,11 @@
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#ifndef CAYMAN_BLIT_SHADERS_H
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#define CAYMAN_BLIT_SHADERS_H
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extern const u32 cayman_ps[];
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extern const u32 cayman_vs[];
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extern const u32 cayman_default_state[];
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extern const u32 cayman_ps_size, cayman_vs_size;
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extern const u32 cayman_default_size;
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#endif
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@ -31,6 +31,7 @@
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#include "evergreend.h"
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#include "evergreen_blit_shaders.h"
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#include "cayman_blit_shaders.h"
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#define DI_PT_RECTLIST 0x11
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#define DI_INDEX_SIZE_16_BIT 0x0
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@ -265,6 +266,11 @@ set_default_state(struct radeon_device *rdev)
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u64 gpu_addr;
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int dwords;
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/* set clear context state */
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radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(rdev, 0);
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if (rdev->family < CHIP_CAYMAN) {
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switch (rdev->family) {
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case CHIP_CEDAR:
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default:
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@ -474,10 +480,6 @@ set_default_state(struct radeon_device *rdev)
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sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
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NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
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/* set clear context state */
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radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(rdev, 0);
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/* disable dyn gprs */
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
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@ -497,6 +499,7 @@ set_default_state(struct radeon_device *rdev)
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radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
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radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
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radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
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}
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/* CONTEXT_CONTROL */
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radeon_ring_write(rdev, 0xc0012800);
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@ -570,7 +573,10 @@ int evergreen_blit_init(struct radeon_device *rdev)
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mutex_init(&rdev->r600_blit.mutex);
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rdev->r600_blit.state_offset = 0;
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if (rdev->family < CHIP_CAYMAN)
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rdev->r600_blit.state_len = evergreen_default_size;
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else
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rdev->r600_blit.state_len = cayman_default_size;
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dwords = rdev->r600_blit.state_len;
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while (dwords & 0xf) {
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@ -582,11 +588,17 @@ int evergreen_blit_init(struct radeon_device *rdev)
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obj_size = ALIGN(obj_size, 256);
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rdev->r600_blit.vs_offset = obj_size;
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if (rdev->family < CHIP_CAYMAN)
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obj_size += evergreen_vs_size * 4;
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else
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obj_size += cayman_vs_size * 4;
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obj_size = ALIGN(obj_size, 256);
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rdev->r600_blit.ps_offset = obj_size;
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if (rdev->family < CHIP_CAYMAN)
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obj_size += evergreen_ps_size * 4;
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else
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obj_size += cayman_ps_size * 4;
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obj_size = ALIGN(obj_size, 256);
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r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
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@ -609,6 +621,7 @@ int evergreen_blit_init(struct radeon_device *rdev)
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return r;
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}
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if (rdev->family < CHIP_CAYMAN) {
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memcpy_toio(ptr + rdev->r600_blit.state_offset,
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evergreen_default_state, rdev->r600_blit.state_len * 4);
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@ -619,6 +632,18 @@ int evergreen_blit_init(struct radeon_device *rdev)
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*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
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for (i = 0; i < evergreen_ps_size; i++)
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*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
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} else {
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memcpy_toio(ptr + rdev->r600_blit.state_offset,
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cayman_default_state, rdev->r600_blit.state_len * 4);
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if (num_packet2s)
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memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
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packet2s, num_packet2s * 4);
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for (i = 0; i < cayman_vs_size; i++)
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*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
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for (i = 0; i < cayman_ps_size; i++)
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*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
|
||||
}
|
||||
radeon_bo_kunmap(rdev->r600_blit.shader_obj);
|
||||
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
||||
|
||||
|
||||
@ -1387,14 +1387,12 @@ static int cayman_startup(struct radeon_device *rdev)
|
||||
return r;
|
||||
cayman_gpu_init(rdev);
|
||||
|
||||
#if 0
|
||||
r = cayman_blit_init(rdev);
|
||||
r = evergreen_blit_init(rdev);
|
||||
if (r) {
|
||||
cayman_blit_fini(rdev);
|
||||
evergreen_blit_fini(rdev);
|
||||
rdev->asic->copy = NULL;
|
||||
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* allocate wb buffer */
|
||||
r = radeon_wb_init(rdev);
|
||||
@ -1452,7 +1450,7 @@ int cayman_resume(struct radeon_device *rdev)
|
||||
|
||||
int cayman_suspend(struct radeon_device *rdev)
|
||||
{
|
||||
/* int r; */
|
||||
int r;
|
||||
|
||||
/* FIXME: we should wait for ring to be empty */
|
||||
cayman_cp_enable(rdev, false);
|
||||
@ -1461,14 +1459,13 @@ int cayman_suspend(struct radeon_device *rdev)
|
||||
radeon_wb_disable(rdev);
|
||||
cayman_pcie_gart_disable(rdev);
|
||||
|
||||
#if 0
|
||||
/* unpin shaders bo */
|
||||
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
||||
if (likely(r == 0)) {
|
||||
radeon_bo_unpin(rdev->r600_blit.shader_obj);
|
||||
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1580,7 +1577,7 @@ int cayman_init(struct radeon_device *rdev)
|
||||
|
||||
void cayman_fini(struct radeon_device *rdev)
|
||||
{
|
||||
/* cayman_blit_fini(rdev); */
|
||||
evergreen_blit_fini(rdev);
|
||||
cayman_cp_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
radeon_wb_fini(rdev);
|
||||
|
||||
@ -906,9 +906,9 @@ static struct radeon_asic cayman_asic = {
|
||||
.get_vblank_counter = &evergreen_get_vblank_counter,
|
||||
.fence_ring_emit = &r600_fence_ring_emit,
|
||||
.cs_parse = &evergreen_cs_parse,
|
||||
.copy_blit = NULL,
|
||||
.copy_dma = NULL,
|
||||
.copy = NULL,
|
||||
.copy_blit = &evergreen_copy_blit,
|
||||
.copy_dma = &evergreen_copy_blit,
|
||||
.copy = &evergreen_copy_blit,
|
||||
.get_engine_clock = &radeon_atom_get_engine_clock,
|
||||
.set_engine_clock = &radeon_atom_set_engine_clock,
|
||||
.get_memory_clock = &radeon_atom_get_memory_clock,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user