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ixgbe: add 1g PHY support for 82599
Add support for 1G SFP+ PHY's to 82599. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -206,6 +206,14 @@ static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
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s32 status = 0;
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u32 autoc = 0;
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/* Determine 1G link capabilities off of SFP+ type */
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if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
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hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
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*speed = IXGBE_LINK_SPEED_1GB_FULL;
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*negotiation = true;
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goto out;
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}
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/*
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* Determine link capabilities based on the stored value of AUTOC,
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* which represents EEPROM defaults. If AUTOC value has not been
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@ -2087,6 +2095,7 @@ static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
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u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
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u16 ext_ability = 0;
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u8 comp_codes_10g = 0;
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u8 comp_codes_1g = 0;
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hw->phy.ops.identify(hw);
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@ -2166,12 +2175,16 @@ sfp_check:
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case ixgbe_phy_sfp_ftl:
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case ixgbe_phy_sfp_intel:
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case ixgbe_phy_sfp_unknown:
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hw->phy.ops.read_i2c_eeprom(hw,
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IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
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hw->phy.ops.read_i2c_eeprom(hw,
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IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
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if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
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physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
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else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
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physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
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else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
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physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
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break;
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default:
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break;
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@ -234,6 +234,13 @@ static int ixgbe_get_settings(struct net_device *netdev,
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case ixgbe_sfp_type_not_present:
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ecmd->port = PORT_NONE;
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break;
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case ixgbe_sfp_type_1g_cu_core0:
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case ixgbe_sfp_type_1g_cu_core1:
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ecmd->port = PORT_TP;
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ecmd->supported = SUPPORTED_TP;
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ecmd->advertising = (ADVERTISED_1000baseT_Full |
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ADVERTISED_TP);
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break;
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case ixgbe_sfp_type_unknown:
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default:
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ecmd->port = PORT_OTHER;
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@ -577,6 +577,8 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
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* 6 SFP_SR/LR_CORE1 - 82599-specific
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* 7 SFP_act_lmt_DA_CORE0 - 82599-specific
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* 8 SFP_act_lmt_DA_CORE1 - 82599-specific
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* 9 SFP_1g_cu_CORE0 - 82599-specific
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* 10 SFP_1g_cu_CORE1 - 82599-specific
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*/
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if (hw->mac.type == ixgbe_mac_82598EB) {
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if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
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@ -625,6 +627,13 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
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else
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hw->phy.sfp_type =
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ixgbe_sfp_type_srlr_core1;
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else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
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if (hw->bus.lan_id == 0)
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hw->phy.sfp_type =
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ixgbe_sfp_type_1g_cu_core0;
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else
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hw->phy.sfp_type =
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ixgbe_sfp_type_1g_cu_core1;
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else
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hw->phy.sfp_type = ixgbe_sfp_type_unknown;
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}
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@ -696,8 +705,10 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
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goto out;
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}
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/* 1G SFP modules are not supported */
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if (comp_codes_10g == 0) {
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/* Verify supported 1G SFP modules */
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if (comp_codes_10g == 0 &&
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!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
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hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
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hw->phy.type = ixgbe_phy_sfp_unsupported;
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status = IXGBE_ERR_SFP_NOT_SUPPORTED;
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goto out;
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@ -711,7 +722,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
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/* This is guaranteed to be 82599, no need to check for NULL */
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hw->mac.ops.get_device_caps(hw, &enforce_sfp);
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if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
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if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
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!((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
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(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
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/* Make sure we're a supported PHY type */
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if (hw->phy.type == ixgbe_phy_sfp_intel) {
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status = 0;
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@ -742,6 +755,7 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
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u16 *data_offset)
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{
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u16 sfp_id;
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u16 sfp_type = hw->phy.sfp_type;
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if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
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return IXGBE_ERR_SFP_NOT_SUPPORTED;
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@ -753,6 +767,17 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
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(hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
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return IXGBE_ERR_SFP_NOT_SUPPORTED;
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/*
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* Limiting active cables and 1G Phys must be initialized as
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* SR modules
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*/
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if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
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sfp_type == ixgbe_sfp_type_1g_cu_core0)
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sfp_type = ixgbe_sfp_type_srlr_core0;
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else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
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sfp_type == ixgbe_sfp_type_1g_cu_core1)
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sfp_type = ixgbe_sfp_type_srlr_core1;
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/* Read offset to PHY init contents */
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hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
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@ -769,7 +794,7 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
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hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
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while (sfp_id != IXGBE_PHY_INIT_END_NL) {
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if (sfp_id == hw->phy.sfp_type) {
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if (sfp_id == sfp_type) {
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(*list_offset)++;
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hw->eeprom.ops.read(hw, *list_offset, data_offset);
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if ((!*data_offset) || (*data_offset == 0xFFFF)) {
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@ -48,6 +48,7 @@
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#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
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#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
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#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
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#define IXGBE_SFF_1GBASET_CAPABLE 0x8
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#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
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#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
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#define IXGBE_I2C_EEPROM_READ_MASK 0x100
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@ -2214,6 +2214,8 @@ enum ixgbe_sfp_type {
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ixgbe_sfp_type_srlr_core1 = 6,
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ixgbe_sfp_type_da_act_lmt_core0 = 7,
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ixgbe_sfp_type_da_act_lmt_core1 = 8,
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ixgbe_sfp_type_1g_cu_core0 = 9,
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ixgbe_sfp_type_1g_cu_core1 = 10,
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ixgbe_sfp_type_not_present = 0xFFFE,
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ixgbe_sfp_type_unknown = 0xFFFF
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};
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