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staging: brcm80211: Add dhdsdio_chip_attach in dhd_sdio.c
dhdsdio_chip_attach and it sub functions are added for si/sb utils removal. It will replace si_attach in following patches. Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Franky Lin
Greg Kroah-Hartman
parent
ddd0b091db
commit
cb63e4c967
@ -53,6 +53,7 @@
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#include <dhdioctl.h>
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#include <sdiovar.h>
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#include <siutils_priv.h>
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#include <bcmchip.h>
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#ifndef DHDSDIO_MEM_DUMP_FNAME
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#define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
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@ -166,12 +167,28 @@ typedef struct dhd_console {
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} dhd_console_t;
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#endif /* DHD_DEBUG */
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/* misc chip info needed by some of the routines */
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struct chip_info {
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u32 chip;
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u32 chiprev;
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u32 cccorebase;
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u32 ccrev;
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u32 cccaps;
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u32 buscorebase;
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u32 buscorerev;
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u32 buscoretype;
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u32 ramcorebase;
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u32 armcorebase;
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u32 pmurev;
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};
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/* Private data for SDIO bus interaction */
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typedef struct dhd_bus {
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dhd_pub_t *dhd;
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bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
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si_t *sih; /* Handle for SI calls */
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struct chip_info *ci; /* Chip info struct */
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char *vars; /* Variables (from CIS and/or other) */
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uint varsz; /* Size of variables buffer */
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u32 sbaddr; /* Current SB window pointer (-1, invalid) */
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@ -465,6 +482,7 @@ static int dhdsdio_download_nvram(struct dhd_bus *bus);
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#ifdef BCMEMBEDIMAGE
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static int dhdsdio_download_code_array(struct dhd_bus *bus);
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#endif
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static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
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static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
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{
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@ -5289,6 +5307,10 @@ dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
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DHD_ERROR(("%s: si_attach failed!\n", __func__));
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goto fail;
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}
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if (dhdsdio_chip_attach(bus, regsva)) {
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DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
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goto fail;
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}
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bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
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@ -6071,3 +6093,234 @@ int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
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}
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return bcmerror;
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}
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static int
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dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
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{
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u32 regdata;
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/*
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* Get CC core rev
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* Chipid is assume to be at offset 0 from regs arg
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* For different chiptypes or old sdio hosts w/o chipcommon,
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* other ways of recognition should be added here.
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*/
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ci->cccorebase = (u32)regs;
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regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
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ci->chip = regdata & CID_ID_MASK;
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ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
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DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
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__func__, ci->chip, ci->chiprev));
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/* Address of cores for new chips should be added here */
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switch (ci->chip) {
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case BCM4329_CHIP_ID:
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ci->buscorebase = BCM4329_CORE_BUS_BASE;
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ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
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ci->armcorebase = BCM4329_CORE_ARM_BASE;
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break;
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default:
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DHD_ERROR(("%s: chipid 0x%x is not supported\n",
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__func__, ci->chip));
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return -ENODEV;
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}
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(ci->cccorebase, sbidhigh), 4);
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ci->ccrev = SBCOREREV(regdata);
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regdata = bcmsdh_reg_read(sdh,
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CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
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ci->pmurev = regdata & PCAP_REV_MASK;
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regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
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ci->buscorerev = SBCOREREV(regdata);
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ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
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DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
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__func__, ci->ccrev, ci->pmurev,
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ci->buscorerev, ci->buscoretype));
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/* get chipcommon capabilites */
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ci->cccaps = bcmsdh_reg_read(sdh,
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CORE_CC_REG(ci->cccorebase, capabilities), 4);
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return 0;
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}
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static void
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dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
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{
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u32 regdata;
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbtmstatelow), 4);
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if (regdata & SBTML_RESET)
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return;
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbtmstatelow), 4);
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if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
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/*
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* set target reject and spin until busy is clear
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* (preserve core-specific bits)
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*/
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbtmstatelow), 4);
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bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
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regdata | SBTML_REJ);
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbtmstatelow), 4);
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udelay(1);
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SPINWAIT((bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbtmstatehigh), 4) &
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SBTMH_BUSY), 100000);
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbtmstatehigh), 4);
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if (regdata & SBTMH_BUSY)
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DHD_ERROR(("%s: ARM core still busy\n", __func__));
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbidlow), 4);
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if (regdata & SBIDL_INIT) {
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbimstate), 4) |
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SBIM_RJ;
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bcmsdh_reg_write(sdh,
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CORE_SB(corebase, sbimstate), 4,
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regdata);
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbimstate), 4);
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udelay(1);
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SPINWAIT((bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbimstate), 4) &
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SBIM_BY), 100000);
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}
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/* set reset and reject while enabling the clocks */
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bcmsdh_reg_write(sdh,
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CORE_SB(corebase, sbtmstatelow), 4,
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(((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
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SBTML_REJ | SBTML_RESET));
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbtmstatelow), 4);
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udelay(10);
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/* clear the initiator reject bit */
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbidlow), 4);
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if (regdata & SBIDL_INIT) {
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regdata = bcmsdh_reg_read(sdh,
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CORE_SB(corebase, sbimstate), 4) &
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~SBIM_RJ;
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bcmsdh_reg_write(sdh,
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CORE_SB(corebase, sbimstate), 4,
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regdata);
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}
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}
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/* leave reset and reject asserted */
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bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
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(SBTML_REJ | SBTML_RESET));
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udelay(1);
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}
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static int
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dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
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{
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struct chip_info *ci;
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int err;
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u8 clkval, clkset;
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DHD_TRACE(("%s: Enter\n", __func__));
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/* alloc chip_info_t */
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ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
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if (NULL == ci) {
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DHD_ERROR(("%s: malloc failed!\n", __func__));
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return -ENOMEM;
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}
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memset((unsigned char *)ci, 0, sizeof(struct chip_info));
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/* bus/core/clk setup for register access */
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/* Try forcing SDIO core to do ALPAvail request only */
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clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
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bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
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clkset, &err);
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if (err) {
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DHD_ERROR(("%s: error writing for HT off\n", __func__));
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goto fail;
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}
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/* If register supported, wait for ALPAvail and then force ALP */
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/* This may take up to 15 milliseconds */
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clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
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SBSDIO_FUNC1_CHIPCLKCSR, NULL);
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if ((clkval & ~SBSDIO_AVBITS) == clkset) {
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SPINWAIT(((clkval =
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bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
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SBSDIO_FUNC1_CHIPCLKCSR,
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NULL)),
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!SBSDIO_ALPAV(clkval)),
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PMU_MAX_TRANSITION_DLY);
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if (!SBSDIO_ALPAV(clkval)) {
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DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
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__func__, clkval));
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err = -EBUSY;
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goto fail;
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}
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clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
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SBSDIO_FORCE_ALP;
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bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
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SBSDIO_FUNC1_CHIPCLKCSR,
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clkset, &err);
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udelay(65);
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} else {
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DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
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__func__, clkset, clkval));
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err = -EACCES;
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goto fail;
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}
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/* Also, disable the extra SDIO pull-ups */
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bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
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NULL);
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err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
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if (err)
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goto fail;
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/*
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* Make sure any on-chip ARM is off (in case strapping is wrong),
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* or downloaded code was already running.
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*/
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dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
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bcmsdh_reg_write(bus->sdh,
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CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
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bcmsdh_reg_write(bus->sdh,
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CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
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/* Disable F2 to clear any intermediate frame state on the dongle */
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bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
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SDIO_FUNC_ENABLE_1, NULL);
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/* WAR: cmd52 backplane read so core HW will drop ALPReq */
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clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
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0, NULL);
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/* Done with backplane-dependent accesses, can drop clock... */
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bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
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NULL);
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bus->ci = ci;
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return 0;
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fail:
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bus->ci = NULL;
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kfree(ci);
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return err;
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}
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