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iio: adc: stm32-dfsdm: move dma enable from start_conv() to start_dma()
Move DMA enable (e.g. set RDMAEN bit) away from start_conv() that is used for both buffer and single conversions. Thus, single conv rely on interrupt, not dma. Note: take care to prepare all DMA stuff and set RDMAEN before starting filter (can be set only when DFEN=0). This is precursor patch to ease support of triggered buffer mode. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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6f2c4a59d9
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caf9c1e598
@ -429,12 +429,10 @@ static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
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}
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static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
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const struct iio_chan_spec *chan,
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bool dma)
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const struct iio_chan_spec *chan)
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{
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struct regmap *regmap = adc->dfsdm->regmap;
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int ret;
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unsigned int dma_en = 0;
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ret = stm32_dfsdm_start_channel(adc->dfsdm, chan->channel);
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if (ret < 0)
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@ -444,25 +442,12 @@ static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
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if (ret < 0)
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goto stop_channels;
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if (dma) {
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/* Enable DMA transfer*/
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dma_en = DFSDM_CR1_RDMAEN(1);
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}
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/* Enable DMA transfer*/
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ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RDMAEN_MASK, dma_en);
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ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
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if (ret < 0)
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goto filter_unconfigure;
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ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
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if (ret < 0)
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goto stop_dma;
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return 0;
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stop_dma:
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regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RDMAEN_MASK, 0);
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filter_unconfigure:
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regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_CFG_MASK, 0);
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@ -479,10 +464,6 @@ static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc,
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stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
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/* Clean conversion options */
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regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RDMAEN_MASK, 0);
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regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_CFG_MASK, 0);
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@ -599,15 +580,36 @@ static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
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cookie = dmaengine_submit(desc);
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ret = dma_submit_error(cookie);
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if (ret) {
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dmaengine_terminate_all(adc->dma_chan);
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return ret;
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}
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if (ret)
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goto err_stop_dma;
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/* Issue pending DMA requests */
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dma_async_issue_pending(adc->dma_chan);
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/* Enable DMA transfer*/
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ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RDMAEN_MASK, DFSDM_CR1_RDMAEN_MASK);
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if (ret < 0)
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goto err_stop_dma;
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return 0;
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err_stop_dma:
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dmaengine_terminate_all(adc->dma_chan);
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return ret;
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}
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static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
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{
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struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
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if (!adc->dma_chan)
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return;
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regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RDMAEN_MASK, 0);
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dmaengine_terminate_all(adc->dma_chan);
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}
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static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
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@ -623,24 +625,22 @@ static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
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if (ret < 0)
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return ret;
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ret = stm32_dfsdm_start_conv(adc, chan, true);
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ret = stm32_dfsdm_adc_dma_start(indio_dev);
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if (ret) {
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dev_err(&indio_dev->dev, "Can't start conversion\n");
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dev_err(&indio_dev->dev, "Can't start DMA\n");
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goto stop_dfsdm;
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}
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if (adc->dma_chan) {
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ret = stm32_dfsdm_adc_dma_start(indio_dev);
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if (ret) {
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dev_err(&indio_dev->dev, "Can't start DMA\n");
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goto err_stop_conv;
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}
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ret = stm32_dfsdm_start_conv(adc, chan);
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if (ret) {
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dev_err(&indio_dev->dev, "Can't start conversion\n");
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goto err_stop_dma;
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}
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return 0;
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err_stop_conv:
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stm32_dfsdm_stop_conv(adc, chan);
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err_stop_dma:
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stm32_dfsdm_adc_dma_stop(indio_dev);
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stop_dfsdm:
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stm32_dfsdm_stop_dfsdm(adc->dfsdm);
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@ -652,11 +652,10 @@ static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
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struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
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const struct iio_chan_spec *chan = &indio_dev->channels[0];
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if (adc->dma_chan)
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dmaengine_terminate_all(adc->dma_chan);
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stm32_dfsdm_stop_conv(adc, chan);
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stm32_dfsdm_adc_dma_stop(indio_dev);
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stm32_dfsdm_stop_dfsdm(adc->dfsdm);
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return 0;
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@ -736,7 +735,7 @@ static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
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if (ret < 0)
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goto stop_dfsdm;
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ret = stm32_dfsdm_start_conv(adc, chan, false);
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ret = stm32_dfsdm_start_conv(adc, chan);
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if (ret < 0) {
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regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
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DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
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