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drm/radeon/si: implement get_current_sclk/mclk

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Will be used for exposing current clocks via INFO ioctl.

Tested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2014-09-30 10:50:07 -04:00
parent 1d633e3a21
commit ca1110bc5b
3 changed files with 40 additions and 0 deletions
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2
drivers/gpu/drm/radeon/radeon_asic.c
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@ -1967,6 +1967,8 @@ static struct radeon_asic si_asic = {
.fan_ctrl_get_mode = &si_fan_ctrl_get_mode, .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
.get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent, .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
.set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent, .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
.get_current_sclk = &si_dpm_get_current_sclk,
.get_current_mclk = &si_dpm_get_current_mclk,
}, },
.pflip = { .pflip = {
.page_flip = &evergreen_page_flip, .page_flip = &evergreen_page_flip,

2
drivers/gpu/drm/radeon/radeon_asic.h
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@ -756,6 +756,8 @@ int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
u32 speed); u32 speed);
u32 si_fan_ctrl_get_mode(struct radeon_device *rdev); u32 si_fan_ctrl_get_mode(struct radeon_device *rdev);
void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
u32 si_dpm_get_current_sclk(struct radeon_device *rdev);
u32 si_dpm_get_current_mclk(struct radeon_device *rdev);
/* DCE8 - CIK */ /* DCE8 - CIK */
void dce8_bandwidth_update(struct radeon_device *rdev); void dce8_bandwidth_update(struct radeon_device *rdev);

36
drivers/gpu/drm/radeon/si_dpm.c
View File

@ -6993,3 +6993,39 @@ void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
} }
} }
u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
struct radeon_ps *rps = &eg_pi->current_rps;
struct ni_ps *ps = ni_get_ps(rps);
struct rv7xx_pl *pl;
u32 current_index =
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
CURRENT_STATE_INDEX_SHIFT;
if (current_index >= ps->performance_level_count) {
return 0;
} else {
pl = &ps->performance_levels[current_index];
return pl->sclk;
}
}
u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
struct radeon_ps *rps = &eg_pi->current_rps;
struct ni_ps *ps = ni_get_ps(rps);
struct rv7xx_pl *pl;
u32 current_index =
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
CURRENT_STATE_INDEX_SHIFT;
if (current_index >= ps->performance_level_count) {
return 0;
} else {
pl = &ps->performance_levels[current_index];
return pl->mclk;
}
}