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drm/i915: convert PIPE_MSA_MISC to transcoder

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Same as the other registers. This one also appeared on Haswell for the
first time, so that's why we are renaming it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni 2012-10-23 18:30:00 -02:00 committed by Daniel Vetter
parent 702e7a56af
commit c9809791ae
2 changed files with 19 additions and 18 deletions
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19
drivers/gpu/drm/i915/i915_reg.h
View File

@ -4556,15 +4556,16 @@
#define TRANS_CLK_SEL_DISABLED (0x0<<29)
#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
#define _PIPEA_MSA_MISC 0x60410
#define _PIPEB_MSA_MISC 0x61410
#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC)
#define PIPE_MSA_SYNC_CLK (1<<0)
#define PIPE_MSA_6_BPC (0<<5)
#define PIPE_MSA_8_BPC (1<<5)
#define PIPE_MSA_10_BPC (2<<5)
#define PIPE_MSA_12_BPC (3<<5)
#define PIPE_MSA_16_BPC (4<<5)
#define _TRANSA_MSA_MISC 0x60410
#define _TRANSB_MSA_MISC 0x61410
#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
_TRANSB_MSA_MISC)
#define TRANS_MSA_SYNC_CLK (1<<0)
#define TRANS_MSA_6_BPC (0<<5)
#define TRANS_MSA_8_BPC (1<<5)
#define TRANS_MSA_10_BPC (2<<5)
#define TRANS_MSA_12_BPC (3<<5)
#define TRANS_MSA_16_BPC (4<<5)
/* LCPLL Control */
#define LCPLL_CTL 0x130040

18
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -888,32 +888,32 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum pipe pipe = intel_crtc->pipe;
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
int type = intel_encoder->type;
uint32_t temp;
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
temp = PIPE_MSA_SYNC_CLK;
temp = TRANS_MSA_SYNC_CLK;
switch (intel_crtc->bpp) {
case 18:
temp |= PIPE_MSA_6_BPC;
temp |= TRANS_MSA_6_BPC;
break;
case 24:
temp |= PIPE_MSA_8_BPC;
temp |= TRANS_MSA_8_BPC;
break;
case 30:
temp |= PIPE_MSA_10_BPC;
temp |= TRANS_MSA_10_BPC;
break;
case 36:
temp |= PIPE_MSA_12_BPC;
temp |= TRANS_MSA_12_BPC;
break;
default:
temp |= PIPE_MSA_8_BPC;
WARN(1, "%d bpp unsupported by pipe DDI function\n",
temp |= TRANS_MSA_8_BPC;
WARN(1, "%d bpp unsupported by DDI function\n",
intel_crtc->bpp);
}
I915_WRITE(PIPE_MSA_MISC(pipe), temp);
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
}