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clk: mediatek: add the option for determining PLL source clock

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Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Chen Zhong 2017-10-05 11:50:23 +08:00 committed by Stephen Boyd
parent 808ecf4ad0
commit c955bf3998
2 changed files with 5 additions and 1 deletions
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1
drivers/clk/mediatek/clk-mtk.h
View File

@ -218,6 +218,7 @@ struct mtk_pll_data {
uint32_t pcw_reg;
int pcw_shift;
const struct mtk_pll_div_table *div_table;
const char *parent_name;
};
void mtk_clk_register_plls(struct device_node *node,

5
drivers/clk/mediatek/clk-pll.c
View File

@ -312,7 +312,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
init.name = data->name;
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
init.ops = &mtk_pll_ops;
init.parent_names = &parent_name;
if (data->parent_name)
init.parent_names = &data->parent_name;
else
init.parent_names = &parent_name;
init.num_parents = 1;
clk = clk_register(NULL, &pll->hw);