mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-17 01:34:00 +08:00
i.MX drivers update for 5.1:
- Do not get GPCv2 driver depend on SOC_IMX8MQ since the driver is
going to be used on more SoCs than just i.MX8MQ.
- Add power domain information into SCU bindings document.
- Add support of start/stop a CPU into imx firmware driver.
- Support multiple address ranges per child node for imx-weim bus
driver.
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Merge tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.1:
- Do not get GPCv2 driver depend on SOC_IMX8MQ since the driver is
going to be used on more SoCs than just i.MX8MQ.
- Add power domain information into SCU bindings document.
- Add support of start/stop a CPU into imx firmware driver.
- Support multiple address ranges per child node for imx-weim bus
driver.
* tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
firmware: imx: Add support to start/stop a CPU
soc: imx: Break dependency on SOC_IMX8MQ for GPCv2
firmware: imx: scu-pd: add fallback compatible string support
dt-bindings: fsl: scu: add imx8qm scu power domain support
dt-bindings: fsl: scu: add fallback compatible string for power domain
bus: imx-weim: guard against timing configuration conflicts
bus: imx-weim: support multiple address ranges per child node
dt-bindings: bus: imx-weim: document multiple address ranges per child node
soc: imx: gpcv2: handle reset clocks
soc: imx: gpcv2: handle additional power-down bits in handshake register
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c9235d9996
@ -58,7 +58,11 @@ This binding for the SCU power domain providers uses the generic power
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domain binding[2].
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Required properties:
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- compatible: Should be "fsl,imx8qxp-scu-pd".
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- compatible: Should be one of:
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"fsl,imx8qm-scu-pd",
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"fsl,imx8qxp-scu-pd"
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followed by "fsl,scu-pd"
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- #power-domain-cells: Must be 1. Contains the Resource ID used by
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SCU commands.
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See detailed Resource ID list from:
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@ -154,7 +158,7 @@ firmware {
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};
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pd: imx8qx-pd {
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compatible = "fsl,imx8qxp-scu-pd";
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compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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};
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@ -47,9 +47,9 @@ Optional properties:
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Timing property for child nodes. It is mandatory, not optional.
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- fsl,weim-cs-timing: The timing array, contains timing values for the
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child node. We can get the CS index from the child
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node's "reg" property. The number of registers depends
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on the selected chip.
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child node. We get the CS indexes from the address
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ranges in the child node's "reg" property.
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The number of registers depends on the selected chip:
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For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
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registers: CSxU, CSxL.
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For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
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@ -80,3 +80,29 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
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0x0000c000 0x1404a38e 0x00000000>;
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};
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};
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Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
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In this case, both chip select 0 and 1 will be configured with the same timing
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array values.
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weim: weim@21b8000 {
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compatible = "fsl,imx6q-weim";
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reg = <0x021b8000 0x4000>;
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clocks = <&clks 196>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x02000000
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1 0 0x0a000000 0x02000000
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2 0 0x0c000000 0x02000000
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3 0 0x0e000000 0x02000000>;
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fsl,weim-cs-gpr = <&gpr>;
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acme@0 {
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compatible = "acme,whatever";
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reg = <0 0 0x100>, <0 0x400000 0x800>,
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<1 0x400000 0x800>;
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fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
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0x00000000 0xa0000240 0x00000000>;
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};
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};
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@ -32,6 +32,9 @@ Required properties:
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Optional properties:
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- power-supply: Power supply used to power the domain
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- clocks: a number of phandles to clocks that need to be enabled during
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domain power-up sequencing to ensure reset propagation into devices
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located inside this power domain
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Example:
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@ -46,6 +46,17 @@ static const struct imx_weim_devtype imx51_weim_devtype = {
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};
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#define MAX_CS_REGS_COUNT 6
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#define MAX_CS_COUNT 6
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#define OF_REG_SIZE 3
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struct cs_timing {
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bool is_applied;
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u32 regs[MAX_CS_REGS_COUNT];
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};
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struct cs_timing_state {
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struct cs_timing cs[MAX_CS_COUNT];
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};
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static const struct of_device_id weim_id_table[] = {
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/* i.MX1/21 */
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@ -111,21 +122,19 @@ err:
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}
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/* Parse and set the timing for this device. */
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static int __init weim_timing_setup(struct device_node *np, void __iomem *base,
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const struct imx_weim_devtype *devtype)
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static int __init weim_timing_setup(struct device *dev,
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struct device_node *np, void __iomem *base,
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const struct imx_weim_devtype *devtype,
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struct cs_timing_state *ts)
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{
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u32 cs_idx, value[MAX_CS_REGS_COUNT];
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int i, ret;
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int reg_idx, num_regs;
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struct cs_timing *cst;
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if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
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return -EINVAL;
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/* get the CS index from this child node's "reg" property. */
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ret = of_property_read_u32(np, "reg", &cs_idx);
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if (ret)
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return ret;
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if (cs_idx >= devtype->cs_count)
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if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
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return -EINVAL;
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ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
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@ -133,9 +142,43 @@ static int __init weim_timing_setup(struct device_node *np, void __iomem *base,
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if (ret)
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return ret;
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/* set the timing for WEIM */
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for (i = 0; i < devtype->cs_regs_count; i++)
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writel(value[i], base + cs_idx * devtype->cs_stride + i * 4);
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/*
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* the child node's "reg" property may contain multiple address ranges,
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* extract the chip select for each.
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*/
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num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
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if (num_regs < 0)
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return num_regs;
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if (!num_regs)
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return -EINVAL;
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for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
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/* get the CS index from this child node's "reg" property. */
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ret = of_property_read_u32_index(np, "reg",
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reg_idx * OF_REG_SIZE, &cs_idx);
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if (ret)
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break;
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if (cs_idx >= devtype->cs_count)
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return -EINVAL;
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/* prevent re-configuring a CS that's already been configured */
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cst = &ts->cs[cs_idx];
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if (cst->is_applied && memcmp(value, cst->regs,
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devtype->cs_regs_count * sizeof(u32))) {
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dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
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return -EINVAL;
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}
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/* set the timing for WEIM */
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for (i = 0; i < devtype->cs_regs_count; i++)
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writel(value[i],
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base + cs_idx * devtype->cs_stride + i * 4);
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if (!cst->is_applied) {
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cst->is_applied = true;
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memcpy(cst->regs, value,
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devtype->cs_regs_count * sizeof(u32));
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}
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}
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return 0;
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}
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@ -148,6 +191,7 @@ static int __init weim_parse_dt(struct platform_device *pdev,
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const struct imx_weim_devtype *devtype = of_id->data;
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struct device_node *child;
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int ret, have_child = 0;
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struct cs_timing_state ts = {};
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if (devtype == &imx50_weim_devtype) {
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ret = imx_weim_gpr_setup(pdev);
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@ -156,7 +200,7 @@ static int __init weim_parse_dt(struct platform_device *pdev,
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}
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for_each_available_child_of_node(pdev->dev.of_node, child) {
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ret = weim_timing_setup(child, base, devtype);
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ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
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if (ret)
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dev_warn(&pdev->dev, "%pOF set timing failed.\n",
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child);
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@ -18,6 +18,14 @@ struct imx_sc_msg_req_misc_set_ctrl {
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u16 resource;
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} __packed;
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struct imx_sc_msg_req_cpu_start {
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struct imx_sc_rpc_msg hdr;
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u32 address_hi;
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u32 address_lo;
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u16 resource;
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u8 enable;
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} __packed;
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struct imx_sc_msg_req_misc_get_ctrl {
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struct imx_sc_rpc_msg hdr;
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u32 ctrl;
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@ -97,3 +105,33 @@ int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource,
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return 0;
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}
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EXPORT_SYMBOL(imx_sc_misc_get_control);
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/*
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* This function starts/stops a CPU identified by @resource
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*
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* @param[in] ipc IPC handle
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* @param[in] resource resource the control is associated with
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* @param[in] enable true for start, false for stop
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* @param[in] phys_addr initial instruction address to be executed
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*
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* @return Returns 0 for success and < 0 for errors.
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*/
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int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource,
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bool enable, u64 phys_addr)
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{
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struct imx_sc_msg_req_cpu_start msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_PM;
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hdr->func = IMX_SC_PM_FUNC_CPU_START;
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hdr->size = 4;
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msg.address_hi = phys_addr >> 32;
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msg.address_lo = phys_addr;
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msg.resource = resource;
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msg.enable = enable;
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return imx_scu_call_rpc(ipc, &msg, true);
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}
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EXPORT_SYMBOL(imx_sc_pm_cpu_start);
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@ -322,6 +322,7 @@ static int imx_sc_pd_probe(struct platform_device *pdev)
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static const struct of_device_id imx_sc_pd_match[] = {
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{ .compatible = "fsl,imx8qxp-scu-pd", &imx8qxp_scu_pd},
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{ .compatible = "fsl,scu-pd", &imx8qxp_scu_pd},
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{ /* sentinel */ }
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};
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@ -2,7 +2,7 @@ menu "i.MX SoC drivers"
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config IMX_GPCV2_PM_DOMAINS
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bool "i.MX GPCv2 PM domains"
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depends on SOC_IMX7D || SOC_IMX8MQ || (COMPILE_TEST && OF)
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depends on ARCH_MXC || (COMPILE_TEST && OF)
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depends on PM
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select PM_GENERIC_DOMAINS
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default y if SOC_IMX7D
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@ -8,6 +8,7 @@
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* Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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@ -65,6 +66,12 @@
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#define GPC_M4_PU_PDN_FLG 0x1bc
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#define GPC_PU_PWRHSK 0x1fc
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#define IMX8M_GPU_HSK_PWRDNREQN BIT(6)
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#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
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#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
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/*
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* The PGC offset values in Reference Manual
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* (Rev. 1, 01/2018 and the older ones) GPC chapter's
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@ -92,16 +99,21 @@
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#define GPC_PGC_CTRL_PCR BIT(0)
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#define GPC_CLK_MAX 6
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struct imx_pgc_domain {
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struct generic_pm_domain genpd;
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struct regmap *regmap;
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struct regulator *regulator;
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struct clk *clk[GPC_CLK_MAX];
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int num_clks;
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unsigned int pgc;
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const struct {
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u32 pxx;
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u32 map;
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u32 hsk;
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} bits;
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const int voltage;
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@ -125,7 +137,7 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
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const bool enable_power_control = !on;
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const bool has_regulator = !IS_ERR(domain->regulator);
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unsigned long deadline;
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int ret = 0;
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int i, ret = 0;
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regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
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domain->bits.map, domain->bits.map);
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@ -138,10 +150,18 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
|
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}
|
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}
|
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|
||||
/* Enable reset clocks for all devices in the domain */
|
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for (i = 0; i < domain->num_clks; i++)
|
||||
clk_prepare_enable(domain->clk[i]);
|
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|
||||
if (enable_power_control)
|
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regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
|
||||
GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
|
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|
||||
if (domain->bits.hsk)
|
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regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
|
||||
domain->bits.hsk, on ? domain->bits.hsk : 0);
|
||||
|
||||
regmap_update_bits(domain->regmap, offset,
|
||||
domain->bits.pxx, domain->bits.pxx);
|
||||
|
||||
@ -179,6 +199,10 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
|
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regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
|
||||
GPC_PGC_CTRL_PCR, 0);
|
||||
|
||||
/* Disable reset clocks for all devices in the domain */
|
||||
for (i = 0; i < domain->num_clks; i++)
|
||||
clk_disable_unprepare(domain->clk[i]);
|
||||
|
||||
if (has_regulator && !on) {
|
||||
int err;
|
||||
|
||||
@ -328,6 +352,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
|
||||
.bits = {
|
||||
.pxx = IMX8M_GPU_SW_Pxx_REQ,
|
||||
.map = IMX8M_GPU_A53_DOMAIN,
|
||||
.hsk = IMX8M_GPU_HSK_PWRDNREQN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_GPU,
|
||||
},
|
||||
@ -339,6 +364,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
|
||||
.bits = {
|
||||
.pxx = IMX8M_VPU_SW_Pxx_REQ,
|
||||
.map = IMX8M_VPU_A53_DOMAIN,
|
||||
.hsk = IMX8M_VPU_HSK_PWRDNREQN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_VPU,
|
||||
},
|
||||
@ -350,6 +376,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
|
||||
.bits = {
|
||||
.pxx = IMX8M_DISP_SW_Pxx_REQ,
|
||||
.map = IMX8M_DISP_A53_DOMAIN,
|
||||
.hsk = IMX8M_DISP_HSK_PWRDNREQN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_DISP,
|
||||
},
|
||||
@ -390,7 +417,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
|
||||
|
||||
static const struct regmap_range imx8m_yes_ranges[] = {
|
||||
regmap_reg_range(GPC_LPCR_A_CORE_BSC,
|
||||
GPC_M4_PU_PDN_FLG),
|
||||
GPC_PU_PWRHSK),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
|
||||
GPC_PGC_SR(IMX8M_PGC_MIPI)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
|
||||
@ -426,6 +453,41 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
|
||||
.reg_access_table = &imx8m_access_table,
|
||||
};
|
||||
|
||||
static int imx_pgc_get_clocks(struct imx_pgc_domain *domain)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; ; i++) {
|
||||
struct clk *clk = of_clk_get(domain->dev->of_node, i);
|
||||
if (IS_ERR(clk))
|
||||
break;
|
||||
if (i >= GPC_CLK_MAX) {
|
||||
dev_err(domain->dev, "more than %d clocks\n",
|
||||
GPC_CLK_MAX);
|
||||
ret = -EINVAL;
|
||||
goto clk_err;
|
||||
}
|
||||
domain->clk[i] = clk;
|
||||
}
|
||||
domain->num_clks = i;
|
||||
|
||||
return 0;
|
||||
|
||||
clk_err:
|
||||
while (i--)
|
||||
clk_put(domain->clk[i]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void imx_pgc_put_clocks(struct imx_pgc_domain *domain)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = domain->num_clks - 1; i >= 0; i--)
|
||||
clk_put(domain->clk[i]);
|
||||
}
|
||||
|
||||
static int imx_pgc_domain_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct imx_pgc_domain *domain = pdev->dev.platform_data;
|
||||
@ -445,9 +507,17 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
|
||||
domain->voltage, domain->voltage);
|
||||
}
|
||||
|
||||
ret = imx_pgc_get_clocks(domain);
|
||||
if (ret) {
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(domain->dev, "Failed to get domain's clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = pm_genpd_init(&domain->genpd, NULL, true);
|
||||
if (ret) {
|
||||
dev_err(domain->dev, "Failed to init power domain\n");
|
||||
imx_pgc_put_clocks(domain);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -456,6 +526,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
|
||||
if (ret) {
|
||||
dev_err(domain->dev, "Failed to add genpd provider\n");
|
||||
pm_genpd_remove(&domain->genpd);
|
||||
imx_pgc_put_clocks(domain);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -467,6 +538,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
|
||||
|
||||
of_genpd_del_provider(domain->dev->of_node);
|
||||
pm_genpd_remove(&domain->genpd);
|
||||
imx_pgc_put_clocks(domain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -52,4 +52,7 @@ int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource,
|
||||
int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource,
|
||||
u8 ctrl, u32 *val);
|
||||
|
||||
int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource,
|
||||
bool enable, u64 phys_addr);
|
||||
|
||||
#endif /* _SC_MISC_API_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user