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ARM: mach-loki: delete
This was introduced more than 3 years ago, and since then only generic janitorial changes were made without further addition of actual support for "real" devices. This is therefore a cost with no benefits to keep in the tree. If someone wishes to revive this code, it is always possible to retrieve it from the Git repository. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> CC: Ke Wei <kewei@marvell.com> CC: Saeed Bishara <saeed@marvell.com> CC: Lennert Buytenhek <buytenh@wantstofly.org>
This commit is contained in:
Nicolas Pitre
Nicolas Pitre
parent
632b7cf6c0
commit
c8b7d43b6d
@ -490,14 +490,6 @@ config ARCH_KIRKWOOD
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Support for the following Marvell Kirkwood series SoCs:
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88F6180, 88F6192 and 88F6281.
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config ARCH_LOKI
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bool "Marvell Loki (88RC8480)"
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select CPU_FEROCEON
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select GENERIC_CLOCKEVENTS
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select PLAT_ORION
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help
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Support for the Marvell Loki (88RC8480) SoC.
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config ARCH_LPC32XX
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bool "NXP LPC32XX"
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select CLKSRC_MMIO
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@ -924,8 +916,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/mach-ks8695/Kconfig"
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source "arch/arm/mach-loki/Kconfig"
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source "arch/arm/mach-lpc32xx/Kconfig"
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source "arch/arm/mach-msm/Kconfig"
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@ -150,7 +150,6 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
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machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
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machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
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machine-$(CONFIG_ARCH_KS8695) := ks8695
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machine-$(CONFIG_ARCH_LOKI) := loki
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machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
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machine-$(CONFIG_ARCH_MMP) := mmp
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machine-$(CONFIG_ARCH_MSM) := msm
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@ -1,120 +0,0 @@
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_EXPERT=y
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CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_ARCH_LOKI=y
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CONFIG_MACH_LB88RC8480=y
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# CONFIG_CPU_FEROCEON_OLD_ID is not set
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_PREEMPT=y
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CONFIG_AEABI=y
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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# CONFIG_IPV6 is not set
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CONFIG_NET_PKTGEN=m
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_MTD=y
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CONFIG_MTD_PARTITIONS=y
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_FTL=y
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CONFIG_NFTL=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_JEDECPROBE=y
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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CONFIG_MTD_CFI_GEOMETRY=y
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CONFIG_MTD_CFI_I4=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_CFI_AMDSTD=y
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CONFIG_MTD_CFI_STAA=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_VERIFY_WRITE=y
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CONFIG_MTD_NAND_ORION=y
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CONFIG_BLK_DEV_LOOP=y
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# CONFIG_MISC_DEVICES is not set
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# CONFIG_SCSI_PROC_FS is not set
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_DEV_SR=m
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CONFIG_CHR_DEV_SG=m
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CONFIG_ATA=y
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CONFIG_SATA_MV=y
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CONFIG_NETDEVICES=y
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CONFIG_NET_ETHERNET=y
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CONFIG_MII=y
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CONFIG_MV643XX_ETH=y
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# CONFIG_NETDEV_10000 is not set
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_RUNTIME_UARTS=2
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CONFIG_LEGACY_PTY_COUNT=16
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CONFIG_I2C=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_MV64XXX=y
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CONFIG_SPI=y
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# CONFIG_HWMON is not set
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# CONFIG_VGA_CONSOLE is not set
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CONFIG_USB=y
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CONFIG_USB_DEVICEFS=y
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CONFIG_USB_PRINTER=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_STORAGE_DATAFAB=y
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CONFIG_USB_STORAGE_FREECOM=y
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CONFIG_USB_STORAGE_SDDR09=y
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CONFIG_USB_STORAGE_SDDR55=y
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CONFIG_USB_STORAGE_JUMPSHOT=y
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CONFIG_NEW_LEDS=y
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CONFIG_EXT2_FS=y
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CONFIG_EXT3_FS=y
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# CONFIG_EXT3_FS_XATTR is not set
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CONFIG_XFS_FS=y
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CONFIG_INOTIFY=y
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CONFIG_ISO9660_FS=y
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CONFIG_UDF_FS=m
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CONFIG_MSDOS_FS=y
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CONFIG_VFAT_FS=y
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CONFIG_TMPFS=y
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CONFIG_JFFS2_FS=y
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CONFIG_CRAMFS=y
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CONFIG_NFS_FS=y
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CONFIG_NFS_V3=y
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CONFIG_ROOT_NFS=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_BSD_DISKLABEL=y
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CONFIG_MINIX_SUBPARTITION=y
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CONFIG_SOLARIS_X86_PARTITION=y
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CONFIG_UNIXWARE_DISKLABEL=y
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CONFIG_LDM_PARTITION=y
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CONFIG_LDM_DEBUG=y
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CONFIG_SUN_PARTITION=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_CODEPAGE_850=y
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CONFIG_NLS_ISO8859_1=y
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CONFIG_NLS_ISO8859_2=y
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_SYSCTL_SYSCALL_CHECK=y
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CONFIG_DEBUG_USER=y
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CONFIG_CRYPTO_CBC=m
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CONFIG_CRYPTO_ECB=m
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CONFIG_CRYPTO_PCBC=m
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CONFIG_CRC_CCITT=y
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CONFIG_CRC16=y
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CONFIG_LIBCRC32C=y
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@ -1,13 +0,0 @@
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if ARCH_LOKI
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menu "Marvell Loki (88RC8480) Implementations"
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config MACH_LB88RC8480
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bool "Marvell LB88RC8480 Development Board"
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help
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Say 'Y' here if you want your kernel to support the
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Marvell LB88RC8480 Development Board.
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endmenu
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endif
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@ -1,3 +0,0 @@
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obj-y += common.o addr-map.o irq.o
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obj-$(CONFIG_MACH_LB88RC8480) += lb88rc8480-setup.o
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@ -1,3 +0,0 @@
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zreladdr-y := 0x00008000
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params_phys-y := 0x00000100
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initrd_phys-y := 0x00800000
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@ -1,122 +0,0 @@
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/*
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* arch/arm/mach-loki/addr-map.c
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*
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* Address map functions for Marvell Loki (88RC8480) SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DDR 0
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#define TARGET_DEV_BUS 1
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#define TARGET_PCIE0 3
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#define TARGET_PCIE1 4
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#define ATTR_DEV_BOOT 0x0f
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#define ATTR_DEV_CS2 0x1b
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#define ATTR_DEV_CS1 0x1d
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#define ATTR_DEV_CS0 0x1e
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#define ATTR_PCIE_IO 0x51
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#define ATTR_PCIE_MEM 0x59
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/*
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* Helpers to get DDR bank info
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*/
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#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3))
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#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3))
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/*
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* CPU Address Decode Windows registers
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*/
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#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
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#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4))
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#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4))
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#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4))
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#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c | ((n) << 4))
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struct mbus_dram_target_info loki_mbus_dram_info;
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static void __init setup_cpu_win(int win, u32 base, u32 size,
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u8 target, u8 attr, int remap)
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{
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u32 ctrl;
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base &= 0xffff0000;
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ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
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writel(base, CPU_WIN_BASE(win));
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writel(ctrl, CPU_WIN_CTRL(win));
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if (win < 2) {
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if (remap < 0)
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remap = base;
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writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
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writel(0, CPU_WIN_REMAP_HI(win));
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}
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}
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void __init loki_setup_cpu_mbus(void)
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{
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int i;
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int cs;
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/*
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* First, disable and clear windows.
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*/
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for (i = 0; i < 8; i++) {
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writel(0, CPU_WIN_BASE(i));
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writel(0, CPU_WIN_CTRL(i));
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if (i < 2) {
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writel(0, CPU_WIN_REMAP_LO(i));
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writel(0, CPU_WIN_REMAP_HI(i));
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}
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}
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/*
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* Setup windows for PCIe IO+MEM space.
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*/
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setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
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TARGET_PCIE0, ATTR_PCIE_MEM, -1);
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setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
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TARGET_PCIE1, ATTR_PCIE_MEM, -1);
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/*
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* Setup MBUS dram target info.
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*/
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loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(DDR_BASE_CS(i));
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u32 size = readl(DDR_SIZE_CS(i));
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/*
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* Chip select enabled?
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*/
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if (size & 1) {
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struct mbus_dram_window *w;
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w = &loki_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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w->base = base & 0xffff0000;
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w->size = (size | 0x0000ffff) + 1;
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}
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}
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loki_mbus_dram_info.num_cs = cs;
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}
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void __init loki_setup_dev_boot_win(u32 base, u32 size)
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{
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setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
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}
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@ -1,162 +0,0 @@
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/*
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* arch/arm/mach-loki/common.c
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*
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* Core functions for Marvell Loki (88RC8480) SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/mbus.h>
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#include <linux/dma-mapping.h>
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#include <asm/page.h>
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#include <asm/timex.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/bridge-regs.h>
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#include <mach/loki.h>
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#include <plat/orion_nand.h>
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#include <plat/time.h>
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#include <plat/common.h>
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#include "common.h"
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc loki_io_desc[] __initdata = {
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{
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.virtual = LOKI_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
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.length = LOKI_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init loki_map_io(void)
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{
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iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
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}
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/*****************************************************************************
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* GE00
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****************************************************************************/
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void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
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{
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writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
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orion_ge00_init(eth_data, &loki_mbus_dram_info,
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GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
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0, LOKI_TCLK);
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}
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/*****************************************************************************
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* GE01
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****************************************************************************/
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void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
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{
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writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
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orion_ge01_init(eth_data, &loki_mbus_dram_info,
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GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
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0, LOKI_TCLK);
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}
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/*****************************************************************************
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* SAS/SATA
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****************************************************************************/
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static struct resource loki_sas_resources[] = {
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{
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.name = "mvsas0 mem",
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.start = SAS0_PHYS_BASE,
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.end = SAS0_PHYS_BASE + 0x01ff,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "mvsas0 irq",
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.start = IRQ_LOKI_SAS_A,
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.end = IRQ_LOKI_SAS_A,
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.flags = IORESOURCE_IRQ,
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}, {
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.name = "mvsas1 mem",
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.start = SAS1_PHYS_BASE,
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.end = SAS1_PHYS_BASE + 0x01ff,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "mvsas1 irq",
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.start = IRQ_LOKI_SAS_B,
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.end = IRQ_LOKI_SAS_B,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device loki_sas = {
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.name = "mvsas",
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.id = 0,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.num_resources = ARRAY_SIZE(loki_sas_resources),
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.resource = loki_sas_resources,
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};
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void __init loki_sas_init(void)
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{
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writel(0x8300f707, DDR_REG(0x1424));
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platform_device_register(&loki_sas);
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}
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/*****************************************************************************
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* UART0
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****************************************************************************/
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void __init loki_uart0_init(void)
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{
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orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
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IRQ_LOKI_UART0, LOKI_TCLK);
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}
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/*****************************************************************************
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* UART1
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****************************************************************************/
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void __init loki_uart1_init(void)
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{
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orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
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IRQ_LOKI_UART1, LOKI_TCLK);
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}
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/*****************************************************************************
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* Time handling
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****************************************************************************/
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void __init loki_init_early(void)
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{
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orion_time_set_base(TIMER_VIRT_BASE);
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}
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static void loki_timer_init(void)
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{
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orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
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IRQ_LOKI_BRIDGE, LOKI_TCLK);
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}
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struct sys_timer loki_timer = {
|
||||
.init = loki_timer_init,
|
||||
};
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* General
|
||||
****************************************************************************/
|
||||
void __init loki_init(void)
|
||||
{
|
||||
printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
|
||||
|
||||
loki_setup_cpu_mbus();
|
||||
}
|
||||
@ -1,37 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/common.h
|
||||
*
|
||||
* Core functions for Marvell Loki (88RC8480) SoCs
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_LOKI_COMMON_H
|
||||
#define __ARCH_LOKI_COMMON_H
|
||||
|
||||
struct mv643xx_eth_platform_data;
|
||||
|
||||
/*
|
||||
* Basic Loki init functions used early by machine-setup.
|
||||
*/
|
||||
void loki_map_io(void);
|
||||
void loki_init(void);
|
||||
void loki_init_early(void);
|
||||
void loki_init_irq(void);
|
||||
|
||||
extern struct mbus_dram_target_info loki_mbus_dram_info;
|
||||
void loki_setup_cpu_mbus(void);
|
||||
void loki_setup_dev_boot_win(u32 base, u32 size);
|
||||
|
||||
void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
|
||||
void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
|
||||
void loki_sas_init(void);
|
||||
void loki_uart0_init(void);
|
||||
void loki_uart1_init(void);
|
||||
|
||||
extern struct sys_timer loki_timer;
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,28 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/bridge-regs.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_BRIDGE_REGS_H
|
||||
#define __ASM_ARCH_BRIDGE_REGS_H
|
||||
|
||||
#include <mach/loki.h>
|
||||
|
||||
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
|
||||
#define SOFT_RESET_OUT_EN 0x00000004
|
||||
|
||||
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
|
||||
#define SOFT_RESET 0x00000001
|
||||
|
||||
#define BRIDGE_INT_TIMER1_CLR 0x0004
|
||||
|
||||
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
|
||||
#define IRQ_CAUSE_OFF 0x0000
|
||||
#define IRQ_MASK_OFF 0x0004
|
||||
|
||||
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
|
||||
|
||||
#endif
|
||||
@ -1,19 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/debug-macro.S
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <mach/loki.h>
|
||||
|
||||
.macro addruart, rp, rv
|
||||
ldr \rp, =LOKI_REGS_PHYS_BASE
|
||||
ldr \rv, =LOKI_REGS_VIRT_BASE
|
||||
orr \rp, \rp, #0x00012000
|
||||
orr \rv, \rv, #0x00012000
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
@ -1,30 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <mach/bridge-regs.h>
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
.macro arch_ret_to_user, tmp1, tmp2
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
ldr \base, =IRQ_VIRT_BASE
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
|
||||
ldr \tmp, [\base, #IRQ_MASK_OFF]
|
||||
mov \irqnr, #0
|
||||
ands \irqstat, \irqstat, \tmp
|
||||
clzne \irqnr, \irqstat
|
||||
rsbne \irqnr, \irqnr, #31
|
||||
.endm
|
||||
@ -1,15 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/hardware.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include "loki.h"
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,26 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/io.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#include "loki.h"
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
static inline void __iomem *__io(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
|
||||
+ LOKI_PCIE0_IO_VIRT_BASE);
|
||||
}
|
||||
|
||||
#define __io(a) __io(a)
|
||||
#define __mem_pci(a) (a)
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,58 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/irqs.h
|
||||
*
|
||||
* IRQ definitions for Marvell Loki (88RC8480) SoCs
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IRQS_H
|
||||
#define __ASM_ARCH_IRQS_H
|
||||
|
||||
#include "loki.h" /* need GPIO_MAX */
|
||||
|
||||
/*
|
||||
* Interrupt Controller
|
||||
*/
|
||||
#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
|
||||
#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
|
||||
#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
|
||||
#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
|
||||
#define IRQ_LOKI_COM_A_ERR 6
|
||||
#define IRQ_LOKI_COM_A_IN 7
|
||||
#define IRQ_LOKI_COM_A_OUT 8
|
||||
#define IRQ_LOKI_COM_B_ERR 9
|
||||
#define IRQ_LOKI_COM_B_IN 10
|
||||
#define IRQ_LOKI_COM_B_OUT 11
|
||||
#define IRQ_LOKI_DMA_A 12
|
||||
#define IRQ_LOKI_DMA_B 13
|
||||
#define IRQ_LOKI_SAS_A 14
|
||||
#define IRQ_LOKI_SAS_B 15
|
||||
#define IRQ_LOKI_DDR 16
|
||||
#define IRQ_LOKI_XOR 17
|
||||
#define IRQ_LOKI_BRIDGE 18
|
||||
#define IRQ_LOKI_PCIE_A_ERR 20
|
||||
#define IRQ_LOKI_PCIE_A_INT 21
|
||||
#define IRQ_LOKI_PCIE_B_ERR 22
|
||||
#define IRQ_LOKI_PCIE_B_INT 23
|
||||
#define IRQ_LOKI_GBE_A_INT 24
|
||||
#define IRQ_LOKI_GBE_B_INT 25
|
||||
#define IRQ_LOKI_DEV_ERR 26
|
||||
#define IRQ_LOKI_UART0 27
|
||||
#define IRQ_LOKI_UART1 28
|
||||
#define IRQ_LOKI_TWSI 29
|
||||
#define IRQ_LOKI_GPIO_23_0 30
|
||||
#define IRQ_LOKI_GPIO_25_24 31
|
||||
|
||||
/*
|
||||
* Loki General Purpose Pins
|
||||
*/
|
||||
#define IRQ_LOKI_GPIO_START 32
|
||||
#define NR_GPIO_IRQS GPIO_MAX
|
||||
|
||||
#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,83 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/loki.h
|
||||
*
|
||||
* Generic definitions for Marvell Loki (88RC8480) SoC flavors
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_LOKI_H
|
||||
#define __ASM_ARCH_LOKI_H
|
||||
|
||||
/*
|
||||
* Marvell Loki (88RC8480) address maps.
|
||||
*
|
||||
* phys
|
||||
* d0000000 on-chip peripheral registers
|
||||
* e0000000 PCIe 0 Memory space
|
||||
* e8000000 PCIe 1 Memory space
|
||||
* f0000000 PCIe 0 I/O space
|
||||
* f0100000 PCIe 1 I/O space
|
||||
*
|
||||
* virt phys size
|
||||
* fed00000 d0000000 1M on-chip peripheral registers
|
||||
* fee00000 f0000000 64K PCIe 0 I/O space
|
||||
* fef00000 f0100000 64K PCIe 1 I/O space
|
||||
*/
|
||||
|
||||
#define LOKI_REGS_PHYS_BASE 0xd0000000
|
||||
#define LOKI_REGS_VIRT_BASE 0xfed00000
|
||||
#define LOKI_REGS_SIZE SZ_1M
|
||||
|
||||
#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
|
||||
#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
|
||||
#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
|
||||
#define LOKI_PCIE0_IO_SIZE SZ_64K
|
||||
|
||||
#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
|
||||
#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
|
||||
#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
|
||||
#define LOKI_PCIE1_IO_SIZE SZ_64K
|
||||
|
||||
#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
|
||||
#define LOKI_PCIE0_MEM_SIZE SZ_128M
|
||||
|
||||
#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
|
||||
#define LOKI_PCIE1_MEM_SIZE SZ_128M
|
||||
|
||||
/*
|
||||
* Register Map
|
||||
*/
|
||||
#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
|
||||
#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
|
||||
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
|
||||
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
|
||||
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
|
||||
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
|
||||
|
||||
#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
|
||||
|
||||
#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
|
||||
|
||||
#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
|
||||
|
||||
#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
|
||||
|
||||
#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
|
||||
|
||||
#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
|
||||
#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
|
||||
|
||||
#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
|
||||
#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
|
||||
|
||||
#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
|
||||
#define DDR_REG(x) (DDR_VIRT_BASE | (x))
|
||||
|
||||
|
||||
#define GPIO_MAX 8
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,10 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/memory.h
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
#define PLAT_PHYS_OFFSET UL(0x00000000)
|
||||
|
||||
#endif
|
||||
@ -1,36 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/system.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <mach/bridge-regs.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode, const char *cmd)
|
||||
{
|
||||
/*
|
||||
* Enable soft reset to assert RSTOUTn.
|
||||
*/
|
||||
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
|
||||
|
||||
/*
|
||||
* Assert soft reset.
|
||||
*/
|
||||
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,11 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/timex.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#define CLOCK_TICK_RATE (100 * HZ)
|
||||
|
||||
#define LOKI_TCLK 180000000
|
||||
@ -1,47 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/uncompress.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/serial_reg.h>
|
||||
#include <mach/loki.h>
|
||||
|
||||
#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
|
||||
|
||||
static void putc(const char c)
|
||||
{
|
||||
unsigned char *base = SERIAL_BASE;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 0x1000; i++) {
|
||||
if (base[UART_LSR << 2] & UART_LSR_THRE)
|
||||
break;
|
||||
barrier();
|
||||
}
|
||||
|
||||
base[UART_TX << 2] = c;
|
||||
}
|
||||
|
||||
static void flush(void)
|
||||
{
|
||||
unsigned char *base = SERIAL_BASE;
|
||||
unsigned char mask;
|
||||
int i;
|
||||
|
||||
mask = UART_LSR_TEMT | UART_LSR_THRE;
|
||||
|
||||
for (i = 0; i < 0x1000; i++) {
|
||||
if ((base[UART_LSR << 2] & mask) == mask)
|
||||
break;
|
||||
barrier();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
#define arch_decomp_wdog()
|
||||
@ -1,5 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/include/mach/vmalloc.h
|
||||
*/
|
||||
|
||||
#define VMALLOC_END 0xfe800000UL
|
||||
@ -1,22 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/irq.c
|
||||
*
|
||||
* Marvell Loki (88RC8480) IRQ handling.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
#include <plat/irq.h>
|
||||
#include "common.h"
|
||||
|
||||
void __init loki_init_irq(void)
|
||||
{
|
||||
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
|
||||
}
|
||||
@ -1,99 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-loki/lb88rc8480-setup.c
|
||||
*
|
||||
* Marvell LB88RC8480 Development Board Setup
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/ata_platform.h>
|
||||
#include <linux/mv643xx_eth.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/loki.h>
|
||||
#include "common.h"
|
||||
|
||||
#define LB88RC8480_FLASH_BOOT_CS_BASE 0xf8000000
|
||||
#define LB88RC8480_FLASH_BOOT_CS_SIZE SZ_128M
|
||||
|
||||
#define LB88RC8480_NOR_BOOT_BASE 0xff000000
|
||||
#define LB88RC8480_NOR_BOOT_SIZE SZ_16M
|
||||
|
||||
static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
|
||||
{
|
||||
.name = "kernel",
|
||||
.offset = 0,
|
||||
.size = SZ_2M,
|
||||
}, {
|
||||
.name = "root-fs",
|
||||
.offset = SZ_2M,
|
||||
.size = (SZ_8M + SZ_4M + SZ_1M),
|
||||
}, {
|
||||
.name = "u-boot",
|
||||
.offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
|
||||
.size = SZ_1M,
|
||||
},
|
||||
};
|
||||
|
||||
static struct physmap_flash_data lb88rc8480_boot_flash_data = {
|
||||
.parts = lb88rc8480_boot_flash_parts,
|
||||
.nr_parts = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
|
||||
.width = 1, /* 8 bit bus width */
|
||||
};
|
||||
|
||||
static struct resource lb88rc8480_boot_flash_resource = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = LB88RC8480_NOR_BOOT_BASE,
|
||||
.end = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
|
||||
};
|
||||
|
||||
static struct platform_device lb88rc8480_boot_flash = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &lb88rc8480_boot_flash_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &lb88rc8480_boot_flash_resource,
|
||||
};
|
||||
|
||||
static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
|
||||
.phy_addr = MV643XX_ETH_PHY_ADDR(1),
|
||||
.mac_addr = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
|
||||
};
|
||||
|
||||
static void __init lb88rc8480_init(void)
|
||||
{
|
||||
/*
|
||||
* Basic setup. Needs to be called early.
|
||||
*/
|
||||
loki_init();
|
||||
|
||||
loki_ge0_init(&lb88rc8480_ge0_data);
|
||||
loki_sas_init();
|
||||
loki_uart0_init();
|
||||
loki_uart1_init();
|
||||
|
||||
loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
|
||||
LB88RC8480_FLASH_BOOT_CS_SIZE);
|
||||
platform_device_register(&lb88rc8480_boot_flash);
|
||||
}
|
||||
|
||||
MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
|
||||
/* Maintainer: Ke Wei <kewei@marvell.com> */
|
||||
.boot_params = 0x00000100,
|
||||
.init_machine = lb88rc8480_init,
|
||||
.map_io = loki_map_io,
|
||||
.init_early = loki_init_early,
|
||||
.init_irq = loki_init_irq,
|
||||
.timer = &loki_timer,
|
||||
MACHINE_END
|
||||
Loading…
Reference in New Issue
Block a user