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ath9k_hw: Initialize mode registers for AR9485
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan
John W. Linville
parent
3050c9146b
commit
c88457eb83
@ -17,6 +17,7 @@
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#include "hw.h"
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#include "ar9003_mac.h"
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#include "ar9003_2p2_initvals.h"
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#include "ar9485_initvals.h"
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/* General hardware code for the AR9003 hadware family */
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@ -39,72 +40,134 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
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*/
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static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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{
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9300_2p2_mac_core,
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ARRAY_SIZE(ar9300_2p2_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9300_2p2_mac_postamble,
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ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
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if (AR_SREV_9485(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9485_1_0_mac_core,
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ARRAY_SIZE(ar9485_1_0_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9485_1_0_mac_postamble,
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ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9300_2p2_baseband_core,
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ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9300_2p2_baseband_postamble,
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ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
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ARRAY_SIZE(ar9485_1_0), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9485_1_0_baseband_core,
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ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9485_1_0_baseband_postamble,
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ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9300_2p2_radio_core,
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ARRAY_SIZE(ar9300_2p2_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9300_2p2_radio_postamble,
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ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9485_1_0_radio_core,
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ARRAY_SIZE(ar9485_1_0_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9485_1_0_radio_postamble,
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ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9300_2p2_soc_preamble,
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ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9300_2p2_soc_postamble,
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ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9485_1_0_soc_preamble,
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ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p2,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
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5);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9485Common_rx_gain_1_0,
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ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9485Modes_lowest_ob_db_tx_gain_1_0,
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ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
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5);
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/* Load PCIE SERDES settings from INI */
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
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ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
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2);
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
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ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
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2);
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/* Sleep Setting */
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9300PciePhy_clkreq_enable_L1_2p2,
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ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
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2);
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1,
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ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1),
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2);
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} else {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9300_2p2_mac_core,
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ARRAY_SIZE(ar9300_2p2_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9300_2p2_mac_postamble,
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ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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ar9300Modes_fast_clock_2p2,
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ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
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3);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9300_2p2_baseband_core,
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ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9300_2p2_baseband_postamble,
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ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9300_2p2_radio_core,
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ARRAY_SIZE(ar9300_2p2_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9300_2p2_radio_postamble,
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ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9300_2p2_soc_preamble,
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ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9300_2p2_soc_postamble,
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ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p2,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
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5);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
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ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
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2);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9300PciePhy_clkreq_enable_L1_2p2,
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ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
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2);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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ar9300Modes_fast_clock_2p2,
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ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
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3);
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}
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}
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static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
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