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sis5513: DMA setup fixes
* Add sis_ata133_get_base() helper function for obtaining the address of the drive control registers on chipset_family == ATA_133 chipsets. * Add three helper functions for programming PIO/MWDMA timings: - sis_ata16_program_timings() (for ATA_16/33/66/100a chipset families) - sis_ata100_program_timings() (for ATA_100/133a chipset families) - sis_ata133_program_timings() (for ATA_133 chipset family) MWDMA timings are taken from datasheets and they match ATA spec. * Add generic helper function sis_program_timings() and use it in ->set_pio_mode and ->set_dma_mode methods (previously the driver depended on BIOS to program the correct MWDMA timings). * Remove redundant !chipset_family check from init_hwif_sis5513() (init_chipset_sis5513() guarantees that we will never get here if chipset_family cannot be determined). * SWDMA seems to be unsupported by SiS chipsets (no info about SWDMA in datasheets and for SWDMA0 mode timing requirements are impossible to fulfill) so remove ->swdma_mask from init_hwif_sis5513() and handling of SWDMA modes from sis_set_dma_mode(). * Enable DMA support for chipset_family == ATA_16. * Bump driver version. Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
parent
a29ec3b219
commit
c77a89cd98
@ -1,5 +1,5 @@
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/*
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* linux/drivers/ide/pci/sis5513.c Version 0.27 Jul 14, 2007
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* linux/drivers/ide/pci/sis5513.c Version 0.28 Aug 1, 2007
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*
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* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
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@ -433,6 +433,95 @@ static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
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/*
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* Configuration functions
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*/
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static u8 sis_ata133_get_base(ide_drive_t *drive)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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u32 reg54 = 0;
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pci_read_config_dword(dev, 0x54, ®54);
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return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
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}
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static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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u16 t1 = 0;
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u8 drive_pci = 0x40 + drive->dn * 2;
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const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
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const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
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pci_read_config_word(dev, drive_pci, &t1);
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/* clear active/recovery timings */
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t1 &= ~0x070f;
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if (mode >= XFER_MW_DMA_0) {
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if (chipset_family > ATA_16)
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t1 &= ~0x8000; /* disable UDMA */
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t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
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} else
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t1 |= pio_timings[mode - XFER_PIO_0];
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pci_write_config_word(dev, drive_pci, t1);
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}
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static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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u8 t1, drive_pci = 0x40 + drive->dn * 2;
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/* timing bits: 7:4 active 3:0 recovery */
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const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
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const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
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if (mode >= XFER_MW_DMA_0) {
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u8 t2 = 0;
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pci_read_config_byte(dev, drive_pci, &t2);
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t2 &= ~0x80; /* disable UDMA */
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pci_write_config_byte(dev, drive_pci, t2);
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t1 = mwdma_timings[mode - XFER_MW_DMA_0];
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} else
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t1 = pio_timings[mode - XFER_PIO_0];
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pci_write_config_byte(dev, drive_pci + 1, t1);
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}
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static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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u32 t1 = 0;
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u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
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pci_read_config_dword(dev, drive_pci, &t1);
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t1 &= 0xc0c00fff;
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clk = (t1 & 0x08) ? ATA_133 : ATA_100;
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if (mode >= XFER_MW_DMA_0) {
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t1 &= ~0x04; /* disable UDMA */
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idx = mode - XFER_MW_DMA_0 + 5;
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}
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idx = mode - XFER_PIO_0;
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t1 |= ini_time_value[clk][idx] << 12;
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t1 |= act_time_value[clk][idx] << 16;
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t1 |= rco_time_value[clk][idx] << 24;
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pci_write_config_dword(dev, drive_pci, t1);
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}
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static void sis_program_timings(ide_drive_t *drive, const u8 mode)
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{
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if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
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sis_ata16_program_timings(drive, mode);
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else if (chipset_family < ATA_133) /* ATA_100/133a */
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sis_ata100_program_timings(drive, mode);
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else /* ATA_133 */
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sis_ata133_program_timings(drive, mode);
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}
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/* Enables per-drive prefetch and postwrite */
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static void config_drive_art_rwp (ide_drive_t *drive)
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{
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@ -450,105 +539,16 @@ static void config_drive_art_rwp (ide_drive_t *drive)
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pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
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}
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/* Set per-drive active and recovery time */
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static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 drive_pci, test1, test2;
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config_drive_art_rwp(drive);
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/* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
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drive_pci = 0x40;
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/* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
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if (chipset_family >= ATA_133) {
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u32 reg54h;
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pci_read_config_dword(dev, 0x54, ®54h);
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if (reg54h & 0x40000000) drive_pci = 0x70;
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drive_pci += ((drive->dn)*0x4);
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} else {
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drive_pci += ((drive->dn)*0x2);
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}
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/* register layout changed with newer ATA100 chips */
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if (chipset_family < ATA_100) {
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pci_read_config_byte(dev, drive_pci, &test1);
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pci_read_config_byte(dev, drive_pci+1, &test2);
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/* Clear active and recovery timings */
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test1 &= ~0x0F;
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test2 &= ~0x07;
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switch(pio) {
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case 4: test1 |= 0x01; test2 |= 0x03; break;
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case 3: test1 |= 0x03; test2 |= 0x03; break;
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case 2: test1 |= 0x04; test2 |= 0x04; break;
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case 1: test1 |= 0x07; test2 |= 0x06; break;
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case 0: /* PIO0: register setting == X000 */
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default: break;
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}
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pci_write_config_byte(dev, drive_pci, test1);
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pci_write_config_byte(dev, drive_pci+1, test2);
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} else if (chipset_family < ATA_133) {
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switch(pio) { /* active recovery
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v v */
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case 4: test1 = 0x30|0x01; break;
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case 3: test1 = 0x30|0x03; break;
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case 2: test1 = 0x40|0x04; break;
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case 1: test1 = 0x60|0x07; break;
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case 0: test1 = 0x00; break;
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default: break;
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}
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pci_write_config_byte(dev, drive_pci, test1);
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} else { /* ATA_133 */
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u32 test3;
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pci_read_config_dword(dev, drive_pci, &test3);
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test3 &= 0xc0c00fff;
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if (test3 & 0x08) {
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test3 |= ini_time_value[ATA_133][pio] << 12;
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test3 |= act_time_value[ATA_133][pio] << 16;
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test3 |= rco_time_value[ATA_133][pio] << 24;
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} else {
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test3 |= ini_time_value[ATA_100][pio] << 12;
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test3 |= act_time_value[ATA_100][pio] << 16;
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test3 |= rco_time_value[ATA_100][pio] << 24;
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}
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pci_write_config_dword(dev, drive_pci, test3);
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}
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sis_program_timings(drive, XFER_PIO_0 + pio);
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}
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static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u32 regdw;
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u8 drive_pci, reg;
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/* See sis_set_pio_mode() for drive PCI config registers */
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drive_pci = 0x40;
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if (chipset_family >= ATA_133) {
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u32 reg54h;
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pci_read_config_dword(dev, 0x54, ®54h);
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if (reg54h & 0x40000000) drive_pci = 0x70;
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drive_pci += ((drive->dn)*0x4);
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pci_read_config_dword(dev, (unsigned long)drive_pci, ®dw);
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/* Disable UDMA bit for non UDMA modes on UDMA chips */
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if (speed < XFER_UDMA_0) {
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regdw &= 0xfffffffb;
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pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
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}
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} else {
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drive_pci += ((drive->dn)*0x2);
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pci_read_config_byte(dev, drive_pci+1, ®);
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/* Disable UDMA bit for non UDMA modes on UDMA chips */
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if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
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reg &= 0x7F;
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pci_write_config_byte(dev, drive_pci+1, reg);
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}
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}
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/* Config chip for mode */
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switch(speed) {
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@ -560,6 +560,10 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
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case XFER_UDMA_1:
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case XFER_UDMA_0:
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if (chipset_family >= ATA_133) {
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u32 regdw = 0;
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u8 drive_pci = sis_ata133_get_base(drive);
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pci_read_config_dword(dev, drive_pci, ®dw);
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regdw |= 0x04;
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regdw &= 0xfffff00f;
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/* check if ATA133 enable */
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@ -572,6 +576,9 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
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}
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pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
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} else {
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u8 drive_pci = 0x40 + drive->dn * 2, reg = 0;
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pci_read_config_byte(dev, drive_pci+1, ®);
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/* Force the UDMA bit on if we want to use UDMA */
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reg |= 0x80;
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/* clean reg cycle time bits */
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@ -586,9 +593,7 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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case XFER_SW_DMA_2:
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case XFER_SW_DMA_1:
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case XFER_SW_DMA_0:
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sis_program_timings(drive, speed);
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break;
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default:
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BUG();
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@ -617,11 +622,9 @@ static int sis5513_config_xfer_rate(ide_drive_t *drive)
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static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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int drive_pci;
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u32 reg54 = 0, regdw = 0;
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u32 regdw = 0;
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u8 drive_pci = sis_ata133_get_base(drive);
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pci_read_config_dword(dev, 0x54, ®54);
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drive_pci = ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
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pci_read_config_dword(dev, drive_pci, ®dw);
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/* if ATA133 disable, we should not set speed above UDMA5 */
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@ -848,22 +851,17 @@ static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
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hwif->ultra_mask = udma_rates[chipset_family];
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hwif->mwdma_mask = 0x07;
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hwif->swdma_mask = 0x07;
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if (!chipset_family)
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return;
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if (hwif->cbl != ATA_CBL_PATA40_SHORT)
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hwif->cbl = ata66_sis5513(hwif);
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if (chipset_family > ATA_16) {
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hwif->ide_dma_check = &sis5513_config_xfer_rate;
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if (!noautodma)
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hwif->autodma = 1;
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}
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hwif->ide_dma_check = &sis5513_config_xfer_rate;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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return;
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}
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static ide_pci_device_t sis5513_chipset __devinitdata = {
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