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Exynos5433 SoC related fixes:
- addition of missing documentation and DT properties for the CMU_AUD
block source clocks,
- correction of CMU_FSYS parent clock definition,
- marking as critical clocks which have to be enabled in order
to access control registers of child CMUs.
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Merge tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Exynos5433 SoC updates from Sylwester Nawrocki:
- addition of missing documentation and DT properties for the CMU_AUD
block source clocks,
- correction of CMU_FSYS parent clock definition,
- marking as critical clocks which have to be enabled in order
to access control registers of child CMUs.
* tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung:
clk: exynos5433: Mark some clocks as critical
clk: exynos5433: Add documentation for the audio block parent clocks
clk: exynos5433: Fix parent clocks for FSYS block
This commit is contained in:
Stephen Boyd
commit
c705d22b64
@ -79,7 +79,7 @@ Required Properties:
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Input clocks for fsys clock controller:
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- oscclk
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- sclk_ufs_mphy
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- div_aclk_fsys_200
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- aclk_fsys_200
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- sclk_pcie_100_fsys
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- sclk_ufsunipro_fsys
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- sclk_mmc2_fsys
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@ -104,6 +104,10 @@ Required Properties:
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- sclk_decon_tv_vclk_disp
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- aclk_disp_333
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Input clocks for audio clock controller:
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- oscclk
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- fout_aud_pll
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Input clocks for bus0 clock controller:
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- aclk_bus0_400
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@ -235,7 +239,7 @@ Example 2: Examples of clock controller nodes are listed below.
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clock-names = "oscclk",
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"sclk_ufs_mphy",
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"div_aclk_fsys_200",
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"aclk_fsys_200",
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"sclk_pcie_100_fsys",
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"sclk_ufsunipro_fsys",
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"sclk_mmc2_fsys",
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@ -245,7 +249,7 @@ Example 2: Examples of clock controller nodes are listed below.
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"sclk_usbdrd30_fsys";
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clocks = <&xxti>,
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<&cmu_cpif CLK_SCLK_UFS_MPHY>,
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<&cmu_top CLK_DIV_ACLK_FSYS_200>,
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<&cmu_top CLK_ACLK_FSYS_200>,
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<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
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<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
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<&cmu_top CLK_SCLK_MMC2_FSYS>,
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@ -297,6 +301,9 @@ Example 2: Examples of clock controller nodes are listed below.
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compatible = "samsung,exynos5433-cmu-aud";
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reg = <0x114c0000 0x0b04>;
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#clock-cells = <1>;
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clock-names = "oscclk", "fout_aud_pll";
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clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
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};
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cmu_bus0: clock-controller@13600000 {
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@ -543,7 +543,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
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static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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/* ENABLE_ACLK_TOP */
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GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
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ENABLE_ACLK_TOP, 30, 0, 0),
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ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
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"div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
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29, CLK_IGNORE_UNUSED, 0),
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@ -555,25 +555,25 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
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ENABLE_ACLK_TOP, 24,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
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ENABLE_ACLK_TOP, 23,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
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ENABLE_ACLK_TOP, 22,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
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ENABLE_ACLK_TOP, 21,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
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ENABLE_ACLK_TOP, 19,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
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ENABLE_ACLK_TOP, 18,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
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ENABLE_ACLK_TOP, 15,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
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ENABLE_ACLK_TOP, 14,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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@ -582,7 +582,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
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ENABLE_ACLK_TOP, 12,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
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ENABLE_ACLK_TOP, 11,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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@ -591,7 +591,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
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ENABLE_ACLK_TOP, 9,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
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ENABLE_ACLK_TOP, 8,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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@ -600,19 +600,19 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
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ENABLE_ACLK_TOP, 6,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
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ENABLE_ACLK_TOP, 5,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
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ENABLE_ACLK_TOP, 3,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
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ENABLE_ACLK_TOP, 2,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
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ENABLE_ACLK_TOP, 0,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
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/* ENABLE_SCLK_TOP_MSCL */
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GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
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@ -1385,7 +1385,7 @@ static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
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ENABLE_ACLK_MIF3, 1,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
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ENABLE_ACLK_MIF3, 0,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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@ -1929,7 +1929,7 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
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/* list of all parent clock list */
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PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
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PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
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PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", };
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PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
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PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
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PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
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