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e1000e: Out of line __ew32_prepare/__ew32
Out of lining these two common inlines saves about 30k text size, due to their errata workarounds. 14131431 2008136 1507328 17646895 10d452f vmlinux-before-e1000e 14101415 2004040 1507328 17612783 10cbfef vmlinux-e1000e Signed-off-by: Andi Kleen <ak@linux.intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -575,35 +575,8 @@ static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
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#define er32(reg) __er32(hw, E1000_##reg)
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/**
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* __ew32_prepare - prepare to write to MAC CSR register on certain parts
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* @hw: pointer to the HW structure
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*
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* When updating the MAC CSR registers, the Manageability Engine (ME) could
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* be accessing the registers at the same time. Normally, this is handled in
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* h/w by an arbiter but on some parts there is a bug that acknowledges Host
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* accesses later than it should which could result in the register to have
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* an incorrect value. Workaround this by checking the FWSM register which
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* has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
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* and try again a number of times.
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**/
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static inline s32 __ew32_prepare(struct e1000_hw *hw)
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{
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s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
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while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
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udelay(50);
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return i;
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}
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static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
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{
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if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
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__ew32_prepare(hw);
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writel(val, hw->hw_addr + reg);
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}
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s32 __ew32_prepare(struct e1000_hw *hw);
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void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
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#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
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@ -123,6 +123,36 @@ static const struct e1000_reg_info e1000_reg_info_tbl[] = {
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{0, NULL}
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};
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/**
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* __ew32_prepare - prepare to write to MAC CSR register on certain parts
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* @hw: pointer to the HW structure
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*
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* When updating the MAC CSR registers, the Manageability Engine (ME) could
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* be accessing the registers at the same time. Normally, this is handled in
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* h/w by an arbiter but on some parts there is a bug that acknowledges Host
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* accesses later than it should which could result in the register to have
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* an incorrect value. Workaround this by checking the FWSM register which
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* has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
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* and try again a number of times.
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**/
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s32 __ew32_prepare(struct e1000_hw *hw)
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{
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s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
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while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
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udelay(50);
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return i;
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}
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void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
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{
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if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
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__ew32_prepare(hw);
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writel(val, hw->hw_addr + reg);
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}
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/**
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* e1000_regdump - register printout routine
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* @hw: pointer to the HW structure
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