mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-18 18:23:53 +08:00
ARM: nomadik: add the new clocks to the device tree
This revamps the device tree to fit with the new clock implementation and brings it quite a bit closer to how the hardware actually works. After this the clock implementation knows about all clock gates and will gate off all unused clocks at boot time and save a bit of power. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
ef6eb322ce
commit
c641d4dfef
@ -14,6 +14,12 @@
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bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
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};
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src@101e0000 {
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/* These chrystal drivers are not used on this board */
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disable-sxtalo;
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disable-mxtalo;
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};
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pinctrl {
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/* Hog CD pins */
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pinctrl-names = "default";
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@ -168,37 +168,464 @@
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src: src@101e0000 {
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compatible = "stericsson,nomadik-src";
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reg = <0x101e0000 0x1000>;
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clocks {
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/*
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* Dummy clock for primecells
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*/
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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/*
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* The 2.4 MHz TIMCLK reference clock is active at
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* boot time, this is actually the MXTALCLK @19.2 MHz
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* divided by 8. This clock is used by the timers and
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* watchdog. See page 105 ff.
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*/
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timclk: timclk@2.4M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <2400000>;
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};
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/*
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* At boot time, PLL2 is set to generate a set of
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* fixed clocks, one of them is CLK48, the 48 MHz
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* clock, routed to the UART, MMC/SD, I2C, IrDA,
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* USB and SSP blocks.
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*/
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clk48: clk48@48M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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};
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disable-sxtalo;
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disable-mxtalo;
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/*
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* MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
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* that is parent of TIMCLK, PLL1 and PLL2
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*/
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mxtal: mxtal@19.2M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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/*
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* The 2.4 MHz TIMCLK reference clock is active at
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* boot time, this is actually the MXTALCLK @19.2 MHz
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* divided by 8. This clock is used by the timers and
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* watchdog. See page 105 ff.
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*/
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timclk: timclk@2.4M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <8>;
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clock-mult = <1>;
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clocks = <&mxtal>;
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};
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/* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
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pll1: pll1@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-pll-clock";
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pll-id = <1>;
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clocks = <&mxtal>;
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};
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/* HCLK divides the PLL1 with 1,2,3 or 4 */
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hclk: hclk@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-hclk-clock";
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clocks = <&pll1>;
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};
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/* The PCLK domain uses HCLK right off */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&hclk>;
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};
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/* PLL2 is usually 864 MHz and divided into a few fixed rates */
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pll2: pll2@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-pll-clock";
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pll-id = <2>;
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clocks = <&mxtal>;
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};
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clk216: clk216@216M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk108: clk108@108M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&clk216>;
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};
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clk72: clk72@72M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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/* The data sheet does not say how this is derived */
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clock-div = <12>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk48: clk48@48M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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/* The data sheet does not say how this is derived */
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clock-div = <18>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk27: clk27@27M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&clk108>;
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};
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/* This apparently exists as well */
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ulpiclk: ulpiclk@60M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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/*
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* IP AMBA bus clocks, driving the bus side of the
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* peripheral clocking, clock gates.
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*/
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hclkdma0: hclkdma0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <0>;
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clocks = <&hclk>;
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};
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hclksmc: hclksmc@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <1>;
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clocks = <&hclk>;
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};
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hclksdram: hclksdram@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <2>;
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clocks = <&hclk>;
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};
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hclkdma1: hclkdma1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <3>;
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clocks = <&hclk>;
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};
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hclkclcd: hclkclcd@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <4>;
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clocks = <&hclk>;
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};
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pclkirda: pclkirda@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <5>;
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clocks = <&pclk>;
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};
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pclkssp: pclkssp@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <6>;
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clocks = <&pclk>;
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};
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pclkuart0: pclkuart0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <7>;
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clocks = <&pclk>;
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};
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pclksdi: pclksdi@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <8>;
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clocks = <&pclk>;
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};
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pclki2c0: pclki2c0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <9>;
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clocks = <&pclk>;
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};
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pclki2c1: pclki2c1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <10>;
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clocks = <&pclk>;
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};
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pclkuart1: pclkuart1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <11>;
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clocks = <&pclk>;
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};
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pclkmsp0: pclkmsp0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <12>;
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clocks = <&pclk>;
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};
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hclkusb: hclkusb@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <13>;
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clocks = <&hclk>;
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};
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hclkdif: hclkdif@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <14>;
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clocks = <&hclk>;
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};
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hclksaa: hclksaa@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <15>;
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clocks = <&hclk>;
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};
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hclksva: hclksva@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <16>;
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clocks = <&hclk>;
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};
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pclkhsi: pclkhsi@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <17>;
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clocks = <&pclk>;
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};
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pclkxti: pclkxti@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <18>;
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clocks = <&pclk>;
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};
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pclkuart2: pclkuart2@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <19>;
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clocks = <&pclk>;
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};
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pclkmsp1: pclkmsp1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <20>;
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clocks = <&pclk>;
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};
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pclkmsp2: pclkmsp2@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <21>;
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clocks = <&pclk>;
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};
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pclkowm: pclkowm@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <22>;
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clocks = <&pclk>;
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};
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hclkhpi: hclkhpi@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <23>;
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clocks = <&hclk>;
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};
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pclkske: pclkske@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <24>;
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clocks = <&pclk>;
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};
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pclkhsem: pclkhsem@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <25>;
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clocks = <&pclk>;
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};
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hclk3d: hclk3d@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <26>;
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clocks = <&hclk>;
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};
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hclkhash: hclkhash@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <27>;
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clocks = <&hclk>;
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};
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hclkcryp: hclkcryp@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <28>;
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clocks = <&hclk>;
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};
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pclkmshc: pclkmshc@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <29>;
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clocks = <&pclk>;
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};
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hclkusbm: hclkusbm@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <30>;
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clocks = <&hclk>;
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};
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hclkrng: hclkrng@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <31>;
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clocks = <&hclk>;
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};
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/* IP kernel clocks */
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clcdclk: clcdclk@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <36>;
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clocks = <&clk72 &clk48>;
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};
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irdaclk: irdaclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <37>;
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clocks = <&clk48>;
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};
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sspiclk: sspiclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <38>;
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clocks = <&clk48>;
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};
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uart0clk: uart0clk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <39>;
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clocks = <&clk48>;
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};
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sdiclk: sdiclk@48M {
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/* Also called MCCLK in some documents */
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <40>;
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clocks = <&clk48>;
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};
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i2c0clk: i2c0clk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <41>;
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clocks = <&clk48>;
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};
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i2c1clk: i2c1clk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <42>;
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clocks = <&clk48>;
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};
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uart1clk: uart1clk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <43>;
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clocks = <&clk48>;
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};
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mspclk0: mspclk0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <44>;
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clocks = <&clk48>;
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};
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usbclk: usbclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <45>;
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clocks = <&clk48>; /* 48 MHz not ULPI */
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};
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difclk: difclk@72M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <46>;
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clocks = <&clk72>;
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};
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ipi2cclk: ipi2cclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <47>;
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clocks = <&clk48>; /* Guess */
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};
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ipbmcclk: ipbmcclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <48>;
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clocks = <&clk48>; /* Guess */
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};
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hsiclkrx: hsiclkrx@216M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <49>;
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clocks = <&clk216>;
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};
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hsiclktx: hsiclktx@108M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <50>;
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clocks = <&clk108>;
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};
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uart2clk: uart2clk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <51>;
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clocks = <&clk48>;
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};
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mspclk1: mspclk1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <52>;
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clocks = <&clk48>;
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};
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mspclk2: mspclk2@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <53>;
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clocks = <&clk48>;
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};
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owmclk: owmclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <54>;
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clocks = <&clk48>; /* Guess */
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};
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skeclk: skeclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <56>;
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clocks = <&clk48>; /* Guess */
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};
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x3dclk: x3dclk@48M {
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||||
#clock-cells = <0>;
|
||||
compatible = "st,nomadik-src-clock";
|
||||
clock-id = <58>;
|
||||
clocks = <&clk48>; /* Guess */
|
||||
};
|
||||
pclkmsp3: pclkmsp3@48M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,nomadik-src-clock";
|
||||
clock-id = <59>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
mspclk3: mspclk3@48M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,nomadik-src-clock";
|
||||
clock-id = <60>;
|
||||
clocks = <&clk48>;
|
||||
};
|
||||
mshcclk: mshcclk@48M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,nomadik-src-clock";
|
||||
clock-id = <61>;
|
||||
clocks = <&clk48>; /* Guess */
|
||||
};
|
||||
usbmclk: usbmclk@48M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,nomadik-src-clock";
|
||||
clock-id = <62>;
|
||||
/* Stated as "48 MHz not ULPI clock" */
|
||||
clocks = <&clk48>;
|
||||
};
|
||||
rngcclk: rngcclk@48M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,nomadik-src-clock";
|
||||
clock-id = <63>;
|
||||
clocks = <&clk48>; /* Guess */
|
||||
};
|
||||
};
|
||||
|
||||
@ -212,7 +639,7 @@
|
||||
<0x41000000 0x2000>, /* NAND Base ADDR */
|
||||
<0x40800000 0x2000>; /* NAND Base CMD */
|
||||
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
|
||||
clocks = <&pclk>;
|
||||
clocks = <&hclksmc>;
|
||||
status = "okay";
|
||||
|
||||
partition@0 {
|
||||
@ -334,7 +761,7 @@
|
||||
reg = <0x101fd000 0x1000>;
|
||||
interrupt-parent = <&vica>;
|
||||
interrupts = <12>;
|
||||
clocks = <&clk48>, <&pclk>;
|
||||
clocks = <&uart0clk>, <&pclkuart0>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_default_mux>;
|
||||
@ -345,7 +772,7 @@
|
||||
reg = <0x101fb000 0x1000>;
|
||||
interrupt-parent = <&vica>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clk48>, <&pclk>;
|
||||
clocks = <&uart1clk>, <&pclkuart1>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_default_mux>;
|
||||
@ -356,7 +783,7 @@
|
||||
reg = <0x101f2000 0x1000>;
|
||||
interrupt-parent = <&vica>;
|
||||
interrupts = <28>;
|
||||
clocks = <&clk48>, <&pclk>;
|
||||
clocks = <&uart2clk>, <&pclkuart2>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -364,7 +791,7 @@
|
||||
rng: rng@101b0000 {
|
||||
compatible = "arm,primecell";
|
||||
reg = <0x101b0000 0x1000>;
|
||||
clocks = <&clk48>, <&pclk>;
|
||||
clocks = <&rngcclk>, <&hclkrng>;
|
||||
clock-names = "rng", "apb_pclk";
|
||||
};
|
||||
|
||||
@ -380,7 +807,7 @@
|
||||
mmcsd: sdi@101f6000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x101f6000 0x1000>;
|
||||
clocks = <&clk48>, <&pclk>;
|
||||
clocks = <&sdiclk>, <&pclksdi>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
interrupt-parent = <&vica>;
|
||||
interrupts = <22>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user