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ARM: dts: uniphier: Add PCIe endpoint and PHY node for Pro5

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This adds PCIe endpoint controller and PHY nodes for Pro5 SoC,
and also adds pinctrl node for PCIe.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Kunihiko Hayashi 2020-07-08 17:52:00 +09:00 committed by Masahiro Yamada
parent 656d648268
commit c60a5cee6e
2 changed files with 35 additions and 0 deletions
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5
arch/arm/boot/dts/uniphier-pinctrl.dtsi
View File

@ -126,6 +126,11 @@
function = "nand";
};
pinctrl_pcie: pcie {
groups = "pcie";
function = "pcie";
};
pinctrl_sd: sd {
groups = "sd";
function = "sd";

30
arch/arm/boot/dts/uniphier-pro5.dtsi
View File

@ -613,6 +613,36 @@
};
};
pcie_ep: pcie-ep@66000000 {
compatible = "socionext,uniphier-pro5-pcie-ep",
"snps,dw-pcie-ep";
status = "disabled";
reg-names = "dbi", "dbi2", "link", "addr_space";
reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
<0x66010000 0x10000>, <0x67000000 0x400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 24>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 24>;
num-ib-windows = <16>;
num-ob-windows = <16>;
num-lanes = <4>;
phy-names = "pcie-phy";
phys = <&pcie_phy>;
};
pcie_phy: phy@66038000 {
compatible = "socionext,uniphier-pro5-pcie-phy";
reg = <0x66038000 0x4000>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 24>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 24>;
};
nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";