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ARM: dts: imx: add device tree support for Freescale imx50evk board

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Add device tree support for the Freescale IMX50EVk board based around the
IMX50 SoC. Supports UART, SPI flash, FEC ethernet and USB on this board.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Greg Ungerer 2013-10-29 15:15:57 +10:00 committed by Shawn Guo
parent 64972acd61
commit c605cbf5e1
2 changed files with 120 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@ -143,6 +143,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx27-phytec-phycard-s-som.dtb \
imx27-phytec-phycard-s-rdk.dtb \
imx31-bug.dtb \
imx50-evk.dtb \
imx51-apf51.dtb \
imx51-apf51dev.dtb \
imx51-babbage.dtb \

119
arch/arm/boot/dts/imx50-evk.dts Normal file
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@ -0,0 +1,119 @@
/*
* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx50.dtsi"
/ {
model = "Freescale i.MX50 Evaluation Kit";
compatible = "fsl,imx50-evk", "fsl,imx50";
memory {
reg = <0x70000000 0x80000000>;
};
};
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
status = "okay";
flash: m25p32@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p32", "m25p80";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "kernel";
reg = <0x100000 0x300000>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 12 0>;
status = "okay";
};
&iomuxc {
imx50-evk {
pinctrl_cspi: cspigrp {
fsl,pins = <
MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX50_PAD_SSI_RXFS__FEC_MDC 0x80
MX50_PAD_SSI_RXC__FEC_MDIO 0x80
MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
MX50_PAD_DISP_D2__FEC_RX_DV 0x80
MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
MX50_PAD_DISP_D5__FEC_TX_EN 0x80
MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbh2 {
status = "okay";
};
&usbh3 {
status = "okay";
};
&usbotg {
status = "okay";
};