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powerpc/powernv: Dynamically release PE
This supports releasing PEs dynamically. A reference count is introduced to PE representing number of PCI devices associated with the PE. The reference count is increased when PCI device joins the PE and decreased when PCI device leaves the PE in pnv_pci_release_device(). When the count becomes zero, the PE and its consumed resources are released. Note that the count is accessed concurrently. So a counter with "int" type is enough here. In order to release the sources consumed by the PE, couple of helper functions are introduced as below: * pnv_pci_ioda1_unset_window() - Unset IODA1 DMA32 window * pnv_pci_ioda1_release_dma_pe() - Release IODA1 DMA32 segments * pnv_pci_ioda2_release_dma_pe() - Release IODA2 DMA resource * pnv_ioda_release_pe_seg() - Unmap IO/M32/M64 segments Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Gavin Shan
Michael Ellerman
parent
93e01a5039
commit
c5f7700bbd
@ -1033,6 +1033,7 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
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if (pdn->pe_number != IODA_INVALID_PE)
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continue;
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pe->device_count++;
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pdn->pcidev = dev;
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pdn->pe_number = pe->pe_number;
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if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
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@ -3394,6 +3395,178 @@ static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
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return true;
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}
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static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
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int num)
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{
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struct pnv_ioda_pe *pe = container_of(table_group,
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struct pnv_ioda_pe, table_group);
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struct pnv_phb *phb = pe->phb;
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unsigned int idx;
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long rc;
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pe_info(pe, "Removing DMA window #%d\n", num);
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for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
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if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
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continue;
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rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
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idx, 0, 0ul, 0ul, 0ul);
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if (rc != OPAL_SUCCESS) {
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pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
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rc, idx);
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return rc;
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}
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phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
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}
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pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
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return OPAL_SUCCESS;
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}
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static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
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{
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unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
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struct iommu_table *tbl = pe->table_group.tables[0];
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int64_t rc;
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if (!weight)
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return;
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rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
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if (rc != OPAL_SUCCESS)
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return;
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pnv_pci_ioda1_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
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if (pe->table_group.group) {
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iommu_group_put(pe->table_group.group);
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WARN_ON(pe->table_group.group);
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}
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free_pages(tbl->it_base, get_order(tbl->it_size << 3));
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iommu_free_table(tbl, "pnv");
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}
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static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
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{
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struct iommu_table *tbl = pe->table_group.tables[0];
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unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
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#ifdef CONFIG_IOMMU_API
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int64_t rc;
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#endif
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if (!weight)
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return;
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#ifdef CONFIG_IOMMU_API
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rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
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if (rc)
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pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
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#endif
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pnv_pci_ioda2_set_bypass(pe, false);
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if (pe->table_group.group) {
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iommu_group_put(pe->table_group.group);
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WARN_ON(pe->table_group.group);
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}
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pnv_pci_ioda2_table_free_pages(tbl);
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iommu_free_table(tbl, "pnv");
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}
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static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
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unsigned short win,
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unsigned int *map)
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{
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struct pnv_phb *phb = pe->phb;
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int idx;
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int64_t rc;
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for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
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if (map[idx] != pe->pe_number)
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continue;
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if (win == OPAL_M64_WINDOW_TYPE)
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rc = opal_pci_map_pe_mmio_window(phb->opal_id,
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phb->ioda.reserved_pe_idx, win,
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idx / PNV_IODA1_M64_SEGS,
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idx % PNV_IODA1_M64_SEGS);
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else
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rc = opal_pci_map_pe_mmio_window(phb->opal_id,
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phb->ioda.reserved_pe_idx, win, 0, idx);
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if (rc != OPAL_SUCCESS)
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pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
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rc, win, idx);
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map[idx] = IODA_INVALID_PE;
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}
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}
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static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
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{
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struct pnv_phb *phb = pe->phb;
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if (phb->type == PNV_PHB_IODA1) {
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pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
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phb->ioda.io_segmap);
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pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
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phb->ioda.m32_segmap);
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pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
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phb->ioda.m64_segmap);
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} else if (phb->type == PNV_PHB_IODA2) {
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pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
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phb->ioda.m32_segmap);
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}
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}
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static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
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{
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struct pnv_phb *phb = pe->phb;
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struct pnv_ioda_pe *slave, *tmp;
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/* Release slave PEs in compound PE */
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if (pe->flags & PNV_IODA_PE_MASTER) {
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list_for_each_entry_safe(slave, tmp, &pe->slaves, list)
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pnv_ioda_release_pe(slave);
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}
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list_del(&pe->list);
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switch (phb->type) {
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case PNV_PHB_IODA1:
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pnv_pci_ioda1_release_pe_dma(pe);
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break;
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case PNV_PHB_IODA2:
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pnv_pci_ioda2_release_pe_dma(pe);
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break;
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default:
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WARN_ON(1);
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}
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pnv_ioda_release_pe_seg(pe);
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pnv_ioda_deconfigure_pe(pe->phb, pe);
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pnv_ioda_free_pe(pe);
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}
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static void pnv_pci_release_device(struct pci_dev *pdev)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct pci_dn *pdn = pci_get_pdn(pdev);
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struct pnv_ioda_pe *pe;
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if (pdev->is_virtfn)
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return;
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if (!pdn || pdn->pe_number == IODA_INVALID_PE)
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return;
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pe = &phb->ioda.pe_array[pdn->pe_number];
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WARN_ON(--pe->device_count < 0);
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if (pe->device_count == 0)
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pnv_ioda_release_pe(pe);
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}
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static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
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{
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struct pnv_phb *phb = hose->private_data;
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@ -3410,6 +3583,7 @@ static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
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.teardown_msi_irqs = pnv_teardown_msi_irqs,
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#endif
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.enable_device_hook = pnv_pci_enable_device_hook,
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.release_device = pnv_pci_release_device,
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.window_alignment = pnv_pci_window_alignment,
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.setup_bridge = pnv_pci_setup_bridge,
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.reset_secondary_bus = pnv_pci_reset_secondary_bus,
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@ -30,6 +30,7 @@ struct pnv_phb;
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struct pnv_ioda_pe {
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unsigned long flags;
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struct pnv_phb *phb;
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int device_count;
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/* A PE can be associated with a single device or an
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* entire bus (& children). In the former case, pdev
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