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spi: Add driver for Cadence SPI controller
Add driver for Cadence SPI controller. This is used in Xilinx Zynq. Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
parent
c9eaa447e7
commit
c474b38665
@ -148,6 +148,13 @@ config SPI_BUTTERFLY
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inexpensive battery powered microcontroller evaluation board.
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This same cable can be used to flash new firmware.
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config SPI_CADENCE
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tristate "Cadence SPI controller"
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depends on SPI_MASTER
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help
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This selects the Cadence SPI controller master driver
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used by Xilinx Zynq.
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config SPI_CLPS711X
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tristate "CLPS711X host SPI controller"
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depends on ARCH_CLPS711X || COMPILE_TEST
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@ -22,6 +22,7 @@ obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o
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obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
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obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
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obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o
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obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
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obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
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obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
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673
drivers/spi/spi-cadence.c
Normal file
673
drivers/spi/spi-cadence.c
Normal file
@ -0,0 +1,673 @@
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/*
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* Cadence SPI controller driver (master mode only)
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*
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* Copyright (C) 2008 - 2014 Xilinx, Inc.
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*
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* based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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/* Name of this driver */
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#define CDNS_SPI_NAME "cdns-spi"
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/* Register offset definitions */
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#define CDNS_SPI_CR_OFFSET 0x00 /* Configuration Register, RW */
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#define CDNS_SPI_ISR_OFFSET 0x04 /* Interrupt Status Register, RO */
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#define CDNS_SPI_IER_OFFSET 0x08 /* Interrupt Enable Register, WO */
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#define CDNS_SPI_IDR_OFFSET 0x0c /* Interrupt Disable Register, WO */
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#define CDNS_SPI_IMR_OFFSET 0x10 /* Interrupt Enabled Mask Register, RO */
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#define CDNS_SPI_ER_OFFSET 0x14 /* Enable/Disable Register, RW */
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#define CDNS_SPI_DR_OFFSET 0x18 /* Delay Register, RW */
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#define CDNS_SPI_TXD_OFFSET 0x1C /* Data Transmit Register, WO */
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#define CDNS_SPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
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#define CDNS_SPI_SICR_OFFSET 0x24 /* Slave Idle Count Register, RW */
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#define CDNS_SPI_THLD_OFFSET 0x28 /* Transmit FIFO Watermark Register,RW */
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/*
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* SPI Configuration Register bit Masks
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*
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* This register contains various control bits that affect the operation
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* of the SPI controller
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*/
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#define CDNS_SPI_CR_MANSTRT_MASK 0x00010000 /* Manual TX Start */
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#define CDNS_SPI_CR_CPHA_MASK 0x00000004 /* Clock Phase Control */
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#define CDNS_SPI_CR_CPOL_MASK 0x00000002 /* Clock Polarity Control */
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#define CDNS_SPI_CR_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */
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#define CDNS_SPI_CR_BAUD_DIV_MASK 0x00000038 /* Baud Rate Divisor Mask */
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#define CDNS_SPI_CR_MSTREN_MASK 0x00000001 /* Master Enable Mask */
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#define CDNS_SPI_CR_MANSTRTEN_MASK 0x00008000 /* Manual TX Enable Mask */
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#define CDNS_SPI_CR_SSFORCE_MASK 0x00004000 /* Manual SS Enable Mask */
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#define CDNS_SPI_CR_BAUD_DIV_4_MASK 0x00000008 /* Default Baud Div Mask */
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#define CDNS_SPI_CR_DEFAULT_MASK (CDNS_SPI_CR_MSTREN_MASK | \
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CDNS_SPI_CR_SSCTRL_MASK | \
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CDNS_SPI_CR_SSFORCE_MASK | \
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CDNS_SPI_CR_BAUD_DIV_4_MASK)
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/*
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* SPI Configuration Register - Baud rate and slave select
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*
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* These are the values used in the calculation of baud rate divisor and
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* setting the slave select.
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*/
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#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
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#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
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#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
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#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
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#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
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/*
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* SPI Interrupt Registers bit Masks
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*
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* All the four interrupt registers (Status/Mask/Enable/Disable) have the same
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* bit definitions.
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*/
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#define CDNS_SPI_IXR_TXOW_MASK 0x00000004 /* SPI TX FIFO Overwater */
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#define CDNS_SPI_IXR_MODF_MASK 0x00000002 /* SPI Mode Fault */
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#define CDNS_SPI_IXR_RXNEMTY_MASK 0x00000010 /* SPI RX FIFO Not Empty */
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#define CDNS_SPI_IXR_DEFAULT_MASK (CDNS_SPI_IXR_TXOW_MASK | \
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CDNS_SPI_IXR_MODF_MASK)
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#define CDNS_SPI_IXR_TXFULL_MASK 0x00000008 /* SPI TX Full */
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#define CDNS_SPI_IXR_ALL_MASK 0x0000007F /* SPI all interrupts */
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/*
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* SPI Enable Register bit Masks
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*
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* This register is used to enable or disable the SPI controller
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*/
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#define CDNS_SPI_ER_ENABLE_MASK 0x00000001 /* SPI Enable Bit Mask */
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#define CDNS_SPI_ER_DISABLE_MASK 0x0 /* SPI Disable Bit Mask */
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/* SPI FIFO depth in bytes */
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#define CDNS_SPI_FIFO_DEPTH 128
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/* Default number of chip select lines */
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#define CDNS_SPI_DEFAULT_NUM_CS 4
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/**
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* struct cdns_spi - This definition defines spi driver instance
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* @regs: Virtual address of the SPI controller registers
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* @ref_clk: Pointer to the peripheral clock
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* @pclk: Pointer to the APB clock
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* @speed_hz: Current SPI bus clock speed in Hz
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* @txbuf: Pointer to the TX buffer
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* @rxbuf: Pointer to the RX buffer
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* @tx_bytes: Number of bytes left to transfer
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* @rx_bytes: Number of bytes requested
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* @dev_busy: Device busy flag
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* @is_decoded_cs: Flag for decoder property set or not
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*/
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struct cdns_spi {
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void __iomem *regs;
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struct clk *ref_clk;
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struct clk *pclk;
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u32 speed_hz;
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const u8 *txbuf;
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u8 *rxbuf;
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int tx_bytes;
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int rx_bytes;
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u8 dev_busy;
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u32 is_decoded_cs;
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};
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/* Macros for the SPI controller read/write */
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static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
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{
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return readl_relaxed(xspi->regs + offset);
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}
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static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
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{
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writel_relaxed(val, xspi->regs + offset);
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}
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/**
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* cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
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* @xspi: Pointer to the cdns_spi structure
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*
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* On reset the SPI controller is configured to be in master mode, baud rate
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* divisor is set to 4, threshold value for TX FIFO not full interrupt is set
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* to 1 and size of the word to be transferred as 8 bit.
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* This function initializes the SPI controller to disable and clear all the
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* interrupts, enable manual slave select and manual start, deselect all the
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* chip select lines, and enable the SPI controller.
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*/
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static void cdns_spi_init_hw(struct cdns_spi *xspi)
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{
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cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
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CDNS_SPI_ER_DISABLE_MASK);
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cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
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CDNS_SPI_IXR_ALL_MASK);
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/* Clear the RX FIFO */
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while (cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET) &
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CDNS_SPI_IXR_RXNEMTY_MASK)
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cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET);
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cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET,
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CDNS_SPI_IXR_ALL_MASK);
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cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET,
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CDNS_SPI_CR_DEFAULT_MASK);
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cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
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CDNS_SPI_ER_ENABLE_MASK);
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}
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/**
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* cdns_spi_chipselect - Select or deselect the chip select line
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* @spi: Pointer to the spi_device structure
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* @is_on: Select(0) or deselect (1) the chip select line
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*/
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static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
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{
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struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
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u32 ctrl_reg;
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ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
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if (is_high) {
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/* Deselect the slave */
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ctrl_reg |= CDNS_SPI_CR_SSCTRL_MASK;
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} else {
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/* Select the slave */
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ctrl_reg &= ~CDNS_SPI_CR_SSCTRL_MASK;
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if (!(xspi->is_decoded_cs))
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ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
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CDNS_SPI_SS_SHIFT) &
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CDNS_SPI_CR_SSCTRL_MASK;
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else
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ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
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CDNS_SPI_CR_SSCTRL_MASK;
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}
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cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
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}
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/**
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* cdns_spi_config_clock_mode - Sets clock polarity and phase
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* @spi: Pointer to the spi_device structure
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*
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* Sets the requested clock polarity and phase.
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*/
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static void cdns_spi_config_clock_mode(struct spi_device *spi)
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{
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struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
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u32 ctrl_reg;
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ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
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/* Set the SPI clock phase and clock polarity */
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ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK);
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if (spi->mode & SPI_CPHA)
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ctrl_reg |= CDNS_SPI_CR_CPHA_MASK;
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if (spi->mode & SPI_CPOL)
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ctrl_reg |= CDNS_SPI_CR_CPOL_MASK;
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cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
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}
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/**
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* cdns_spi_config_clock_freq - Sets clock frequency
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* @spi: Pointer to the spi_device structure
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* @transfer: Pointer to the spi_transfer structure which provides
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* information about next transfer setup parameters
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*
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* Sets the requested clock frequency.
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* Note: If the requested frequency is not an exact match with what can be
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* obtained using the prescalar value the driver sets the clock frequency which
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* is lower than the requested frequency (maximum lower) for the transfer. If
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* the requested frequency is higher or lower than that is supported by the SPI
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* controller the driver will set the highest or lowest frequency supported by
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* controller.
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*/
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static void cdns_spi_config_clock_freq(struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
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u32 ctrl_reg, baud_rate_val;
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unsigned long frequency;
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frequency = clk_get_rate(xspi->ref_clk);
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ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
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/* Set the clock frequency */
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if (xspi->speed_hz != transfer->speed_hz) {
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/* first valid value is 1 */
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baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
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while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
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(frequency / (2 << baud_rate_val)) > transfer->speed_hz)
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baud_rate_val++;
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ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV_MASK;
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ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
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xspi->speed_hz = frequency / (2 << baud_rate_val);
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}
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cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
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}
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/**
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* cdns_spi_setup_transfer - Configure SPI controller for specified transfer
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* @spi: Pointer to the spi_device structure
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* @transfer: Pointer to the spi_transfer structure which provides
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* information about next transfer setup parameters
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*
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* Sets the operational mode of SPI controller for the next SPI transfer and
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* sets the requested clock frequency.
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*
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* Return: Always 0
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*/
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static int cdns_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
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cdns_spi_config_clock_freq(spi, transfer);
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dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
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__func__, spi->mode, spi->bits_per_word,
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xspi->speed_hz);
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return 0;
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}
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/**
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* cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
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* @xspi: Pointer to the cdns_spi structure
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*/
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static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
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{
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unsigned long trans_cnt = 0;
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while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
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(xspi->tx_bytes > 0)) {
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if (xspi->txbuf)
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cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET,
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*xspi->txbuf++);
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else
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cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET, 0);
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xspi->tx_bytes--;
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trans_cnt++;
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}
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}
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/**
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* cdns_spi_irq - Interrupt service routine of the SPI controller
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* @irq: IRQ number
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* @dev_id: Pointer to the xspi structure
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*
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* This function handles TX empty and Mode Fault interrupts only.
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* On TX empty interrupt this function reads the received data from RX FIFO and
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* fills the TX FIFO if there is any data remaining to be transferred.
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* On Mode Fault interrupt this function indicates that transfer is completed,
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* the SPI subsystem will identify the error as the remaining bytes to be
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* transferred is non-zero.
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*
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* Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
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*/
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static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct cdns_spi *xspi = spi_master_get_devdata(master);
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u32 intr_status, status;
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status = IRQ_NONE;
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intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET);
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cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, intr_status);
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if (intr_status & CDNS_SPI_IXR_MODF_MASK) {
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/* Indicate that transfer is completed, the SPI subsystem will
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* identify the error as the remaining bytes to be
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* transferred is non-zero
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*/
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cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
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CDNS_SPI_IXR_DEFAULT_MASK);
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spi_finalize_current_transfer(master);
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status = IRQ_HANDLED;
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} else if (intr_status & CDNS_SPI_IXR_TXOW_MASK) {
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unsigned long trans_cnt;
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trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
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/* Read out the data from the RX FIFO */
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while (trans_cnt) {
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u8 data;
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data = cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET);
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if (xspi->rxbuf)
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*xspi->rxbuf++ = data;
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xspi->rx_bytes--;
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trans_cnt--;
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}
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if (xspi->tx_bytes) {
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/* There is more data to send */
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cdns_spi_fill_tx_fifo(xspi);
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} else {
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/* Transfer is completed */
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cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
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CDNS_SPI_IXR_DEFAULT_MASK);
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spi_finalize_current_transfer(master);
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}
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status = IRQ_HANDLED;
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}
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return status;
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}
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/**
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* cdns_transfer_one - Initiates the SPI transfer
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* @master: Pointer to spi_master structure
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* @spi: Pointer to the spi_device structure
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* @transfer: Pointer to the spi_transfer structure which provides
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* information about next transfer parameters
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*
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* This function fills the TX FIFO, starts the SPI transfer and
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* returns a positive transfer count so that core will wait for completion.
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*
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* Return: Number of bytes transferred in the last transfer
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*/
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static int cdns_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct cdns_spi *xspi = spi_master_get_devdata(master);
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xspi->txbuf = transfer->tx_buf;
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xspi->rxbuf = transfer->rx_buf;
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xspi->tx_bytes = transfer->len;
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xspi->rx_bytes = transfer->len;
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||||
cdns_spi_setup_transfer(spi, transfer);
|
||||
|
||||
cdns_spi_fill_tx_fifo(xspi);
|
||||
|
||||
cdns_spi_write(xspi, CDNS_SPI_IER_OFFSET,
|
||||
CDNS_SPI_IXR_DEFAULT_MASK);
|
||||
return transfer->len;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdns_prepare_transfer_hardware - Prepares hardware for transfer.
|
||||
* @master: Pointer to the spi_master structure which provides
|
||||
* information about the controller.
|
||||
*
|
||||
* This function enables SPI master controller.
|
||||
*
|
||||
* Return: 0 always
|
||||
*/
|
||||
static int cdns_prepare_transfer_hardware(struct spi_master *master)
|
||||
{
|
||||
struct cdns_spi *xspi = spi_master_get_devdata(master);
|
||||
|
||||
cdns_spi_config_clock_mode(master->cur_msg->spi);
|
||||
|
||||
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
|
||||
CDNS_SPI_ER_ENABLE_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
|
||||
* @master: Pointer to the spi_master structure which provides
|
||||
* information about the controller.
|
||||
*
|
||||
* This function disables the SPI master controller.
|
||||
*
|
||||
* Return: 0 always
|
||||
*/
|
||||
static int cdns_unprepare_transfer_hardware(struct spi_master *master)
|
||||
{
|
||||
struct cdns_spi *xspi = spi_master_get_devdata(master);
|
||||
|
||||
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
|
||||
CDNS_SPI_ER_DISABLE_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdns_spi_probe - Probe method for the SPI driver
|
||||
* @pdev: Pointer to the platform_device structure
|
||||
*
|
||||
* This function initializes the driver data structures and the hardware.
|
||||
*
|
||||
* Return: 0 on success and error value on error
|
||||
*/
|
||||
static int cdns_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret = 0, irq;
|
||||
struct spi_master *master;
|
||||
struct cdns_spi *xspi;
|
||||
struct resource *res;
|
||||
u32 num_cs;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
|
||||
if (master == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
xspi = spi_master_get_devdata(master);
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
xspi->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(xspi->regs)) {
|
||||
ret = PTR_ERR(xspi->regs);
|
||||
goto remove_master;
|
||||
}
|
||||
|
||||
xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
|
||||
if (IS_ERR(xspi->pclk)) {
|
||||
dev_err(&pdev->dev, "pclk clock not found.\n");
|
||||
ret = PTR_ERR(xspi->pclk);
|
||||
goto remove_master;
|
||||
}
|
||||
|
||||
xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
|
||||
if (IS_ERR(xspi->ref_clk)) {
|
||||
dev_err(&pdev->dev, "ref_clk clock not found.\n");
|
||||
ret = PTR_ERR(xspi->ref_clk);
|
||||
goto remove_master;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(xspi->pclk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Unable to enable APB clock.\n");
|
||||
goto remove_master;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(xspi->ref_clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Unable to enable device clock.\n");
|
||||
goto clk_dis_apb;
|
||||
}
|
||||
|
||||
/* SPI controller initializations */
|
||||
cdns_spi_init_hw(xspi);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq <= 0) {
|
||||
ret = -ENXIO;
|
||||
dev_err(&pdev->dev, "irq number is invalid\n");
|
||||
goto remove_master;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
|
||||
0, pdev->name, master);
|
||||
if (ret != 0) {
|
||||
ret = -ENXIO;
|
||||
dev_err(&pdev->dev, "request_irq failed\n");
|
||||
goto remove_master;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
|
||||
|
||||
if (ret < 0)
|
||||
master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
|
||||
else
|
||||
master->num_chipselect = num_cs;
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
|
||||
&xspi->is_decoded_cs);
|
||||
|
||||
if (ret < 0)
|
||||
xspi->is_decoded_cs = 0;
|
||||
|
||||
master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
|
||||
master->transfer_one = cdns_transfer_one;
|
||||
master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
|
||||
master->set_cs = cdns_spi_chipselect;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
||||
|
||||
/* Set to default valid value */
|
||||
master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
|
||||
xspi->speed_hz = master->max_speed_hz;
|
||||
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
|
||||
ret = spi_register_master(master);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "spi_register_master failed\n");
|
||||
goto clk_dis_all;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
clk_dis_all:
|
||||
clk_disable_unprepare(xspi->ref_clk);
|
||||
clk_dis_apb:
|
||||
clk_disable_unprepare(xspi->pclk);
|
||||
remove_master:
|
||||
spi_master_put(master);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdns_spi_remove - Remove method for the SPI driver
|
||||
* @pdev: Pointer to the platform_device structure
|
||||
*
|
||||
* This function is called if a device is physically removed from the system or
|
||||
* if the driver module is being unloaded. It frees all resources allocated to
|
||||
* the device.
|
||||
*
|
||||
* Return: 0 on success and error value on error
|
||||
*/
|
||||
static int cdns_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct cdns_spi *xspi = spi_master_get_devdata(master);
|
||||
|
||||
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
|
||||
CDNS_SPI_ER_DISABLE_MASK);
|
||||
|
||||
clk_disable_unprepare(xspi->ref_clk);
|
||||
clk_disable_unprepare(xspi->pclk);
|
||||
|
||||
spi_unregister_master(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdns_spi_suspend - Suspend method for the SPI driver
|
||||
* @dev: Address of the platform_device structure
|
||||
*
|
||||
* This function disables the SPI controller and
|
||||
* changes the driver state to "suspend"
|
||||
*
|
||||
* Return: Always 0
|
||||
*/
|
||||
static int __maybe_unused cdns_spi_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = container_of(dev,
|
||||
struct platform_device, dev);
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct cdns_spi *xspi = spi_master_get_devdata(master);
|
||||
|
||||
spi_master_suspend(master);
|
||||
|
||||
clk_disable_unprepare(xspi->ref_clk);
|
||||
|
||||
clk_disable_unprepare(xspi->pclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdns_spi_resume - Resume method for the SPI driver
|
||||
* @dev: Address of the platform_device structure
|
||||
*
|
||||
* This function changes the driver state to "ready"
|
||||
*
|
||||
* Return: 0 on success and error value on error
|
||||
*/
|
||||
static int __maybe_unused cdns_spi_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = container_of(dev,
|
||||
struct platform_device, dev);
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct cdns_spi *xspi = spi_master_get_devdata(master);
|
||||
int ret = 0;
|
||||
|
||||
ret = clk_prepare_enable(xspi->pclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot enable APB clock.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(xspi->ref_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot enable device clock.\n");
|
||||
clk_disable(xspi->pclk);
|
||||
return ret;
|
||||
}
|
||||
spi_master_resume(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend,
|
||||
cdns_spi_resume);
|
||||
|
||||
static struct of_device_id cdns_spi_of_match[] = {
|
||||
{ .compatible = "xlnx,zynq-spi-r1p6" },
|
||||
{ .compatible = "cdns,spi-r1p6" },
|
||||
{ /* end of table */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
|
||||
|
||||
/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
|
||||
static struct platform_driver cdns_spi_driver = {
|
||||
.probe = cdns_spi_probe,
|
||||
.remove = cdns_spi_remove,
|
||||
.driver = {
|
||||
.name = CDNS_SPI_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = cdns_spi_of_match,
|
||||
.pm = &cdns_spi_dev_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(cdns_spi_driver);
|
||||
|
||||
MODULE_AUTHOR("Xilinx, Inc.");
|
||||
MODULE_DESCRIPTION("Cadence SPI driver");
|
||||
MODULE_LICENSE("GPL");
|
Loading…
Reference in New Issue
Block a user