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interconnect changes for 5.15
Here are changes for the 5.15-rc1 merge window consisting of interconnect core and driver updates. Framework change: - Add sanity check to detect if node is already added to provider. Driver changes: - RPMh drivers probe function consolidation - Add driver for SC8180x platforms - Add support for SC8180x OSM L3 - Use driver-specific naming in OSM L3 Signed-off-by: Georgi Djakov <djakov@kernel.org> -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJhI7tWAAoJEIDQzArG2BZjRWsQAIPaOLOBYGN7+aGLI0MO4aRx u5P7i5QD/EJzSQ6z+MtNkzwgDV4+D6EzWxA2eyIPtHQsbpmift+qdWBVHPZcRFkD sKV+B0NqJZSJe2W/RQ8u66yKaj931nbiSfxvCdpCB/Vamrfip8Bv7IO0hRsmFsSe ji+UFg7SnCyou1C461visnl7+yGVwDB6e5BS7aXTYJ/3gl5lJ7IGooCwXs6w/EsS FBBrvBqGU3ez61y6SYKrTQTI9MQEcioIUULXa0z8OGdAIqjfY3lWOIk6bhJTYFj8 snjowrGxMP+K7JzR9KgktB/eCivzYAdyMJKJrd6z1sPUS6vrAOLd0OZdHKVF87si 8s1ed6gUTkEK62Eg1OL1dIL3D6Ivf+UgGolz98hFqr2IxI/WRLGQ5oeuSHefiE8U Rni13/vCNeM82mYIxk4e5VScM1PWPUdSPJl/40TgKELt7XvxKTPc0FO2u6mc+nRl vsMJpnnVFszas0I40g0eIspWI4NYnukOFARP+2AXTpVuAylbf4YLkKSiwG1MN5TV LdralsxcRLvp2ot9IliqmXjam+QJILK7GBpIqWe0jbo6ND4fGcd5ZN48pGmWxot6 mrNMXfq7cUbsG0aWrHIUZ8bISUEBlBBqqTSzKqVT4RtSZ8862lvQEHx5j72sQLj/ EYGoCI2F7tqFzs5P+qqm =K/bk -----END PGP SIGNATURE----- Merge tag 'icc-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next Georgi writes: interconnect changes for 5.15 Here are changes for the 5.15-rc1 merge window consisting of interconnect core and driver updates. Framework change: - Add sanity check to detect if node is already added to provider. Driver changes: - RPMh drivers probe function consolidation - Add driver for SC8180x platforms - Add support for SC8180x OSM L3 - Use driver-specific naming in OSM L3 Signed-off-by: Georgi Djakov <djakov@kernel.org> * tag 'icc-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc: interconnect: qcom: osm-l3: Use driver-specific naming interconnect: qcom: osm-l3: Add sc8180x support dt-bindings: interconnect: Add SC8180x to OSM L3 DT binding interconnect: qcom: Add SC8180x providers dt-bindings: interconnect: Add Qualcomm SC8180x DT bindings interconnect: Sanity check that node isn't already on list interconnect: qcom: icc-rpmh: Consolidate probe functions
This commit is contained in:
commit
c446e40ed3
@ -18,6 +18,7 @@ properties:
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compatible:
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compatible:
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enum:
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enum:
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- qcom,sc7180-osm-l3
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- qcom,sc7180-osm-l3
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- qcom,sc8180x-osm-l3
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- qcom,sdm845-osm-l3
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- qcom,sdm845-osm-l3
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- qcom,sm8150-osm-l3
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- qcom,sm8150-osm-l3
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- qcom,sm8250-epss-l3
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- qcom,sm8250-epss-l3
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@ -49,6 +49,17 @@ properties:
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- qcom,sc7280-mmss-noc
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- qcom,sc7280-mmss-noc
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- qcom,sc7280-nsp-noc
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- qcom,sc7280-nsp-noc
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- qcom,sc7280-system-noc
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- qcom,sc7280-system-noc
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- qcom,sc8180x-aggre1-noc
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- qcom,sc8180x-aggre2-noc
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- qcom,sc8180x-camnoc-virt
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- qcom,sc8180x-compute-noc
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- qcom,sc8180x-config-noc
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- qcom,sc8180x-dc-noc
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- qcom,sc8180x-gem-noc
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- qcom,sc8180x-ipa-virt
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- qcom,sc8180x-mc-virt
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- qcom,sc8180x-mmss-noc
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- qcom,sc8180x-system-noc
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- qcom,sdm845-aggre1-noc
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- qcom,sdm845-aggre1-noc
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- qcom,sdm845-aggre2-noc
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- qcom,sdm845-aggre2-noc
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- qcom,sdm845-config-noc
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- qcom,sdm845-config-noc
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@ -959,6 +959,9 @@ EXPORT_SYMBOL_GPL(icc_link_destroy);
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*/
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*/
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void icc_node_add(struct icc_node *node, struct icc_provider *provider)
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void icc_node_add(struct icc_node *node, struct icc_provider *provider)
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{
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{
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if (WARN_ON(node->provider))
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return;
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mutex_lock(&icc_lock);
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mutex_lock(&icc_lock);
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node->provider = provider;
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node->provider = provider;
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@ -83,6 +83,15 @@ config INTERCONNECT_QCOM_SC7280
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This is a driver for the Qualcomm Network-on-Chip on sc7280-based
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This is a driver for the Qualcomm Network-on-Chip on sc7280-based
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platforms.
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platforms.
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config INTERCONNECT_QCOM_SC8180X
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tristate "Qualcomm SC8180X interconnect driver"
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depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
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select INTERCONNECT_QCOM_RPMH
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select INTERCONNECT_QCOM_BCM_VOTER
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help
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This is a driver for the Qualcomm Network-on-Chip on sc8180x-based
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platforms.
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config INTERCONNECT_QCOM_SDM660
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config INTERCONNECT_QCOM_SDM660
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tristate "Qualcomm SDM660 interconnect driver"
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tristate "Qualcomm SDM660 interconnect driver"
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depends on INTERCONNECT_QCOM
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depends on INTERCONNECT_QCOM
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@ -9,6 +9,7 @@ qnoc-qcs404-objs := qcs404.o
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icc-rpmh-obj := icc-rpmh.o
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icc-rpmh-obj := icc-rpmh.o
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qnoc-sc7180-objs := sc7180.o
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qnoc-sc7180-objs := sc7180.o
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qnoc-sc7280-objs := sc7280.o
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qnoc-sc7280-objs := sc7280.o
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qnoc-sc8180x-objs := sc8180x.o
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qnoc-sdm660-objs := sdm660.o
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qnoc-sdm660-objs := sdm660.o
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qnoc-sdm845-objs := sdm845.o
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qnoc-sdm845-objs := sdm845.o
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qnoc-sdx55-objs := sdx55.o
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qnoc-sdx55-objs := sdx55.o
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@ -26,6 +27,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
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obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
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obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
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@ -7,6 +7,7 @@
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#include <linux/interconnect-provider.h>
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#include <linux/interconnect-provider.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include "bcm-voter.h"
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#include "bcm-voter.h"
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@ -182,4 +183,96 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
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}
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}
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EXPORT_SYMBOL_GPL(qcom_icc_bcm_init);
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EXPORT_SYMBOL_GPL(qcom_icc_bcm_init);
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int qcom_icc_rpmh_probe(struct platform_device *pdev)
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{
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const struct qcom_icc_desc *desc;
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struct device *dev = &pdev->dev;
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struct icc_onecell_data *data;
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struct icc_provider *provider;
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struct qcom_icc_node **qnodes, *qn;
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struct qcom_icc_provider *qp;
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struct icc_node *node;
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size_t num_nodes, i, j;
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int ret;
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desc = of_device_get_match_data(dev);
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if (!desc)
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return -EINVAL;
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qnodes = desc->nodes;
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num_nodes = desc->num_nodes;
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qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
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if (!qp)
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return -ENOMEM;
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data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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provider = &qp->provider;
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provider->dev = dev;
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provider->set = qcom_icc_set;
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provider->pre_aggregate = qcom_icc_pre_aggregate;
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provider->aggregate = qcom_icc_aggregate;
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provider->xlate_extended = qcom_icc_xlate_extended;
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INIT_LIST_HEAD(&provider->nodes);
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provider->data = data;
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qp->dev = dev;
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qp->bcms = desc->bcms;
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qp->num_bcms = desc->num_bcms;
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qp->voter = of_bcm_voter_get(qp->dev, NULL);
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if (IS_ERR(qp->voter))
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return PTR_ERR(qp->voter);
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ret = icc_provider_add(provider);
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if (ret)
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return ret;
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for (i = 0; i < qp->num_bcms; i++)
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qcom_icc_bcm_init(qp->bcms[i], dev);
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for (i = 0; i < num_nodes; i++) {
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qn = qnodes[i];
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if (!qn)
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continue;
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node = icc_node_create(qn->id);
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if (IS_ERR(node)) {
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ret = PTR_ERR(node);
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goto err;
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}
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node->name = qn->name;
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node->data = qn;
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icc_node_add(node, provider);
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for (j = 0; j < qn->num_links; j++)
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icc_link_create(node, qn->links[j]);
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data->nodes[i] = node;
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}
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data->num_nodes = num_nodes;
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platform_set_drvdata(pdev, qp);
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return 0;
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err:
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icc_nodes_remove(provider);
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icc_provider_del(provider);
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return ret;
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}
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EXPORT_SYMBOL_GPL(qcom_icc_rpmh_probe);
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int qcom_icc_rpmh_remove(struct platform_device *pdev)
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{
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struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
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icc_nodes_remove(&qp->provider);
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return icc_provider_del(&qp->provider);
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}
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EXPORT_SYMBOL_GPL(qcom_icc_rpmh_remove);
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MODULE_LICENSE("GPL v2");
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MODULE_LICENSE("GPL v2");
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@ -134,5 +134,7 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst);
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struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data);
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struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data);
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int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev);
|
int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev);
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void qcom_icc_pre_aggregate(struct icc_node *node);
|
void qcom_icc_pre_aggregate(struct icc_node *node);
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||||||
|
int qcom_icc_rpmh_probe(struct platform_device *pdev);
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|
int qcom_icc_rpmh_remove(struct platform_device *pdev);
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|
|
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#endif
|
#endif
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|
@ -15,6 +15,7 @@
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
|
#include <dt-bindings/interconnect/qcom,osm-l3.h>
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||||||
|
|
||||||
#include "sc7180.h"
|
#include "sc7180.h"
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||||||
|
#include "sc8180x.h"
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||||||
#include "sdm845.h"
|
#include "sdm845.h"
|
||||||
#include "sm8150.h"
|
#include "sm8150.h"
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#include "sm8250.h"
|
#include "sm8250.h"
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@ -37,7 +38,7 @@
|
|||||||
|
|
||||||
#define OSM_L3_MAX_LINKS 1
|
#define OSM_L3_MAX_LINKS 1
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||||||
|
|
||||||
#define to_qcom_provider(_provider) \
|
#define to_osm_l3_provider(_provider) \
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container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
|
container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
|
||||||
|
|
||||||
struct qcom_osm_l3_icc_provider {
|
struct qcom_osm_l3_icc_provider {
|
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@ -49,14 +50,14 @@ struct qcom_osm_l3_icc_provider {
|
|||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct qcom_icc_node - Qualcomm specific interconnect nodes
|
* struct qcom_osm_l3_node - Qualcomm specific interconnect nodes
|
||||||
* @name: the node name used in debugfs
|
* @name: the node name used in debugfs
|
||||||
* @links: an array of nodes where we can go next while traversing
|
* @links: an array of nodes where we can go next while traversing
|
||||||
* @id: a unique node identifier
|
* @id: a unique node identifier
|
||||||
* @num_links: the total number of @links
|
* @num_links: the total number of @links
|
||||||
* @buswidth: width of the interconnect between a node and the bus
|
* @buswidth: width of the interconnect between a node and the bus
|
||||||
*/
|
*/
|
||||||
struct qcom_icc_node {
|
struct qcom_osm_l3_node {
|
||||||
const char *name;
|
const char *name;
|
||||||
u16 links[OSM_L3_MAX_LINKS];
|
u16 links[OSM_L3_MAX_LINKS];
|
||||||
u16 id;
|
u16 id;
|
||||||
@ -64,8 +65,8 @@ struct qcom_icc_node {
|
|||||||
u16 buswidth;
|
u16 buswidth;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct qcom_icc_desc {
|
struct qcom_osm_l3_desc {
|
||||||
const struct qcom_icc_node **nodes;
|
const struct qcom_osm_l3_node **nodes;
|
||||||
size_t num_nodes;
|
size_t num_nodes;
|
||||||
unsigned int lut_row_size;
|
unsigned int lut_row_size;
|
||||||
unsigned int reg_freq_lut;
|
unsigned int reg_freq_lut;
|
||||||
@ -73,7 +74,7 @@ struct qcom_icc_desc {
|
|||||||
};
|
};
|
||||||
|
|
||||||
#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
|
#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
|
||||||
static const struct qcom_icc_node _name = { \
|
static const struct qcom_osm_l3_node _name = { \
|
||||||
.name = #_name, \
|
.name = #_name, \
|
||||||
.id = _id, \
|
.id = _id, \
|
||||||
.buswidth = _buswidth, \
|
.buswidth = _buswidth, \
|
||||||
@ -84,12 +85,12 @@ struct qcom_icc_desc {
|
|||||||
DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
|
DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
|
||||||
DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
|
DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
|
||||||
|
|
||||||
static const struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
|
static const struct qcom_osm_l3_node *sdm845_osm_l3_nodes[] = {
|
||||||
[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
|
[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
|
||||||
[SLAVE_OSM_L3] = &sdm845_osm_l3,
|
[SLAVE_OSM_L3] = &sdm845_osm_l3,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct qcom_icc_desc sdm845_icc_osm_l3 = {
|
static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
|
||||||
.nodes = sdm845_osm_l3_nodes,
|
.nodes = sdm845_osm_l3_nodes,
|
||||||
.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
|
.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
|
||||||
.lut_row_size = OSM_LUT_ROW_SIZE,
|
.lut_row_size = OSM_LUT_ROW_SIZE,
|
||||||
@ -100,12 +101,12 @@ static const struct qcom_icc_desc sdm845_icc_osm_l3 = {
|
|||||||
DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
|
DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
|
||||||
DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
|
DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
|
||||||
|
|
||||||
static const struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
|
static const struct qcom_osm_l3_node *sc7180_osm_l3_nodes[] = {
|
||||||
[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
|
[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
|
||||||
[SLAVE_OSM_L3] = &sc7180_osm_l3,
|
[SLAVE_OSM_L3] = &sc7180_osm_l3,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct qcom_icc_desc sc7180_icc_osm_l3 = {
|
static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
|
||||||
.nodes = sc7180_osm_l3_nodes,
|
.nodes = sc7180_osm_l3_nodes,
|
||||||
.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
|
.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
|
||||||
.lut_row_size = OSM_LUT_ROW_SIZE,
|
.lut_row_size = OSM_LUT_ROW_SIZE,
|
||||||
@ -113,15 +114,31 @@ static const struct qcom_icc_desc sc7180_icc_osm_l3 = {
|
|||||||
.reg_perf_state = OSM_REG_PERF_STATE,
|
.reg_perf_state = OSM_REG_PERF_STATE,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
|
||||||
|
DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
|
||||||
|
|
||||||
|
static const struct qcom_osm_l3_node *sc8180x_osm_l3_nodes[] = {
|
||||||
|
[MASTER_OSM_L3_APPS] = &sc8180x_osm_apps_l3,
|
||||||
|
[SLAVE_OSM_L3] = &sc8180x_osm_l3,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = {
|
||||||
|
.nodes = sc8180x_osm_l3_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(sc8180x_osm_l3_nodes),
|
||||||
|
.lut_row_size = OSM_LUT_ROW_SIZE,
|
||||||
|
.reg_freq_lut = OSM_REG_FREQ_LUT,
|
||||||
|
.reg_perf_state = OSM_REG_PERF_STATE,
|
||||||
|
};
|
||||||
|
|
||||||
DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
|
DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
|
||||||
DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
|
DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
|
||||||
|
|
||||||
static const struct qcom_icc_node *sm8150_osm_l3_nodes[] = {
|
static const struct qcom_osm_l3_node *sm8150_osm_l3_nodes[] = {
|
||||||
[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
|
[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
|
||||||
[SLAVE_OSM_L3] = &sm8150_osm_l3,
|
[SLAVE_OSM_L3] = &sm8150_osm_l3,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
|
static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = {
|
||||||
.nodes = sm8150_osm_l3_nodes,
|
.nodes = sm8150_osm_l3_nodes,
|
||||||
.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
|
.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
|
||||||
.lut_row_size = OSM_LUT_ROW_SIZE,
|
.lut_row_size = OSM_LUT_ROW_SIZE,
|
||||||
@ -132,12 +149,12 @@ static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
|
|||||||
DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
|
DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
|
||||||
DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
|
DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
|
||||||
|
|
||||||
static const struct qcom_icc_node *sm8250_epss_l3_nodes[] = {
|
static const struct qcom_osm_l3_node *sm8250_epss_l3_nodes[] = {
|
||||||
[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
|
[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
|
||||||
[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
|
[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct qcom_icc_desc sm8250_icc_epss_l3 = {
|
static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
|
||||||
.nodes = sm8250_epss_l3_nodes,
|
.nodes = sm8250_epss_l3_nodes,
|
||||||
.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
|
.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
|
||||||
.lut_row_size = EPSS_LUT_ROW_SIZE,
|
.lut_row_size = EPSS_LUT_ROW_SIZE,
|
||||||
@ -145,11 +162,11 @@ static const struct qcom_icc_desc sm8250_icc_epss_l3 = {
|
|||||||
.reg_perf_state = EPSS_REG_PERF_STATE,
|
.reg_perf_state = EPSS_REG_PERF_STATE,
|
||||||
};
|
};
|
||||||
|
|
||||||
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
|
||||||
{
|
{
|
||||||
struct qcom_osm_l3_icc_provider *qp;
|
struct qcom_osm_l3_icc_provider *qp;
|
||||||
struct icc_provider *provider;
|
struct icc_provider *provider;
|
||||||
const struct qcom_icc_node *qn;
|
const struct qcom_osm_l3_node *qn;
|
||||||
struct icc_node *n;
|
struct icc_node *n;
|
||||||
unsigned int index;
|
unsigned int index;
|
||||||
u32 agg_peak = 0;
|
u32 agg_peak = 0;
|
||||||
@ -158,7 +175,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
|||||||
|
|
||||||
qn = src->data;
|
qn = src->data;
|
||||||
provider = src->provider;
|
provider = src->provider;
|
||||||
qp = to_qcom_provider(provider);
|
qp = to_osm_l3_provider(provider);
|
||||||
|
|
||||||
list_for_each_entry(n, &provider->nodes, node_list)
|
list_for_each_entry(n, &provider->nodes, node_list)
|
||||||
provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
|
provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
|
||||||
@ -191,10 +208,10 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
|
|||||||
u32 info, src, lval, i, prev_freq = 0, freq;
|
u32 info, src, lval, i, prev_freq = 0, freq;
|
||||||
static unsigned long hw_rate, xo_rate;
|
static unsigned long hw_rate, xo_rate;
|
||||||
struct qcom_osm_l3_icc_provider *qp;
|
struct qcom_osm_l3_icc_provider *qp;
|
||||||
const struct qcom_icc_desc *desc;
|
const struct qcom_osm_l3_desc *desc;
|
||||||
struct icc_onecell_data *data;
|
struct icc_onecell_data *data;
|
||||||
struct icc_provider *provider;
|
struct icc_provider *provider;
|
||||||
const struct qcom_icc_node **qnodes;
|
const struct qcom_osm_l3_node **qnodes;
|
||||||
struct icc_node *node;
|
struct icc_node *node;
|
||||||
size_t num_nodes;
|
size_t num_nodes;
|
||||||
struct clk *clk;
|
struct clk *clk;
|
||||||
@ -264,7 +281,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
|
|||||||
|
|
||||||
provider = &qp->provider;
|
provider = &qp->provider;
|
||||||
provider->dev = &pdev->dev;
|
provider->dev = &pdev->dev;
|
||||||
provider->set = qcom_icc_set;
|
provider->set = qcom_osm_l3_set;
|
||||||
provider->aggregate = icc_std_aggregate;
|
provider->aggregate = icc_std_aggregate;
|
||||||
provider->xlate = of_icc_xlate_onecell;
|
provider->xlate = of_icc_xlate_onecell;
|
||||||
INIT_LIST_HEAD(&provider->nodes);
|
INIT_LIST_HEAD(&provider->nodes);
|
||||||
@ -286,7 +303,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
|
|||||||
}
|
}
|
||||||
|
|
||||||
node->name = qnodes[i]->name;
|
node->name = qnodes[i]->name;
|
||||||
/* Cast away const and add it back in qcom_icc_set() */
|
/* Cast away const and add it back in qcom_osm_l3_set() */
|
||||||
node->data = (void *)qnodes[i];
|
node->data = (void *)qnodes[i];
|
||||||
icc_node_add(node, provider);
|
icc_node_add(node, provider);
|
||||||
|
|
||||||
@ -311,6 +328,7 @@ static const struct of_device_id osm_l3_of_match[] = {
|
|||||||
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
|
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
|
||||||
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
|
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
|
||||||
{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
|
{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
|
||||||
|
{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
|
||||||
{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
|
{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
|
||||||
{ }
|
{ }
|
||||||
};
|
};
|
||||||
|
@ -504,98 +504,6 @@ static struct qcom_icc_desc sc7180_system_noc = {
|
|||||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||||
};
|
};
|
||||||
|
|
||||||
static int qnoc_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
const struct qcom_icc_desc *desc;
|
|
||||||
struct icc_onecell_data *data;
|
|
||||||
struct icc_provider *provider;
|
|
||||||
struct qcom_icc_node **qnodes;
|
|
||||||
struct qcom_icc_provider *qp;
|
|
||||||
struct icc_node *node;
|
|
||||||
size_t num_nodes, i;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
desc = device_get_match_data(&pdev->dev);
|
|
||||||
if (!desc)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
qnodes = desc->nodes;
|
|
||||||
num_nodes = desc->num_nodes;
|
|
||||||
|
|
||||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
|
||||||
if (!qp)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
|
||||||
if (!data)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
provider = &qp->provider;
|
|
||||||
provider->dev = &pdev->dev;
|
|
||||||
provider->set = qcom_icc_set;
|
|
||||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
|
||||||
provider->aggregate = qcom_icc_aggregate;
|
|
||||||
provider->xlate_extended = qcom_icc_xlate_extended;
|
|
||||||
INIT_LIST_HEAD(&provider->nodes);
|
|
||||||
provider->data = data;
|
|
||||||
|
|
||||||
qp->dev = &pdev->dev;
|
|
||||||
qp->bcms = desc->bcms;
|
|
||||||
qp->num_bcms = desc->num_bcms;
|
|
||||||
|
|
||||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
|
||||||
if (IS_ERR(qp->voter))
|
|
||||||
return PTR_ERR(qp->voter);
|
|
||||||
|
|
||||||
ret = icc_provider_add(provider);
|
|
||||||
if (ret) {
|
|
||||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < qp->num_bcms; i++)
|
|
||||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
|
||||||
|
|
||||||
for (i = 0; i < num_nodes; i++) {
|
|
||||||
size_t j;
|
|
||||||
|
|
||||||
if (!qnodes[i])
|
|
||||||
continue;
|
|
||||||
|
|
||||||
node = icc_node_create(qnodes[i]->id);
|
|
||||||
if (IS_ERR(node)) {
|
|
||||||
ret = PTR_ERR(node);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
node->name = qnodes[i]->name;
|
|
||||||
node->data = qnodes[i];
|
|
||||||
icc_node_add(node, provider);
|
|
||||||
|
|
||||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
|
||||||
icc_link_create(node, qnodes[i]->links[j]);
|
|
||||||
|
|
||||||
data->nodes[i] = node;
|
|
||||||
}
|
|
||||||
data->num_nodes = num_nodes;
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, qp);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
err:
|
|
||||||
icc_nodes_remove(provider);
|
|
||||||
icc_provider_del(provider);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int qnoc_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
icc_nodes_remove(&qp->provider);
|
|
||||||
return icc_provider_del(&qp->provider);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id qnoc_of_match[] = {
|
static const struct of_device_id qnoc_of_match[] = {
|
||||||
{ .compatible = "qcom,sc7180-aggre1-noc",
|
{ .compatible = "qcom,sc7180-aggre1-noc",
|
||||||
.data = &sc7180_aggre1_noc},
|
.data = &sc7180_aggre1_noc},
|
||||||
@ -628,8 +536,8 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||||
|
|
||||||
static struct platform_driver qnoc_driver = {
|
static struct platform_driver qnoc_driver = {
|
||||||
.probe = qnoc_probe,
|
.probe = qcom_icc_rpmh_probe,
|
||||||
.remove = qnoc_remove,
|
.remove = qcom_icc_rpmh_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "qnoc-sc7180",
|
.name = "qnoc-sc7180",
|
||||||
.of_match_table = qnoc_of_match,
|
.of_match_table = qnoc_of_match,
|
||||||
|
@ -1802,98 +1802,6 @@ static struct qcom_icc_desc sc7280_system_noc = {
|
|||||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||||
};
|
};
|
||||||
|
|
||||||
static int qnoc_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
const struct qcom_icc_desc *desc;
|
|
||||||
struct icc_onecell_data *data;
|
|
||||||
struct icc_provider *provider;
|
|
||||||
struct qcom_icc_node **qnodes;
|
|
||||||
struct qcom_icc_provider *qp;
|
|
||||||
struct icc_node *node;
|
|
||||||
size_t num_nodes, i;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
desc = device_get_match_data(&pdev->dev);
|
|
||||||
if (!desc)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
qnodes = desc->nodes;
|
|
||||||
num_nodes = desc->num_nodes;
|
|
||||||
|
|
||||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
|
||||||
if (!qp)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
|
||||||
if (!data)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
provider = &qp->provider;
|
|
||||||
provider->dev = &pdev->dev;
|
|
||||||
provider->set = qcom_icc_set;
|
|
||||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
|
||||||
provider->aggregate = qcom_icc_aggregate;
|
|
||||||
provider->xlate_extended = qcom_icc_xlate_extended;
|
|
||||||
INIT_LIST_HEAD(&provider->nodes);
|
|
||||||
provider->data = data;
|
|
||||||
|
|
||||||
qp->dev = &pdev->dev;
|
|
||||||
qp->bcms = desc->bcms;
|
|
||||||
qp->num_bcms = desc->num_bcms;
|
|
||||||
|
|
||||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
|
||||||
if (IS_ERR(qp->voter))
|
|
||||||
return PTR_ERR(qp->voter);
|
|
||||||
|
|
||||||
ret = icc_provider_add(provider);
|
|
||||||
if (ret) {
|
|
||||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < qp->num_bcms; i++)
|
|
||||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
|
||||||
|
|
||||||
for (i = 0; i < num_nodes; i++) {
|
|
||||||
size_t j;
|
|
||||||
|
|
||||||
if (!qnodes[i])
|
|
||||||
continue;
|
|
||||||
|
|
||||||
node = icc_node_create(qnodes[i]->id);
|
|
||||||
if (IS_ERR(node)) {
|
|
||||||
ret = PTR_ERR(node);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
node->name = qnodes[i]->name;
|
|
||||||
node->data = qnodes[i];
|
|
||||||
icc_node_add(node, provider);
|
|
||||||
|
|
||||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
|
||||||
icc_link_create(node, qnodes[i]->links[j]);
|
|
||||||
|
|
||||||
data->nodes[i] = node;
|
|
||||||
}
|
|
||||||
data->num_nodes = num_nodes;
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, qp);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
err:
|
|
||||||
icc_nodes_remove(provider);
|
|
||||||
icc_provider_del(provider);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int qnoc_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
icc_nodes_remove(&qp->provider);
|
|
||||||
return icc_provider_del(&qp->provider);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id qnoc_of_match[] = {
|
static const struct of_device_id qnoc_of_match[] = {
|
||||||
{ .compatible = "qcom,sc7280-aggre1-noc",
|
{ .compatible = "qcom,sc7280-aggre1-noc",
|
||||||
.data = &sc7280_aggre1_noc},
|
.data = &sc7280_aggre1_noc},
|
||||||
@ -1924,8 +1832,8 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||||
|
|
||||||
static struct platform_driver qnoc_driver = {
|
static struct platform_driver qnoc_driver = {
|
||||||
.probe = qnoc_probe,
|
.probe = qcom_icc_rpmh_probe,
|
||||||
.remove = qnoc_remove,
|
.remove = qcom_icc_rpmh_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "qnoc-sc7280",
|
.name = "qnoc-sc7280",
|
||||||
.of_match_table = qnoc_of_match,
|
.of_match_table = qnoc_of_match,
|
||||||
|
626
drivers/interconnect/qcom/sc8180x.c
Normal file
626
drivers/interconnect/qcom/sc8180x.c
Normal file
@ -0,0 +1,626 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||||
|
* Copyright (c) 2021, Linaro Ltd.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/device.h>
|
||||||
|
#include <linux/interconnect-provider.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/of_device.h>
|
||||||
|
|
||||||
|
#include <dt-bindings/interconnect/qcom,sc8180x.h>
|
||||||
|
|
||||||
|
#include "bcm-voter.h"
|
||||||
|
#include "icc-rpmh.h"
|
||||||
|
#include "sc8180x.h"
|
||||||
|
|
||||||
|
DEFINE_QNODE(mas_qhm_a1noc_cfg, SC8180X_MASTER_A1NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_A1NOC);
|
||||||
|
DEFINE_QNODE(mas_xm_ufs_card, SC8180X_MASTER_UFS_CARD, 1, 8, SC8180X_A1NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_ufs_g4, SC8180X_MASTER_UFS_GEN4, 1, 8, SC8180X_A1NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_ufs_mem, SC8180X_MASTER_UFS_MEM, 1, 8, SC8180X_A1NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_usb3_0, SC8180X_MASTER_USB3, 1, 8, SC8180X_A1NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_usb3_1, SC8180X_MASTER_USB3_1, 1, 8, SC8180X_A1NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_usb3_2, SC8180X_MASTER_USB3_2, 1, 16, SC8180X_A1NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qhm_a2noc_cfg, SC8180X_MASTER_A2NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_A2NOC);
|
||||||
|
DEFINE_QNODE(mas_qhm_qdss_bam, SC8180X_MASTER_QDSS_BAM, 1, 4, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qhm_qspi, SC8180X_MASTER_QSPI_0, 1, 4, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qhm_qspi1, SC8180X_MASTER_QSPI_1, 1, 4, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qhm_qup0, SC8180X_MASTER_QUP_0, 1, 4, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qhm_qup1, SC8180X_MASTER_QUP_1, 1, 4, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qhm_qup2, SC8180X_MASTER_QUP_2, 1, 4, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qhm_sensorss_ahb, SC8180X_MASTER_SENSORS_AHB, 1, 4, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qxm_crypto, SC8180X_MASTER_CRYPTO_CORE_0, 1, 8, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qxm_ipa, SC8180X_MASTER_IPA, 1, 8, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_emac, SC8180X_MASTER_EMAC, 1, 8, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_pcie3_0, SC8180X_MASTER_PCIE, 1, 8, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_xm_pcie3_1, SC8180X_MASTER_PCIE_1, 1, 16, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_xm_pcie3_2, SC8180X_MASTER_PCIE_2, 1, 8, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_xm_pcie3_3, SC8180X_MASTER_PCIE_3, 1, 16, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_xm_qdss_etr, SC8180X_MASTER_QDSS_ETR, 1, 8, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_sdc2, SC8180X_MASTER_SDCC_2, 1, 8, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_xm_sdc4, SC8180X_MASTER_SDCC_4, 1, 8, SC8180X_A2NOC_SNOC_SLV);
|
||||||
|
DEFINE_QNODE(mas_qxm_camnoc_hf0_uncomp, SC8180X_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP);
|
||||||
|
DEFINE_QNODE(mas_qxm_camnoc_hf1_uncomp, SC8180X_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP);
|
||||||
|
DEFINE_QNODE(mas_qxm_camnoc_sf_uncomp, SC8180X_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP);
|
||||||
|
DEFINE_QNODE(mas_qnm_npu, SC8180X_MASTER_NPU, 1, 32, SC8180X_SLAVE_CDSP_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qnm_snoc, SC8180X_SNOC_CNOC_MAS, 1, 8, SC8180X_SLAVE_TLMM_SOUTH, SC8180X_SLAVE_CDSP_CFG, SC8180X_SLAVE_SPSS_CFG, SC8180X_SLAVE_CAMERA_CFG, SC8180X_SLAVE_SDCC_4, SC8180X_SLAVE_AHB2PHY_CENTER, SC8180X_SLAVE_SDCC_2, SC8180X_SLAVE_PCIE_2_CFG, SC8180X_SLAVE_CNOC_MNOC_CFG, SC8180X_SLAVE_EMAC_CFG, SC8180X_SLAVE_QSPI_0, SC8180X_SLAVE_QSPI_1, SC8180X_SLAVE_TLMM_EAST, SC8180X_SLAVE_SNOC_CFG, SC8180X_SLAVE_AHB2PHY_EAST, SC8180X_SLAVE_GLM, SC8180X_SLAVE_PDM, SC8180X_SLAVE_PCIE_1_CFG, SC8180X_SLAVE_A2NOC_CFG, SC8180X_SLAVE_QDSS_CFG, SC8180X_SLAVE_DISPLAY_CFG, SC8180X_SLAVE_TCSR, SC8180X_SLAVE_UFS_MEM_0_CFG, SC8180X_SLAVE_CNOC_DDRSS, SC8180X_SLAVE_PCIE_0_CFG, SC8180X_SLAVE_QUP_1, SC8180X_SLAVE_QUP_2, SC8180X_SLAVE_NPU_CFG, SC8180X_SLAVE_CRYPTO_0_CFG, SC8180X_SLAVE_GRAPHICS_3D_CFG, SC8180X_SLAVE_VENUS_CFG, SC8180X_SLAVE_TSIF, SC8180X_SLAVE_IPA_CFG, SC8180X_SLAVE_CLK_CTL, SC8180X_SLAVE_SECURITY, SC8180X_SLAVE_AOP, SC8180X_SLAVE_AHB2PHY_WEST, SC8180X_SLAVE_AHB2PHY_SOUTH, SC8180X_SLAVE_SERVICE_CNOC, SC8180X_SLAVE_UFS_CARD_CFG, SC8180X_SLAVE_USB3_1, SC8180X_SLAVE_USB3_2, SC8180X_SLAVE_PCIE_3_CFG, SC8180X_SLAVE_RBCPR_CX_CFG, SC8180X_SLAVE_TLMM_WEST, SC8180X_SLAVE_A1NOC_CFG, SC8180X_SLAVE_AOSS, SC8180X_SLAVE_PRNG, SC8180X_SLAVE_VSENSE_CTRL_CFG, SC8180X_SLAVE_QUP_0, SC8180X_SLAVE_USB3, SC8180X_SLAVE_RBCPR_MMCX_CFG, SC8180X_SLAVE_PIMEM_CFG, SC8180X_SLAVE_UFS_MEM_1_CFG, SC8180X_SLAVE_RBCPR_MX_CFG, SC8180X_SLAVE_IMEM_CFG);
|
||||||
|
DEFINE_QNODE(mas_qhm_cnoc_dc_noc, SC8180X_MASTER_CNOC_DC_NOC, 1, 4, SC8180X_SLAVE_LLCC_CFG, SC8180X_SLAVE_GEM_NOC_CFG);
|
||||||
|
DEFINE_QNODE(mas_acm_apps, SC8180X_MASTER_AMPSS_M0, 4, 64, SC8180X_SLAVE_ECC, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC);
|
||||||
|
DEFINE_QNODE(mas_acm_gpu_tcu, SC8180X_MASTER_GPU_TCU, 1, 8, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC);
|
||||||
|
DEFINE_QNODE(mas_acm_sys_tcu, SC8180X_MASTER_SYS_TCU, 1, 8, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC);
|
||||||
|
DEFINE_QNODE(mas_qhm_gemnoc_cfg, SC8180X_MASTER_GEM_NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_GEM_NOC_1, SC8180X_SLAVE_SERVICE_GEM_NOC, SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG);
|
||||||
|
DEFINE_QNODE(mas_qnm_cmpnoc, SC8180X_MASTER_COMPUTE_NOC, 2, 32, SC8180X_SLAVE_ECC, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC);
|
||||||
|
DEFINE_QNODE(mas_qnm_gpu, SC8180X_MASTER_GRAPHICS_3D, 4, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC);
|
||||||
|
DEFINE_QNODE(mas_qnm_mnoc_hf, SC8180X_MASTER_MNOC_HF_MEM_NOC, 2, 32, SC8180X_SLAVE_LLCC);
|
||||||
|
DEFINE_QNODE(mas_qnm_mnoc_sf, SC8180X_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC);
|
||||||
|
DEFINE_QNODE(mas_qnm_pcie, SC8180X_MASTER_GEM_NOC_PCIE_SNOC, 1, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC);
|
||||||
|
DEFINE_QNODE(mas_qnm_snoc_gc, SC8180X_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC8180X_SLAVE_LLCC);
|
||||||
|
DEFINE_QNODE(mas_qnm_snoc_sf, SC8180X_MASTER_SNOC_SF_MEM_NOC, 1, 32, SC8180X_SLAVE_LLCC);
|
||||||
|
DEFINE_QNODE(mas_qxm_ecc, SC8180X_MASTER_ECC, 2, 32, SC8180X_SLAVE_LLCC);
|
||||||
|
DEFINE_QNODE(mas_ipa_core_master, SC8180X_MASTER_IPA_CORE, 1, 8, SC8180X_SLAVE_IPA_CORE);
|
||||||
|
DEFINE_QNODE(mas_llcc_mc, SC8180X_MASTER_LLCC, 8, 4, SC8180X_SLAVE_EBI_CH0);
|
||||||
|
DEFINE_QNODE(mas_qhm_mnoc_cfg, SC8180X_MASTER_CNOC_MNOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_MNOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_camnoc_hf0, SC8180X_MASTER_CAMNOC_HF0, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_camnoc_hf1, SC8180X_MASTER_CAMNOC_HF1, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_camnoc_sf, SC8180X_MASTER_CAMNOC_SF, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_mdp0, SC8180X_MASTER_MDP_PORT0, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_mdp1, SC8180X_MASTER_MDP_PORT1, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_rot, SC8180X_MASTER_ROTATOR, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_venus0, SC8180X_MASTER_VIDEO_P0, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_venus1, SC8180X_MASTER_VIDEO_P1, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qxm_venus_arm9, SC8180X_MASTER_VIDEO_PROC, 1, 8, SC8180X_SLAVE_MNOC_SF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(mas_qhm_snoc_cfg, SC8180X_MASTER_SNOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_SNOC);
|
||||||
|
DEFINE_QNODE(mas_qnm_aggre1_noc, SC8180X_A1NOC_SNOC_MAS, 1, 32, SC8180X_SLAVE_SNOC_GEM_NOC_SF, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_QDSS_STM);
|
||||||
|
DEFINE_QNODE(mas_qnm_aggre2_noc, SC8180X_A2NOC_SNOC_MAS, 1, 16, SC8180X_SLAVE_SNOC_GEM_NOC_SF, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_PCIE_3, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SLAVE_PCIE_2, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_PCIE_0, SC8180X_SLAVE_PCIE_1, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM);
|
||||||
|
DEFINE_QNODE(mas_qnm_gemnoc, SC8180X_MASTER_GEM_NOC_SNOC, 1, 8, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM);
|
||||||
|
DEFINE_QNODE(mas_qxm_pimem, SC8180X_MASTER_PIMEM, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM);
|
||||||
|
DEFINE_QNODE(mas_xm_gic, SC8180X_MASTER_GIC, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM);
|
||||||
|
DEFINE_QNODE(slv_qns_a1noc_snoc, SC8180X_A1NOC_SNOC_SLV, 1, 32, SC8180X_A1NOC_SNOC_MAS);
|
||||||
|
DEFINE_QNODE(slv_srvc_aggre1_noc, SC8180X_SLAVE_SERVICE_A1NOC, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qns_a2noc_snoc, SC8180X_A2NOC_SNOC_SLV, 1, 16, SC8180X_A2NOC_SNOC_MAS);
|
||||||
|
DEFINE_QNODE(slv_qns_pcie_mem_noc, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, 1, 32, SC8180X_MASTER_GEM_NOC_PCIE_SNOC);
|
||||||
|
DEFINE_QNODE(slv_srvc_aggre2_noc, SC8180X_SLAVE_SERVICE_A2NOC, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qns_camnoc_uncomp, SC8180X_SLAVE_CAMNOC_UNCOMP, 1, 32);
|
||||||
|
DEFINE_QNODE(slv_qns_cdsp_mem_noc, SC8180X_SLAVE_CDSP_MEM_NOC, 2, 32, SC8180X_MASTER_COMPUTE_NOC);
|
||||||
|
DEFINE_QNODE(slv_qhs_a1_noc_cfg, SC8180X_SLAVE_A1NOC_CFG, 1, 4, SC8180X_MASTER_A1NOC_CFG);
|
||||||
|
DEFINE_QNODE(slv_qhs_a2_noc_cfg, SC8180X_SLAVE_A2NOC_CFG, 1, 4, SC8180X_MASTER_A2NOC_CFG);
|
||||||
|
DEFINE_QNODE(slv_qhs_ahb2phy_refgen_center, SC8180X_SLAVE_AHB2PHY_CENTER, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_ahb2phy_refgen_east, SC8180X_SLAVE_AHB2PHY_EAST, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_ahb2phy_refgen_west, SC8180X_SLAVE_AHB2PHY_WEST, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_ahb2phy_south, SC8180X_SLAVE_AHB2PHY_SOUTH, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_aop, SC8180X_SLAVE_AOP, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_aoss, SC8180X_SLAVE_AOSS, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_camera_cfg, SC8180X_SLAVE_CAMERA_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_clk_ctl, SC8180X_SLAVE_CLK_CTL, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_compute_dsp, SC8180X_SLAVE_CDSP_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_cpr_cx, SC8180X_SLAVE_RBCPR_CX_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_cpr_mmcx, SC8180X_SLAVE_RBCPR_MMCX_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_cpr_mx, SC8180X_SLAVE_RBCPR_MX_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_crypto0_cfg, SC8180X_SLAVE_CRYPTO_0_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_ddrss_cfg, SC8180X_SLAVE_CNOC_DDRSS, 1, 4, SC8180X_MASTER_CNOC_DC_NOC);
|
||||||
|
DEFINE_QNODE(slv_qhs_display_cfg, SC8180X_SLAVE_DISPLAY_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_emac_cfg, SC8180X_SLAVE_EMAC_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_glm, SC8180X_SLAVE_GLM, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_gpuss_cfg, SC8180X_SLAVE_GRAPHICS_3D_CFG, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_qhs_imem_cfg, SC8180X_SLAVE_IMEM_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_ipa, SC8180X_SLAVE_IPA_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_mnoc_cfg, SC8180X_SLAVE_CNOC_MNOC_CFG, 1, 4, SC8180X_MASTER_CNOC_MNOC_CFG);
|
||||||
|
DEFINE_QNODE(slv_qhs_npu_cfg, SC8180X_SLAVE_NPU_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_pcie0_cfg, SC8180X_SLAVE_PCIE_0_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_pcie1_cfg, SC8180X_SLAVE_PCIE_1_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_pcie2_cfg, SC8180X_SLAVE_PCIE_2_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_pcie3_cfg, SC8180X_SLAVE_PCIE_3_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_pdm, SC8180X_SLAVE_PDM, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_pimem_cfg, SC8180X_SLAVE_PIMEM_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_prng, SC8180X_SLAVE_PRNG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_qdss_cfg, SC8180X_SLAVE_QDSS_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_qspi_0, SC8180X_SLAVE_QSPI_0, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_qspi_1, SC8180X_SLAVE_QSPI_1, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_qupv3_east0, SC8180X_SLAVE_QUP_1, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_qupv3_east1, SC8180X_SLAVE_QUP_2, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_qupv3_west, SC8180X_SLAVE_QUP_0, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_sdc2, SC8180X_SLAVE_SDCC_2, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_sdc4, SC8180X_SLAVE_SDCC_4, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_security, SC8180X_SLAVE_SECURITY, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_snoc_cfg, SC8180X_SLAVE_SNOC_CFG, 1, 4, SC8180X_MASTER_SNOC_CFG);
|
||||||
|
DEFINE_QNODE(slv_qhs_spss_cfg, SC8180X_SLAVE_SPSS_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_tcsr, SC8180X_SLAVE_TCSR, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_tlmm_east, SC8180X_SLAVE_TLMM_EAST, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_tlmm_south, SC8180X_SLAVE_TLMM_SOUTH, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_tlmm_west, SC8180X_SLAVE_TLMM_WEST, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_tsif, SC8180X_SLAVE_TSIF, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_ufs_card_cfg, SC8180X_SLAVE_UFS_CARD_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_ufs_mem0_cfg, SC8180X_SLAVE_UFS_MEM_0_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_ufs_mem1_cfg, SC8180X_SLAVE_UFS_MEM_1_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_usb3_0, SC8180X_SLAVE_USB3, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_usb3_1, SC8180X_SLAVE_USB3_1, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_usb3_2, SC8180X_SLAVE_USB3_2, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_venus_cfg, SC8180X_SLAVE_VENUS_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_vsense_ctrl_cfg, SC8180X_SLAVE_VSENSE_CTRL_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_srvc_cnoc, SC8180X_SLAVE_SERVICE_CNOC, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_gemnoc, SC8180X_SLAVE_GEM_NOC_CFG, 1, 4, SC8180X_MASTER_GEM_NOC_CFG);
|
||||||
|
DEFINE_QNODE(slv_qhs_llcc, SC8180X_SLAVE_LLCC_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_mdsp_ms_mpu_cfg, SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qns_ecc, SC8180X_SLAVE_ECC, 1, 32);
|
||||||
|
DEFINE_QNODE(slv_qns_gem_noc_snoc, SC8180X_SLAVE_GEM_NOC_SNOC, 1, 8, SC8180X_MASTER_GEM_NOC_SNOC);
|
||||||
|
DEFINE_QNODE(slv_qns_llcc, SC8180X_SLAVE_LLCC, 8, 16, SC8180X_MASTER_LLCC);
|
||||||
|
DEFINE_QNODE(slv_srvc_gemnoc, SC8180X_SLAVE_SERVICE_GEM_NOC, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_srvc_gemnoc1, SC8180X_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_ipa_core_slave, SC8180X_SLAVE_IPA_CORE, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_ebi, SC8180X_SLAVE_EBI_CH0, 8, 4);
|
||||||
|
DEFINE_QNODE(slv_qns2_mem_noc, SC8180X_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC8180X_MASTER_MNOC_SF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(slv_qns_mem_noc_hf, SC8180X_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SC8180X_MASTER_MNOC_HF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(slv_srvc_mnoc, SC8180X_SLAVE_SERVICE_MNOC, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_qhs_apss, SC8180X_SLAVE_APPSS, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_qns_cnoc, SC8180X_SNOC_CNOC_SLV, 1, 8, SC8180X_SNOC_CNOC_MAS);
|
||||||
|
DEFINE_QNODE(slv_qns_gemnoc_gc, SC8180X_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC8180X_MASTER_SNOC_GC_MEM_NOC);
|
||||||
|
DEFINE_QNODE(slv_qns_gemnoc_sf, SC8180X_SLAVE_SNOC_GEM_NOC_SF, 1, 32, SC8180X_MASTER_SNOC_SF_MEM_NOC);
|
||||||
|
DEFINE_QNODE(slv_qxs_imem, SC8180X_SLAVE_OCIMEM, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_qxs_pimem, SC8180X_SLAVE_PIMEM, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_srvc_snoc, SC8180X_SLAVE_SERVICE_SNOC, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_xs_pcie_0, SC8180X_SLAVE_PCIE_0, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_xs_pcie_1, SC8180X_SLAVE_PCIE_1, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_xs_pcie_2, SC8180X_SLAVE_PCIE_2, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_xs_pcie_3, SC8180X_SLAVE_PCIE_3, 1, 8);
|
||||||
|
DEFINE_QNODE(slv_xs_qdss_stm, SC8180X_SLAVE_QDSS_STM, 1, 4);
|
||||||
|
DEFINE_QNODE(slv_xs_sys_tcu_cfg, SC8180X_SLAVE_TCU, 1, 8);
|
||||||
|
|
||||||
|
DEFINE_QBCM(bcm_acv, "ACV", false, &slv_ebi);
|
||||||
|
DEFINE_QBCM(bcm_mc0, "MC0", false, &slv_ebi);
|
||||||
|
DEFINE_QBCM(bcm_sh0, "SH0", false, &slv_qns_llcc);
|
||||||
|
DEFINE_QBCM(bcm_mm0, "MM0", false, &slv_qns_mem_noc_hf);
|
||||||
|
DEFINE_QBCM(bcm_co0, "CO0", false, &slv_qns_cdsp_mem_noc);
|
||||||
|
DEFINE_QBCM(bcm_ce0, "CE0", false, &mas_qxm_crypto);
|
||||||
|
DEFINE_QBCM(bcm_cn0, "CN0", false, &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, &slv_qhs_a2_noc_cfg, &slv_qhs_ahb2phy_refgen_center, &slv_qhs_ahb2phy_refgen_east, &slv_qhs_ahb2phy_refgen_west, &slv_qhs_ahb2phy_south, &slv_qhs_aop, &slv_qhs_aoss, &slv_qhs_camera_cfg, &slv_qhs_clk_ctl, &slv_qhs_compute_dsp, &slv_qhs_cpr_cx, &slv_qhs_cpr_mmcx, &slv_qhs_cpr_mx, &slv_qhs_crypto0_cfg, &slv_qhs_ddrss_cfg, &slv_qhs_display_cfg, &slv_qhs_emac_cfg, &slv_qhs_glm, &slv_qhs_gpuss_cfg, &slv_qhs_imem_cfg, &slv_qhs_ipa, &slv_qhs_mnoc_cfg, &slv_qhs_npu_cfg, &slv_qhs_pcie0_cfg, &slv_qhs_pcie1_cfg, &slv_qhs_pcie2_cfg, &slv_qhs_pcie3_cfg, &slv_qhs_pdm, &slv_qhs_pimem_cfg, &slv_qhs_prng, &slv_qhs_qdss_cfg, &slv_qhs_qspi_0, &slv_qhs_qspi_1, &slv_qhs_qupv3_east0, &slv_qhs_qupv3_east1, &slv_qhs_qupv3_west, &slv_qhs_sdc2, &slv_qhs_sdc4, &slv_qhs_security, &slv_qhs_snoc_cfg, &slv_qhs_spss_cfg, &slv_qhs_tcsr, &slv_qhs_tlmm_east, &slv_qhs_tlmm_south, &slv_qhs_tlmm_west, &slv_qhs_tsif, &slv_qhs_ufs_card_cfg, &slv_qhs_ufs_mem0_cfg, &slv_qhs_ufs_mem1_cfg, &slv_qhs_usb3_0, &slv_qhs_usb3_1, &slv_qhs_usb3_2, &slv_qhs_venus_cfg, &slv_qhs_vsense_ctrl_cfg, &slv_srvc_cnoc);
|
||||||
|
DEFINE_QBCM(bcm_mm1, "MM1", false, &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, &mas_qxm_camnoc_sf_uncomp, &mas_qxm_camnoc_hf0, &mas_qxm_camnoc_hf1, &mas_qxm_mdp0, &mas_qxm_mdp1);
|
||||||
|
DEFINE_QBCM(bcm_qup0, "QUP0", false, &mas_qhm_qup0, &mas_qhm_qup1, &mas_qhm_qup2);
|
||||||
|
DEFINE_QBCM(bcm_sh2, "SH2", false, &slv_qns_gem_noc_snoc);
|
||||||
|
DEFINE_QBCM(bcm_mm2, "MM2", false, &mas_qxm_camnoc_sf, &mas_qxm_rot, &mas_qxm_venus0, &mas_qxm_venus1, &mas_qxm_venus_arm9, &slv_qns2_mem_noc);
|
||||||
|
DEFINE_QBCM(bcm_sh3, "SH3", false, &mas_acm_apps);
|
||||||
|
DEFINE_QBCM(bcm_sn0, "SN0", false, &slv_qns_gemnoc_sf);
|
||||||
|
DEFINE_QBCM(bcm_sn1, "SN1", false, &slv_qxs_imem);
|
||||||
|
DEFINE_QBCM(bcm_sn2, "SN2", false, &slv_qns_gemnoc_gc);
|
||||||
|
DEFINE_QBCM(bcm_co2, "CO2", false, &mas_qnm_npu);
|
||||||
|
DEFINE_QBCM(bcm_ip0, "IP0", false, &slv_ipa_core_slave);
|
||||||
|
DEFINE_QBCM(bcm_sn3, "SN3", false, &slv_srvc_aggre1_noc, &slv_qns_cnoc);
|
||||||
|
DEFINE_QBCM(bcm_sn4, "SN4", false, &slv_qxs_pimem);
|
||||||
|
DEFINE_QBCM(bcm_sn8, "SN8", false, &slv_xs_pcie_0, &slv_xs_pcie_1, &slv_xs_pcie_2, &slv_xs_pcie_3);
|
||||||
|
DEFINE_QBCM(bcm_sn9, "SN9", false, &mas_qnm_aggre1_noc);
|
||||||
|
DEFINE_QBCM(bcm_sn11, "SN11", false, &mas_qnm_aggre2_noc);
|
||||||
|
DEFINE_QBCM(bcm_sn14, "SN14", false, &slv_qns_pcie_mem_noc);
|
||||||
|
DEFINE_QBCM(bcm_sn15, "SN15", false, &mas_qnm_gemnoc);
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
|
||||||
|
&bcm_sn3,
|
||||||
|
&bcm_ce0,
|
||||||
|
&bcm_qup0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
|
||||||
|
&bcm_sn14,
|
||||||
|
&bcm_ce0,
|
||||||
|
&bcm_qup0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
|
||||||
|
&bcm_mm1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *compute_noc_bcms[] = {
|
||||||
|
&bcm_co0,
|
||||||
|
&bcm_co2,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *config_noc_bcms[] = {
|
||||||
|
&bcm_cn0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *gem_noc_bcms[] = {
|
||||||
|
&bcm_sh0,
|
||||||
|
&bcm_sh2,
|
||||||
|
&bcm_sh3,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *ipa_virt_bcms[] = {
|
||||||
|
&bcm_ip0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *mc_virt_bcms[] = {
|
||||||
|
&bcm_mc0,
|
||||||
|
&bcm_acv,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
|
||||||
|
&bcm_mm0,
|
||||||
|
&bcm_mm1,
|
||||||
|
&bcm_mm2,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_bcm *system_noc_bcms[] = {
|
||||||
|
&bcm_sn0,
|
||||||
|
&bcm_sn1,
|
||||||
|
&bcm_sn2,
|
||||||
|
&bcm_sn3,
|
||||||
|
&bcm_sn4,
|
||||||
|
&bcm_sn8,
|
||||||
|
&bcm_sn9,
|
||||||
|
&bcm_sn11,
|
||||||
|
&bcm_sn15,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *aggre1_noc_nodes[] = {
|
||||||
|
[MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg,
|
||||||
|
[MASTER_UFS_CARD] = &mas_xm_ufs_card,
|
||||||
|
[MASTER_UFS_GEN4] = &mas_xm_ufs_g4,
|
||||||
|
[MASTER_UFS_MEM] = &mas_xm_ufs_mem,
|
||||||
|
[MASTER_USB3] = &mas_xm_usb3_0,
|
||||||
|
[MASTER_USB3_1] = &mas_xm_usb3_1,
|
||||||
|
[MASTER_USB3_2] = &mas_xm_usb3_2,
|
||||||
|
[A1NOC_SNOC_SLV] = &slv_qns_a1noc_snoc,
|
||||||
|
[SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *aggre2_noc_nodes[] = {
|
||||||
|
[MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg,
|
||||||
|
[MASTER_QDSS_BAM] = &mas_qhm_qdss_bam,
|
||||||
|
[MASTER_QSPI_0] = &mas_qhm_qspi,
|
||||||
|
[MASTER_QSPI_1] = &mas_qhm_qspi1,
|
||||||
|
[MASTER_QUP_0] = &mas_qhm_qup0,
|
||||||
|
[MASTER_QUP_1] = &mas_qhm_qup1,
|
||||||
|
[MASTER_QUP_2] = &mas_qhm_qup2,
|
||||||
|
[MASTER_SENSORS_AHB] = &mas_qhm_sensorss_ahb,
|
||||||
|
[MASTER_CRYPTO_CORE_0] = &mas_qxm_crypto,
|
||||||
|
[MASTER_IPA] = &mas_qxm_ipa,
|
||||||
|
[MASTER_EMAC] = &mas_xm_emac,
|
||||||
|
[MASTER_PCIE] = &mas_xm_pcie3_0,
|
||||||
|
[MASTER_PCIE_1] = &mas_xm_pcie3_1,
|
||||||
|
[MASTER_PCIE_2] = &mas_xm_pcie3_2,
|
||||||
|
[MASTER_PCIE_3] = &mas_xm_pcie3_3,
|
||||||
|
[MASTER_QDSS_ETR] = &mas_xm_qdss_etr,
|
||||||
|
[MASTER_SDCC_2] = &mas_xm_sdc2,
|
||||||
|
[MASTER_SDCC_4] = &mas_xm_sdc4,
|
||||||
|
[A2NOC_SNOC_SLV] = &slv_qns_a2noc_snoc,
|
||||||
|
[SLAVE_ANOC_PCIE_GEM_NOC] = &slv_qns_pcie_mem_noc,
|
||||||
|
[SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *camnoc_virt_nodes[] = {
|
||||||
|
[MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp,
|
||||||
|
[MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp,
|
||||||
|
[MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp,
|
||||||
|
[SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *compute_noc_nodes[] = {
|
||||||
|
[MASTER_NPU] = &mas_qnm_npu,
|
||||||
|
[SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *config_noc_nodes[] = {
|
||||||
|
[SNOC_CNOC_MAS] = &mas_qnm_snoc,
|
||||||
|
[SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg,
|
||||||
|
[SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg,
|
||||||
|
[SLAVE_AHB2PHY_CENTER] = &slv_qhs_ahb2phy_refgen_center,
|
||||||
|
[SLAVE_AHB2PHY_EAST] = &slv_qhs_ahb2phy_refgen_east,
|
||||||
|
[SLAVE_AHB2PHY_WEST] = &slv_qhs_ahb2phy_refgen_west,
|
||||||
|
[SLAVE_AHB2PHY_SOUTH] = &slv_qhs_ahb2phy_south,
|
||||||
|
[SLAVE_AOP] = &slv_qhs_aop,
|
||||||
|
[SLAVE_AOSS] = &slv_qhs_aoss,
|
||||||
|
[SLAVE_CAMERA_CFG] = &slv_qhs_camera_cfg,
|
||||||
|
[SLAVE_CLK_CTL] = &slv_qhs_clk_ctl,
|
||||||
|
[SLAVE_CDSP_CFG] = &slv_qhs_compute_dsp,
|
||||||
|
[SLAVE_RBCPR_CX_CFG] = &slv_qhs_cpr_cx,
|
||||||
|
[SLAVE_RBCPR_MMCX_CFG] = &slv_qhs_cpr_mmcx,
|
||||||
|
[SLAVE_RBCPR_MX_CFG] = &slv_qhs_cpr_mx,
|
||||||
|
[SLAVE_CRYPTO_0_CFG] = &slv_qhs_crypto0_cfg,
|
||||||
|
[SLAVE_CNOC_DDRSS] = &slv_qhs_ddrss_cfg,
|
||||||
|
[SLAVE_DISPLAY_CFG] = &slv_qhs_display_cfg,
|
||||||
|
[SLAVE_EMAC_CFG] = &slv_qhs_emac_cfg,
|
||||||
|
[SLAVE_GLM] = &slv_qhs_glm,
|
||||||
|
[SLAVE_GRAPHICS_3D_CFG] = &slv_qhs_gpuss_cfg,
|
||||||
|
[SLAVE_IMEM_CFG] = &slv_qhs_imem_cfg,
|
||||||
|
[SLAVE_IPA_CFG] = &slv_qhs_ipa,
|
||||||
|
[SLAVE_CNOC_MNOC_CFG] = &slv_qhs_mnoc_cfg,
|
||||||
|
[SLAVE_NPU_CFG] = &slv_qhs_npu_cfg,
|
||||||
|
[SLAVE_PCIE_0_CFG] = &slv_qhs_pcie0_cfg,
|
||||||
|
[SLAVE_PCIE_1_CFG] = &slv_qhs_pcie1_cfg,
|
||||||
|
[SLAVE_PCIE_2_CFG] = &slv_qhs_pcie2_cfg,
|
||||||
|
[SLAVE_PCIE_3_CFG] = &slv_qhs_pcie3_cfg,
|
||||||
|
[SLAVE_PDM] = &slv_qhs_pdm,
|
||||||
|
[SLAVE_PIMEM_CFG] = &slv_qhs_pimem_cfg,
|
||||||
|
[SLAVE_PRNG] = &slv_qhs_prng,
|
||||||
|
[SLAVE_QDSS_CFG] = &slv_qhs_qdss_cfg,
|
||||||
|
[SLAVE_QSPI_0] = &slv_qhs_qspi_0,
|
||||||
|
[SLAVE_QSPI_1] = &slv_qhs_qspi_1,
|
||||||
|
[SLAVE_QUP_1] = &slv_qhs_qupv3_east0,
|
||||||
|
[SLAVE_QUP_2] = &slv_qhs_qupv3_east1,
|
||||||
|
[SLAVE_QUP_0] = &slv_qhs_qupv3_west,
|
||||||
|
[SLAVE_SDCC_2] = &slv_qhs_sdc2,
|
||||||
|
[SLAVE_SDCC_4] = &slv_qhs_sdc4,
|
||||||
|
[SLAVE_SECURITY] = &slv_qhs_security,
|
||||||
|
[SLAVE_SNOC_CFG] = &slv_qhs_snoc_cfg,
|
||||||
|
[SLAVE_SPSS_CFG] = &slv_qhs_spss_cfg,
|
||||||
|
[SLAVE_TCSR] = &slv_qhs_tcsr,
|
||||||
|
[SLAVE_TLMM_EAST] = &slv_qhs_tlmm_east,
|
||||||
|
[SLAVE_TLMM_SOUTH] = &slv_qhs_tlmm_south,
|
||||||
|
[SLAVE_TLMM_WEST] = &slv_qhs_tlmm_west,
|
||||||
|
[SLAVE_TSIF] = &slv_qhs_tsif,
|
||||||
|
[SLAVE_UFS_CARD_CFG] = &slv_qhs_ufs_card_cfg,
|
||||||
|
[SLAVE_UFS_MEM_0_CFG] = &slv_qhs_ufs_mem0_cfg,
|
||||||
|
[SLAVE_UFS_MEM_1_CFG] = &slv_qhs_ufs_mem1_cfg,
|
||||||
|
[SLAVE_USB3] = &slv_qhs_usb3_0,
|
||||||
|
[SLAVE_USB3_1] = &slv_qhs_usb3_1,
|
||||||
|
[SLAVE_USB3_2] = &slv_qhs_usb3_2,
|
||||||
|
[SLAVE_VENUS_CFG] = &slv_qhs_venus_cfg,
|
||||||
|
[SLAVE_VSENSE_CTRL_CFG] = &slv_qhs_vsense_ctrl_cfg,
|
||||||
|
[SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *dc_noc_nodes[] = {
|
||||||
|
[MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc,
|
||||||
|
[SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc,
|
||||||
|
[SLAVE_LLCC_CFG] = &slv_qhs_llcc,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *gem_noc_nodes[] = {
|
||||||
|
[MASTER_AMPSS_M0] = &mas_acm_apps,
|
||||||
|
[MASTER_GPU_TCU] = &mas_acm_gpu_tcu,
|
||||||
|
[MASTER_SYS_TCU] = &mas_acm_sys_tcu,
|
||||||
|
[MASTER_GEM_NOC_CFG] = &mas_qhm_gemnoc_cfg,
|
||||||
|
[MASTER_COMPUTE_NOC] = &mas_qnm_cmpnoc,
|
||||||
|
[MASTER_GRAPHICS_3D] = &mas_qnm_gpu,
|
||||||
|
[MASTER_MNOC_HF_MEM_NOC] = &mas_qnm_mnoc_hf,
|
||||||
|
[MASTER_MNOC_SF_MEM_NOC] = &mas_qnm_mnoc_sf,
|
||||||
|
[MASTER_GEM_NOC_PCIE_SNOC] = &mas_qnm_pcie,
|
||||||
|
[MASTER_SNOC_GC_MEM_NOC] = &mas_qnm_snoc_gc,
|
||||||
|
[MASTER_SNOC_SF_MEM_NOC] = &mas_qnm_snoc_sf,
|
||||||
|
[MASTER_ECC] = &mas_qxm_ecc,
|
||||||
|
[SLAVE_MSS_PROC_MS_MPU_CFG] = &slv_qhs_mdsp_ms_mpu_cfg,
|
||||||
|
[SLAVE_ECC] = &slv_qns_ecc,
|
||||||
|
[SLAVE_GEM_NOC_SNOC] = &slv_qns_gem_noc_snoc,
|
||||||
|
[SLAVE_LLCC] = &slv_qns_llcc,
|
||||||
|
[SLAVE_SERVICE_GEM_NOC] = &slv_srvc_gemnoc,
|
||||||
|
[SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *ipa_virt_nodes[] = {
|
||||||
|
[MASTER_IPA_CORE] = &mas_ipa_core_master,
|
||||||
|
[SLAVE_IPA_CORE] = &slv_ipa_core_slave,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *mc_virt_nodes[] = {
|
||||||
|
[MASTER_LLCC] = &mas_llcc_mc,
|
||||||
|
[SLAVE_EBI_CH0] = &slv_ebi,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *mmss_noc_nodes[] = {
|
||||||
|
[MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg,
|
||||||
|
[MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0,
|
||||||
|
[MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1,
|
||||||
|
[MASTER_CAMNOC_SF] = &mas_qxm_camnoc_sf,
|
||||||
|
[MASTER_MDP_PORT0] = &mas_qxm_mdp0,
|
||||||
|
[MASTER_MDP_PORT1] = &mas_qxm_mdp1,
|
||||||
|
[MASTER_ROTATOR] = &mas_qxm_rot,
|
||||||
|
[MASTER_VIDEO_P0] = &mas_qxm_venus0,
|
||||||
|
[MASTER_VIDEO_P1] = &mas_qxm_venus1,
|
||||||
|
[MASTER_VIDEO_PROC] = &mas_qxm_venus_arm9,
|
||||||
|
[SLAVE_MNOC_SF_MEM_NOC] = &slv_qns2_mem_noc,
|
||||||
|
[SLAVE_MNOC_HF_MEM_NOC] = &slv_qns_mem_noc_hf,
|
||||||
|
[SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct qcom_icc_node *system_noc_nodes[] = {
|
||||||
|
[MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg,
|
||||||
|
[A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc,
|
||||||
|
[A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc,
|
||||||
|
[MASTER_GEM_NOC_SNOC] = &mas_qnm_gemnoc,
|
||||||
|
[MASTER_PIMEM] = &mas_qxm_pimem,
|
||||||
|
[MASTER_GIC] = &mas_xm_gic,
|
||||||
|
[SLAVE_APPSS] = &slv_qhs_apss,
|
||||||
|
[SNOC_CNOC_SLV] = &slv_qns_cnoc,
|
||||||
|
[SLAVE_SNOC_GEM_NOC_GC] = &slv_qns_gemnoc_gc,
|
||||||
|
[SLAVE_SNOC_GEM_NOC_SF] = &slv_qns_gemnoc_sf,
|
||||||
|
[SLAVE_OCIMEM] = &slv_qxs_imem,
|
||||||
|
[SLAVE_PIMEM] = &slv_qxs_pimem,
|
||||||
|
[SLAVE_SERVICE_SNOC] = &slv_srvc_snoc,
|
||||||
|
[SLAVE_QDSS_STM] = &slv_xs_qdss_stm,
|
||||||
|
[SLAVE_TCU] = &slv_xs_sys_tcu_cfg,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_aggre1_noc = {
|
||||||
|
.nodes = aggre1_noc_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
|
||||||
|
.bcms = aggre1_noc_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_aggre2_noc = {
|
||||||
|
.nodes = aggre2_noc_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
|
||||||
|
.bcms = aggre2_noc_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_camnoc_virt = {
|
||||||
|
.nodes = camnoc_virt_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
|
||||||
|
.bcms = camnoc_virt_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_compute_noc = {
|
||||||
|
.nodes = compute_noc_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
|
||||||
|
.bcms = compute_noc_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(compute_noc_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_config_noc = {
|
||||||
|
.nodes = config_noc_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(config_noc_nodes),
|
||||||
|
.bcms = config_noc_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(config_noc_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_dc_noc = {
|
||||||
|
.nodes = dc_noc_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_gem_noc = {
|
||||||
|
.nodes = gem_noc_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
|
||||||
|
.bcms = gem_noc_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_ipa_virt = {
|
||||||
|
.nodes = ipa_virt_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
|
||||||
|
.bcms = ipa_virt_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_mc_virt = {
|
||||||
|
.nodes = mc_virt_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
|
||||||
|
.bcms = mc_virt_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_mmss_noc = {
|
||||||
|
.nodes = mmss_noc_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
|
||||||
|
.bcms = mmss_noc_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qcom_icc_desc sc8180x_system_noc = {
|
||||||
|
.nodes = system_noc_nodes,
|
||||||
|
.num_nodes = ARRAY_SIZE(system_noc_nodes),
|
||||||
|
.bcms = system_noc_bcms,
|
||||||
|
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||||
|
};
|
||||||
|
|
||||||
|
static int qnoc_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
const struct qcom_icc_desc *desc;
|
||||||
|
struct icc_onecell_data *data;
|
||||||
|
struct icc_provider *provider;
|
||||||
|
struct qcom_icc_node **qnodes;
|
||||||
|
struct qcom_icc_provider *qp;
|
||||||
|
struct icc_node *node;
|
||||||
|
size_t num_nodes, i;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
desc = device_get_match_data(&pdev->dev);
|
||||||
|
if (!desc)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
qnodes = desc->nodes;
|
||||||
|
num_nodes = desc->num_nodes;
|
||||||
|
|
||||||
|
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
||||||
|
if (!qp)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
||||||
|
if (!data)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
provider = &qp->provider;
|
||||||
|
provider->dev = &pdev->dev;
|
||||||
|
provider->set = qcom_icc_set;
|
||||||
|
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
||||||
|
provider->aggregate = qcom_icc_aggregate;
|
||||||
|
provider->xlate = of_icc_xlate_onecell;
|
||||||
|
INIT_LIST_HEAD(&provider->nodes);
|
||||||
|
provider->data = data;
|
||||||
|
|
||||||
|
qp->dev = &pdev->dev;
|
||||||
|
qp->bcms = desc->bcms;
|
||||||
|
qp->num_bcms = desc->num_bcms;
|
||||||
|
|
||||||
|
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
||||||
|
if (IS_ERR(qp->voter))
|
||||||
|
return PTR_ERR(qp->voter);
|
||||||
|
|
||||||
|
ret = icc_provider_add(provider);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < qp->num_bcms; i++)
|
||||||
|
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
||||||
|
|
||||||
|
for (i = 0; i < num_nodes; i++) {
|
||||||
|
size_t j;
|
||||||
|
|
||||||
|
if (!qnodes[i])
|
||||||
|
continue;
|
||||||
|
|
||||||
|
node = icc_node_create(qnodes[i]->id);
|
||||||
|
if (IS_ERR(node)) {
|
||||||
|
ret = PTR_ERR(node);
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
|
||||||
|
node->name = qnodes[i]->name;
|
||||||
|
node->data = qnodes[i];
|
||||||
|
icc_node_add(node, provider);
|
||||||
|
|
||||||
|
for (j = 0; j < qnodes[i]->num_links; j++)
|
||||||
|
icc_link_create(node, qnodes[i]->links[j]);
|
||||||
|
|
||||||
|
data->nodes[i] = node;
|
||||||
|
}
|
||||||
|
data->num_nodes = num_nodes;
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, qp);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
err:
|
||||||
|
icc_nodes_remove(provider);
|
||||||
|
icc_provider_del(provider);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qnoc_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
icc_nodes_remove(&qp->provider);
|
||||||
|
return icc_provider_del(&qp->provider);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id qnoc_of_match[] = {
|
||||||
|
{ .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc },
|
||||||
|
{ .compatible = "qcom,sc8180x-aggre2-noc", .data = &sc8180x_aggre2_noc },
|
||||||
|
{ .compatible = "qcom,sc8180x-camnoc-virt", .data = &sc8180x_camnoc_virt },
|
||||||
|
{ .compatible = "qcom,sc8180x-compute-noc", .data = &sc8180x_compute_noc, },
|
||||||
|
{ .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc },
|
||||||
|
{ .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc },
|
||||||
|
{ .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc },
|
||||||
|
{ .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt },
|
||||||
|
{ .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt },
|
||||||
|
{ .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc },
|
||||||
|
{ .compatible = "qcom,sc8180x-system-noc", .data = &sc8180x_system_noc },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||||
|
|
||||||
|
static struct platform_driver qnoc_driver = {
|
||||||
|
.probe = qnoc_probe,
|
||||||
|
.remove = qnoc_remove,
|
||||||
|
.driver = {
|
||||||
|
.name = "qnoc-sc8180x",
|
||||||
|
.of_match_table = qnoc_of_match,
|
||||||
|
.sync_state = icc_sync_state,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
module_platform_driver(qnoc_driver);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("Qualcomm sc8180x NoC driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
174
drivers/interconnect/qcom/sc8180x.h
Normal file
174
drivers/interconnect/qcom/sc8180x.h
Normal file
@ -0,0 +1,174 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Qualcomm #define SC8180X interconnect IDs
|
||||||
|
*
|
||||||
|
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8180X_H
|
||||||
|
#define __DRIVERS_INTERCONNECT_QCOM_SC8180X_H
|
||||||
|
|
||||||
|
#define SC8180X_MASTER_A1NOC_CFG 1
|
||||||
|
#define SC8180X_MASTER_UFS_CARD 2
|
||||||
|
#define SC8180X_MASTER_UFS_GEN4 3
|
||||||
|
#define SC8180X_MASTER_UFS_MEM 4
|
||||||
|
#define SC8180X_MASTER_USB3 5
|
||||||
|
#define SC8180X_MASTER_USB3_1 6
|
||||||
|
#define SC8180X_MASTER_USB3_2 7
|
||||||
|
#define SC8180X_MASTER_A2NOC_CFG 8
|
||||||
|
#define SC8180X_MASTER_QDSS_BAM 9
|
||||||
|
#define SC8180X_MASTER_QSPI_0 10
|
||||||
|
#define SC8180X_MASTER_QSPI_1 11
|
||||||
|
#define SC8180X_MASTER_QUP_0 12
|
||||||
|
#define SC8180X_MASTER_QUP_1 13
|
||||||
|
#define SC8180X_MASTER_QUP_2 14
|
||||||
|
#define SC8180X_MASTER_SENSORS_AHB 15
|
||||||
|
#define SC8180X_MASTER_CRYPTO_CORE_0 16
|
||||||
|
#define SC8180X_MASTER_IPA 17
|
||||||
|
#define SC8180X_MASTER_EMAC 18
|
||||||
|
#define SC8180X_MASTER_PCIE 19
|
||||||
|
#define SC8180X_MASTER_PCIE_1 20
|
||||||
|
#define SC8180X_MASTER_PCIE_2 21
|
||||||
|
#define SC8180X_MASTER_PCIE_3 22
|
||||||
|
#define SC8180X_MASTER_QDSS_ETR 23
|
||||||
|
#define SC8180X_MASTER_SDCC_2 24
|
||||||
|
#define SC8180X_MASTER_SDCC_4 25
|
||||||
|
#define SC8180X_MASTER_CAMNOC_HF0_UNCOMP 26
|
||||||
|
#define SC8180X_MASTER_CAMNOC_HF1_UNCOMP 27
|
||||||
|
#define SC8180X_MASTER_CAMNOC_SF_UNCOMP 28
|
||||||
|
#define SC8180X_MASTER_NPU 29
|
||||||
|
#define SC8180X_SNOC_CNOC_MAS 30
|
||||||
|
#define SC8180X_MASTER_CNOC_DC_NOC 31
|
||||||
|
#define SC8180X_MASTER_AMPSS_M0 32
|
||||||
|
#define SC8180X_MASTER_GPU_TCU 33
|
||||||
|
#define SC8180X_MASTER_SYS_TCU 34
|
||||||
|
#define SC8180X_MASTER_GEM_NOC_CFG 35
|
||||||
|
#define SC8180X_MASTER_COMPUTE_NOC 36
|
||||||
|
#define SC8180X_MASTER_GRAPHICS_3D 37
|
||||||
|
#define SC8180X_MASTER_MNOC_HF_MEM_NOC 38
|
||||||
|
#define SC8180X_MASTER_MNOC_SF_MEM_NOC 39
|
||||||
|
#define SC8180X_MASTER_GEM_NOC_PCIE_SNOC 40
|
||||||
|
#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
|
||||||
|
#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
|
||||||
|
#define SC8180X_MASTER_ECC 43
|
||||||
|
#define SC8180X_MASTER_IPA_CORE 44
|
||||||
|
#define SC8180X_MASTER_LLCC 45
|
||||||
|
#define SC8180X_MASTER_CNOC_MNOC_CFG 46
|
||||||
|
#define SC8180X_MASTER_CAMNOC_HF0 47
|
||||||
|
#define SC8180X_MASTER_CAMNOC_HF1 48
|
||||||
|
#define SC8180X_MASTER_CAMNOC_SF 49
|
||||||
|
#define SC8180X_MASTER_MDP_PORT0 50
|
||||||
|
#define SC8180X_MASTER_MDP_PORT1 51
|
||||||
|
#define SC8180X_MASTER_ROTATOR 52
|
||||||
|
#define SC8180X_MASTER_VIDEO_P0 53
|
||||||
|
#define SC8180X_MASTER_VIDEO_P1 54
|
||||||
|
#define SC8180X_MASTER_VIDEO_PROC 55
|
||||||
|
#define SC8180X_MASTER_SNOC_CFG 56
|
||||||
|
#define SC8180X_A1NOC_SNOC_MAS 57
|
||||||
|
#define SC8180X_A2NOC_SNOC_MAS 58
|
||||||
|
#define SC8180X_MASTER_GEM_NOC_SNOC 59
|
||||||
|
#define SC8180X_MASTER_PIMEM 60
|
||||||
|
#define SC8180X_MASTER_GIC 61
|
||||||
|
#define SC8180X_MASTER_MNOC_HF_MEM_NOC_DISPLAY 62
|
||||||
|
#define SC8180X_MASTER_MNOC_SF_MEM_NOC_DISPLAY 63
|
||||||
|
#define SC8180X_MASTER_LLCC_DISPLAY 64
|
||||||
|
#define SC8180X_MASTER_MDP_PORT0_DISPLAY 65
|
||||||
|
#define SC8180X_MASTER_MDP_PORT1_DISPLAY 66
|
||||||
|
#define SC8180X_MASTER_ROTATOR_DISPLAY 67
|
||||||
|
#define SC8180X_A1NOC_SNOC_SLV 68
|
||||||
|
#define SC8180X_SLAVE_SERVICE_A1NOC 69
|
||||||
|
#define SC8180X_A2NOC_SNOC_SLV 70
|
||||||
|
#define SC8180X_SLAVE_ANOC_PCIE_GEM_NOC 71
|
||||||
|
#define SC8180X_SLAVE_SERVICE_A2NOC 72
|
||||||
|
#define SC8180X_SLAVE_CAMNOC_UNCOMP 73
|
||||||
|
#define SC8180X_SLAVE_CDSP_MEM_NOC 74
|
||||||
|
#define SC8180X_SLAVE_A1NOC_CFG 75
|
||||||
|
#define SC8180X_SLAVE_A2NOC_CFG 76
|
||||||
|
#define SC8180X_SLAVE_AHB2PHY_CENTER 77
|
||||||
|
#define SC8180X_SLAVE_AHB2PHY_EAST 78
|
||||||
|
#define SC8180X_SLAVE_AHB2PHY_WEST 79
|
||||||
|
#define SC8180X_SLAVE_AHB2PHY_SOUTH 80
|
||||||
|
#define SC8180X_SLAVE_AOP 81
|
||||||
|
#define SC8180X_SLAVE_AOSS 82
|
||||||
|
#define SC8180X_SLAVE_CAMERA_CFG 83
|
||||||
|
#define SC8180X_SLAVE_CLK_CTL 84
|
||||||
|
#define SC8180X_SLAVE_CDSP_CFG 85
|
||||||
|
#define SC8180X_SLAVE_RBCPR_CX_CFG 86
|
||||||
|
#define SC8180X_SLAVE_RBCPR_MMCX_CFG 87
|
||||||
|
#define SC8180X_SLAVE_RBCPR_MX_CFG 88
|
||||||
|
#define SC8180X_SLAVE_CRYPTO_0_CFG 89
|
||||||
|
#define SC8180X_SLAVE_CNOC_DDRSS 90
|
||||||
|
#define SC8180X_SLAVE_DISPLAY_CFG 91
|
||||||
|
#define SC8180X_SLAVE_EMAC_CFG 92
|
||||||
|
#define SC8180X_SLAVE_GLM 93
|
||||||
|
#define SC8180X_SLAVE_GRAPHICS_3D_CFG 94
|
||||||
|
#define SC8180X_SLAVE_IMEM_CFG 95
|
||||||
|
#define SC8180X_SLAVE_IPA_CFG 96
|
||||||
|
#define SC8180X_SLAVE_CNOC_MNOC_CFG 97
|
||||||
|
#define SC8180X_SLAVE_NPU_CFG 98
|
||||||
|
#define SC8180X_SLAVE_PCIE_0_CFG 99
|
||||||
|
#define SC8180X_SLAVE_PCIE_1_CFG 100
|
||||||
|
#define SC8180X_SLAVE_PCIE_2_CFG 101
|
||||||
|
#define SC8180X_SLAVE_PCIE_3_CFG 102
|
||||||
|
#define SC8180X_SLAVE_PDM 103
|
||||||
|
#define SC8180X_SLAVE_PIMEM_CFG 104
|
||||||
|
#define SC8180X_SLAVE_PRNG 105
|
||||||
|
#define SC8180X_SLAVE_QDSS_CFG 106
|
||||||
|
#define SC8180X_SLAVE_QSPI_0 107
|
||||||
|
#define SC8180X_SLAVE_QSPI_1 108
|
||||||
|
#define SC8180X_SLAVE_QUP_1 109
|
||||||
|
#define SC8180X_SLAVE_QUP_2 110
|
||||||
|
#define SC8180X_SLAVE_QUP_0 111
|
||||||
|
#define SC8180X_SLAVE_SDCC_2 112
|
||||||
|
#define SC8180X_SLAVE_SDCC_4 113
|
||||||
|
#define SC8180X_SLAVE_SECURITY 114
|
||||||
|
#define SC8180X_SLAVE_SNOC_CFG 115
|
||||||
|
#define SC8180X_SLAVE_SPSS_CFG 116
|
||||||
|
#define SC8180X_SLAVE_TCSR 117
|
||||||
|
#define SC8180X_SLAVE_TLMM_EAST 118
|
||||||
|
#define SC8180X_SLAVE_TLMM_SOUTH 119
|
||||||
|
#define SC8180X_SLAVE_TLMM_WEST 120
|
||||||
|
#define SC8180X_SLAVE_TSIF 121
|
||||||
|
#define SC8180X_SLAVE_UFS_CARD_CFG 122
|
||||||
|
#define SC8180X_SLAVE_UFS_MEM_0_CFG 123
|
||||||
|
#define SC8180X_SLAVE_UFS_MEM_1_CFG 124
|
||||||
|
#define SC8180X_SLAVE_USB3 125
|
||||||
|
#define SC8180X_SLAVE_USB3_1 126
|
||||||
|
#define SC8180X_SLAVE_USB3_2 127
|
||||||
|
#define SC8180X_SLAVE_VENUS_CFG 128
|
||||||
|
#define SC8180X_SLAVE_VSENSE_CTRL_CFG 129
|
||||||
|
#define SC8180X_SLAVE_SERVICE_CNOC 130
|
||||||
|
#define SC8180X_SLAVE_GEM_NOC_CFG 131
|
||||||
|
#define SC8180X_SLAVE_LLCC_CFG 132
|
||||||
|
#define SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG 133
|
||||||
|
#define SC8180X_SLAVE_ECC 134
|
||||||
|
#define SC8180X_SLAVE_GEM_NOC_SNOC 135
|
||||||
|
#define SC8180X_SLAVE_LLCC 136
|
||||||
|
#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
|
||||||
|
#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
|
||||||
|
#define SC8180X_SLAVE_IPA_CORE 139
|
||||||
|
#define SC8180X_SLAVE_EBI_CH0 140
|
||||||
|
#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
|
||||||
|
#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142
|
||||||
|
#define SC8180X_SLAVE_SERVICE_MNOC 143
|
||||||
|
#define SC8180X_SLAVE_APPSS 144
|
||||||
|
#define SC8180X_SNOC_CNOC_SLV 145
|
||||||
|
#define SC8180X_SLAVE_SNOC_GEM_NOC_GC 146
|
||||||
|
#define SC8180X_SLAVE_SNOC_GEM_NOC_SF 147
|
||||||
|
#define SC8180X_SLAVE_OCIMEM 148
|
||||||
|
#define SC8180X_SLAVE_PIMEM 149
|
||||||
|
#define SC8180X_SLAVE_SERVICE_SNOC 150
|
||||||
|
#define SC8180X_SLAVE_PCIE_0 151
|
||||||
|
#define SC8180X_SLAVE_PCIE_1 152
|
||||||
|
#define SC8180X_SLAVE_PCIE_2 153
|
||||||
|
#define SC8180X_SLAVE_PCIE_3 154
|
||||||
|
#define SC8180X_SLAVE_QDSS_STM 155
|
||||||
|
#define SC8180X_SLAVE_TCU 156
|
||||||
|
#define SC8180X_SLAVE_LLCC_DISPLAY 157
|
||||||
|
#define SC8180X_SLAVE_EBI_CH0_DISPLAY 158
|
||||||
|
#define SC8180X_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 159
|
||||||
|
#define SC8180X_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 160
|
||||||
|
#define SC8180X_MASTER_OSM_L3_APPS 161
|
||||||
|
#define SC8180X_SLAVE_OSM_L3 162
|
||||||
|
|
||||||
|
#endif
|
@ -440,101 +440,6 @@ static const struct qcom_icc_desc sdm845_system_noc = {
|
|||||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||||
};
|
};
|
||||||
|
|
||||||
static int qnoc_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
const struct qcom_icc_desc *desc;
|
|
||||||
struct icc_onecell_data *data;
|
|
||||||
struct icc_provider *provider;
|
|
||||||
struct qcom_icc_node **qnodes;
|
|
||||||
struct qcom_icc_provider *qp;
|
|
||||||
struct icc_node *node;
|
|
||||||
size_t num_nodes, i;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
desc = device_get_match_data(&pdev->dev);
|
|
||||||
if (!desc)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
qnodes = desc->nodes;
|
|
||||||
num_nodes = desc->num_nodes;
|
|
||||||
|
|
||||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
|
||||||
if (!qp)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
data = devm_kzalloc(&pdev->dev, struct_size(data, nodes, num_nodes),
|
|
||||||
GFP_KERNEL);
|
|
||||||
if (!data)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
provider = &qp->provider;
|
|
||||||
provider->dev = &pdev->dev;
|
|
||||||
provider->set = qcom_icc_set;
|
|
||||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
|
||||||
provider->aggregate = qcom_icc_aggregate;
|
|
||||||
provider->xlate_extended = qcom_icc_xlate_extended;
|
|
||||||
INIT_LIST_HEAD(&provider->nodes);
|
|
||||||
provider->data = data;
|
|
||||||
|
|
||||||
qp->dev = &pdev->dev;
|
|
||||||
qp->bcms = desc->bcms;
|
|
||||||
qp->num_bcms = desc->num_bcms;
|
|
||||||
|
|
||||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
|
||||||
if (IS_ERR(qp->voter)) {
|
|
||||||
dev_err(&pdev->dev, "bcm_voter err:%ld\n", PTR_ERR(qp->voter));
|
|
||||||
return PTR_ERR(qp->voter);
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = icc_provider_add(provider);
|
|
||||||
if (ret) {
|
|
||||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < qp->num_bcms; i++)
|
|
||||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
|
||||||
|
|
||||||
for (i = 0; i < num_nodes; i++) {
|
|
||||||
size_t j;
|
|
||||||
|
|
||||||
if (!qnodes[i])
|
|
||||||
continue;
|
|
||||||
|
|
||||||
node = icc_node_create(qnodes[i]->id);
|
|
||||||
if (IS_ERR(node)) {
|
|
||||||
ret = PTR_ERR(node);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
node->name = qnodes[i]->name;
|
|
||||||
node->data = qnodes[i];
|
|
||||||
icc_node_add(node, provider);
|
|
||||||
|
|
||||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
|
||||||
icc_link_create(node, qnodes[i]->links[j]);
|
|
||||||
|
|
||||||
data->nodes[i] = node;
|
|
||||||
}
|
|
||||||
data->num_nodes = num_nodes;
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, qp);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
err:
|
|
||||||
icc_nodes_remove(provider);
|
|
||||||
icc_provider_del(provider);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int qnoc_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
icc_nodes_remove(&qp->provider);
|
|
||||||
return icc_provider_del(&qp->provider);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id qnoc_of_match[] = {
|
static const struct of_device_id qnoc_of_match[] = {
|
||||||
{ .compatible = "qcom,sdm845-aggre1-noc",
|
{ .compatible = "qcom,sdm845-aggre1-noc",
|
||||||
.data = &sdm845_aggre1_noc},
|
.data = &sdm845_aggre1_noc},
|
||||||
@ -557,8 +462,8 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||||
|
|
||||||
static struct platform_driver qnoc_driver = {
|
static struct platform_driver qnoc_driver = {
|
||||||
.probe = qnoc_probe,
|
.probe = qcom_icc_rpmh_probe,
|
||||||
.remove = qnoc_remove,
|
.remove = qcom_icc_rpmh_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "qnoc-sdm845",
|
.name = "qnoc-sdm845",
|
||||||
.of_match_table = qnoc_of_match,
|
.of_match_table = qnoc_of_match,
|
||||||
|
@ -235,98 +235,6 @@ static const struct qcom_icc_desc sdx55_ipa_virt = {
|
|||||||
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
|
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
|
||||||
};
|
};
|
||||||
|
|
||||||
static int qnoc_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
const struct qcom_icc_desc *desc;
|
|
||||||
struct icc_onecell_data *data;
|
|
||||||
struct icc_provider *provider;
|
|
||||||
struct qcom_icc_node **qnodes;
|
|
||||||
struct qcom_icc_provider *qp;
|
|
||||||
struct icc_node *node;
|
|
||||||
size_t num_nodes, i;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
desc = device_get_match_data(&pdev->dev);
|
|
||||||
if (!desc)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
qnodes = desc->nodes;
|
|
||||||
num_nodes = desc->num_nodes;
|
|
||||||
|
|
||||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
|
||||||
if (!qp)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
|
||||||
if (!data)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
provider = &qp->provider;
|
|
||||||
provider->dev = &pdev->dev;
|
|
||||||
provider->set = qcom_icc_set;
|
|
||||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
|
||||||
provider->aggregate = qcom_icc_aggregate;
|
|
||||||
provider->xlate = of_icc_xlate_onecell;
|
|
||||||
INIT_LIST_HEAD(&provider->nodes);
|
|
||||||
provider->data = data;
|
|
||||||
|
|
||||||
qp->dev = &pdev->dev;
|
|
||||||
qp->bcms = desc->bcms;
|
|
||||||
qp->num_bcms = desc->num_bcms;
|
|
||||||
|
|
||||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
|
||||||
if (IS_ERR(qp->voter))
|
|
||||||
return PTR_ERR(qp->voter);
|
|
||||||
|
|
||||||
ret = icc_provider_add(provider);
|
|
||||||
if (ret) {
|
|
||||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < qp->num_bcms; i++)
|
|
||||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
|
||||||
|
|
||||||
for (i = 0; i < num_nodes; i++) {
|
|
||||||
size_t j;
|
|
||||||
|
|
||||||
if (!qnodes[i])
|
|
||||||
continue;
|
|
||||||
|
|
||||||
node = icc_node_create(qnodes[i]->id);
|
|
||||||
if (IS_ERR(node)) {
|
|
||||||
ret = PTR_ERR(node);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
node->name = qnodes[i]->name;
|
|
||||||
node->data = qnodes[i];
|
|
||||||
icc_node_add(node, provider);
|
|
||||||
|
|
||||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
|
||||||
icc_link_create(node, qnodes[i]->links[j]);
|
|
||||||
|
|
||||||
data->nodes[i] = node;
|
|
||||||
}
|
|
||||||
data->num_nodes = num_nodes;
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, qp);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
err:
|
|
||||||
icc_nodes_remove(provider);
|
|
||||||
icc_provider_del(provider);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int qnoc_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
icc_nodes_remove(&qp->provider);
|
|
||||||
return icc_provider_del(&qp->provider);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id qnoc_of_match[] = {
|
static const struct of_device_id qnoc_of_match[] = {
|
||||||
{ .compatible = "qcom,sdx55-mc-virt",
|
{ .compatible = "qcom,sdx55-mc-virt",
|
||||||
.data = &sdx55_mc_virt},
|
.data = &sdx55_mc_virt},
|
||||||
@ -341,8 +249,8 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||||
|
|
||||||
static struct platform_driver qnoc_driver = {
|
static struct platform_driver qnoc_driver = {
|
||||||
.probe = qnoc_probe,
|
.probe = qcom_icc_rpmh_probe,
|
||||||
.remove = qnoc_remove,
|
.remove = qcom_icc_rpmh_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "qnoc-sdx55",
|
.name = "qnoc-sdx55",
|
||||||
.of_match_table = qnoc_of_match,
|
.of_match_table = qnoc_of_match,
|
||||||
|
@ -502,98 +502,6 @@ static struct qcom_icc_desc sm8150_system_noc = {
|
|||||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||||
};
|
};
|
||||||
|
|
||||||
static int qnoc_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
const struct qcom_icc_desc *desc;
|
|
||||||
struct icc_onecell_data *data;
|
|
||||||
struct icc_provider *provider;
|
|
||||||
struct qcom_icc_node **qnodes;
|
|
||||||
struct qcom_icc_provider *qp;
|
|
||||||
struct icc_node *node;
|
|
||||||
size_t num_nodes, i;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
desc = device_get_match_data(&pdev->dev);
|
|
||||||
if (!desc)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
qnodes = desc->nodes;
|
|
||||||
num_nodes = desc->num_nodes;
|
|
||||||
|
|
||||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
|
||||||
if (!qp)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
|
||||||
if (!data)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
provider = &qp->provider;
|
|
||||||
provider->dev = &pdev->dev;
|
|
||||||
provider->set = qcom_icc_set;
|
|
||||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
|
||||||
provider->aggregate = qcom_icc_aggregate;
|
|
||||||
provider->xlate = of_icc_xlate_onecell;
|
|
||||||
INIT_LIST_HEAD(&provider->nodes);
|
|
||||||
provider->data = data;
|
|
||||||
|
|
||||||
qp->dev = &pdev->dev;
|
|
||||||
qp->bcms = desc->bcms;
|
|
||||||
qp->num_bcms = desc->num_bcms;
|
|
||||||
|
|
||||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
|
||||||
if (IS_ERR(qp->voter))
|
|
||||||
return PTR_ERR(qp->voter);
|
|
||||||
|
|
||||||
ret = icc_provider_add(provider);
|
|
||||||
if (ret) {
|
|
||||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < qp->num_bcms; i++)
|
|
||||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
|
||||||
|
|
||||||
for (i = 0; i < num_nodes; i++) {
|
|
||||||
size_t j;
|
|
||||||
|
|
||||||
if (!qnodes[i])
|
|
||||||
continue;
|
|
||||||
|
|
||||||
node = icc_node_create(qnodes[i]->id);
|
|
||||||
if (IS_ERR(node)) {
|
|
||||||
ret = PTR_ERR(node);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
node->name = qnodes[i]->name;
|
|
||||||
node->data = qnodes[i];
|
|
||||||
icc_node_add(node, provider);
|
|
||||||
|
|
||||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
|
||||||
icc_link_create(node, qnodes[i]->links[j]);
|
|
||||||
|
|
||||||
data->nodes[i] = node;
|
|
||||||
}
|
|
||||||
data->num_nodes = num_nodes;
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, qp);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
err:
|
|
||||||
icc_nodes_remove(provider);
|
|
||||||
icc_provider_del(provider);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int qnoc_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
icc_nodes_remove(&qp->provider);
|
|
||||||
return icc_provider_del(&qp->provider);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id qnoc_of_match[] = {
|
static const struct of_device_id qnoc_of_match[] = {
|
||||||
{ .compatible = "qcom,sm8150-aggre1-noc",
|
{ .compatible = "qcom,sm8150-aggre1-noc",
|
||||||
.data = &sm8150_aggre1_noc},
|
.data = &sm8150_aggre1_noc},
|
||||||
@ -622,8 +530,8 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||||
|
|
||||||
static struct platform_driver qnoc_driver = {
|
static struct platform_driver qnoc_driver = {
|
||||||
.probe = qnoc_probe,
|
.probe = qcom_icc_rpmh_probe,
|
||||||
.remove = qnoc_remove,
|
.remove = qcom_icc_rpmh_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "qnoc-sm8150",
|
.name = "qnoc-sm8150",
|
||||||
.of_match_table = qnoc_of_match,
|
.of_match_table = qnoc_of_match,
|
||||||
|
@ -518,98 +518,6 @@ static struct qcom_icc_desc sm8250_system_noc = {
|
|||||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||||
};
|
};
|
||||||
|
|
||||||
static int qnoc_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
const struct qcom_icc_desc *desc;
|
|
||||||
struct icc_onecell_data *data;
|
|
||||||
struct icc_provider *provider;
|
|
||||||
struct qcom_icc_node **qnodes;
|
|
||||||
struct qcom_icc_provider *qp;
|
|
||||||
struct icc_node *node;
|
|
||||||
size_t num_nodes, i;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
desc = device_get_match_data(&pdev->dev);
|
|
||||||
if (!desc)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
qnodes = desc->nodes;
|
|
||||||
num_nodes = desc->num_nodes;
|
|
||||||
|
|
||||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
|
||||||
if (!qp)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
|
||||||
if (!data)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
provider = &qp->provider;
|
|
||||||
provider->dev = &pdev->dev;
|
|
||||||
provider->set = qcom_icc_set;
|
|
||||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
|
||||||
provider->aggregate = qcom_icc_aggregate;
|
|
||||||
provider->xlate = of_icc_xlate_onecell;
|
|
||||||
INIT_LIST_HEAD(&provider->nodes);
|
|
||||||
provider->data = data;
|
|
||||||
|
|
||||||
qp->dev = &pdev->dev;
|
|
||||||
qp->bcms = desc->bcms;
|
|
||||||
qp->num_bcms = desc->num_bcms;
|
|
||||||
|
|
||||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
|
||||||
if (IS_ERR(qp->voter))
|
|
||||||
return PTR_ERR(qp->voter);
|
|
||||||
|
|
||||||
ret = icc_provider_add(provider);
|
|
||||||
if (ret) {
|
|
||||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < qp->num_bcms; i++)
|
|
||||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
|
||||||
|
|
||||||
for (i = 0; i < num_nodes; i++) {
|
|
||||||
size_t j;
|
|
||||||
|
|
||||||
if (!qnodes[i])
|
|
||||||
continue;
|
|
||||||
|
|
||||||
node = icc_node_create(qnodes[i]->id);
|
|
||||||
if (IS_ERR(node)) {
|
|
||||||
ret = PTR_ERR(node);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
node->name = qnodes[i]->name;
|
|
||||||
node->data = qnodes[i];
|
|
||||||
icc_node_add(node, provider);
|
|
||||||
|
|
||||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
|
||||||
icc_link_create(node, qnodes[i]->links[j]);
|
|
||||||
|
|
||||||
data->nodes[i] = node;
|
|
||||||
}
|
|
||||||
data->num_nodes = num_nodes;
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, qp);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
err:
|
|
||||||
icc_nodes_remove(provider);
|
|
||||||
icc_provider_del(provider);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int qnoc_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
icc_nodes_remove(&qp->provider);
|
|
||||||
return icc_provider_del(&qp->provider);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id qnoc_of_match[] = {
|
static const struct of_device_id qnoc_of_match[] = {
|
||||||
{ .compatible = "qcom,sm8250-aggre1-noc",
|
{ .compatible = "qcom,sm8250-aggre1-noc",
|
||||||
.data = &sm8250_aggre1_noc},
|
.data = &sm8250_aggre1_noc},
|
||||||
@ -638,8 +546,8 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||||
|
|
||||||
static struct platform_driver qnoc_driver = {
|
static struct platform_driver qnoc_driver = {
|
||||||
.probe = qnoc_probe,
|
.probe = qcom_icc_rpmh_probe,
|
||||||
.remove = qnoc_remove,
|
.remove = qcom_icc_rpmh_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "qnoc-sm8250",
|
.name = "qnoc-sm8250",
|
||||||
.of_match_table = qnoc_of_match,
|
.of_match_table = qnoc_of_match,
|
||||||
|
@ -510,99 +510,6 @@ static struct qcom_icc_desc sm8350_system_noc = {
|
|||||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||||
};
|
};
|
||||||
|
|
||||||
static int qnoc_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
const struct qcom_icc_desc *desc;
|
|
||||||
struct icc_onecell_data *data;
|
|
||||||
struct icc_provider *provider;
|
|
||||||
struct qcom_icc_node **qnodes;
|
|
||||||
struct qcom_icc_provider *qp;
|
|
||||||
struct icc_node *node;
|
|
||||||
size_t num_nodes, i;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
desc = of_device_get_match_data(&pdev->dev);
|
|
||||||
if (!desc)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
qnodes = desc->nodes;
|
|
||||||
num_nodes = desc->num_nodes;
|
|
||||||
|
|
||||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
|
||||||
if (!qp)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
|
||||||
if (!data)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
provider = &qp->provider;
|
|
||||||
provider->dev = &pdev->dev;
|
|
||||||
provider->set = qcom_icc_set;
|
|
||||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
|
||||||
provider->aggregate = qcom_icc_aggregate;
|
|
||||||
provider->xlate = of_icc_xlate_onecell;
|
|
||||||
INIT_LIST_HEAD(&provider->nodes);
|
|
||||||
provider->data = data;
|
|
||||||
|
|
||||||
qp->dev = &pdev->dev;
|
|
||||||
qp->bcms = desc->bcms;
|
|
||||||
qp->num_bcms = desc->num_bcms;
|
|
||||||
|
|
||||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
|
||||||
if (IS_ERR(qp->voter))
|
|
||||||
return PTR_ERR(qp->voter);
|
|
||||||
|
|
||||||
ret = icc_provider_add(provider);
|
|
||||||
if (ret) {
|
|
||||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < qp->num_bcms; i++)
|
|
||||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
|
||||||
|
|
||||||
for (i = 0; i < num_nodes; i++) {
|
|
||||||
size_t j;
|
|
||||||
|
|
||||||
if (!qnodes[i])
|
|
||||||
continue;
|
|
||||||
|
|
||||||
node = icc_node_create(qnodes[i]->id);
|
|
||||||
if (IS_ERR(node)) {
|
|
||||||
ret = PTR_ERR(node);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
node->name = qnodes[i]->name;
|
|
||||||
node->data = qnodes[i];
|
|
||||||
icc_node_add(node, provider);
|
|
||||||
|
|
||||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
|
||||||
icc_link_create(node, qnodes[i]->links[j]);
|
|
||||||
|
|
||||||
data->nodes[i] = node;
|
|
||||||
}
|
|
||||||
data->num_nodes = num_nodes;
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, qp);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
err:
|
|
||||||
icc_nodes_remove(provider);
|
|
||||||
icc_provider_del(provider);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int qnoc_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
icc_nodes_remove(&qp->provider);
|
|
||||||
return icc_provider_del(&qp->provider);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id qnoc_of_match[] = {
|
static const struct of_device_id qnoc_of_match[] = {
|
||||||
{ .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
|
{ .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
|
||||||
{ .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
|
{ .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
|
||||||
@ -619,8 +526,8 @@ static const struct of_device_id qnoc_of_match[] = {
|
|||||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||||
|
|
||||||
static struct platform_driver qnoc_driver = {
|
static struct platform_driver qnoc_driver = {
|
||||||
.probe = qnoc_probe,
|
.probe = qcom_icc_rpmh_probe,
|
||||||
.remove = qnoc_remove,
|
.remove = qcom_icc_rpmh_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "qnoc-sm8350",
|
.name = "qnoc-sm8350",
|
||||||
.of_match_table = qnoc_of_match,
|
.of_match_table = qnoc_of_match,
|
||||||
|
185
include/dt-bindings/interconnect/qcom,sc8180x.h
Normal file
185
include/dt-bindings/interconnect/qcom,sc8180x.h
Normal file
@ -0,0 +1,185 @@
|
|||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||||
|
/*
|
||||||
|
* Qualcomm SC8180x interconnect IDs
|
||||||
|
*
|
||||||
|
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC8180X_H
|
||||||
|
#define __DT_BINDINGS_INTERCONNECT_QCOM_SC8180X_H
|
||||||
|
|
||||||
|
#define MASTER_A1NOC_CFG 0
|
||||||
|
#define MASTER_UFS_CARD 1
|
||||||
|
#define MASTER_UFS_GEN4 2
|
||||||
|
#define MASTER_UFS_MEM 3
|
||||||
|
#define MASTER_USB3 4
|
||||||
|
#define MASTER_USB3_1 5
|
||||||
|
#define MASTER_USB3_2 6
|
||||||
|
#define A1NOC_SNOC_SLV 7
|
||||||
|
#define SLAVE_SERVICE_A1NOC 8
|
||||||
|
|
||||||
|
#define MASTER_A2NOC_CFG 0
|
||||||
|
#define MASTER_QDSS_BAM 1
|
||||||
|
#define MASTER_QSPI_0 2
|
||||||
|
#define MASTER_QSPI_1 3
|
||||||
|
#define MASTER_QUP_0 4
|
||||||
|
#define MASTER_QUP_1 5
|
||||||
|
#define MASTER_QUP_2 6
|
||||||
|
#define MASTER_SENSORS_AHB 7
|
||||||
|
#define MASTER_CRYPTO_CORE_0 8
|
||||||
|
#define MASTER_IPA 9
|
||||||
|
#define MASTER_EMAC 10
|
||||||
|
#define MASTER_PCIE 11
|
||||||
|
#define MASTER_PCIE_1 12
|
||||||
|
#define MASTER_PCIE_2 13
|
||||||
|
#define MASTER_PCIE_3 14
|
||||||
|
#define MASTER_QDSS_ETR 15
|
||||||
|
#define MASTER_SDCC_2 16
|
||||||
|
#define MASTER_SDCC_4 17
|
||||||
|
#define A2NOC_SNOC_SLV 18
|
||||||
|
#define SLAVE_ANOC_PCIE_GEM_NOC 19
|
||||||
|
#define SLAVE_SERVICE_A2NOC 20
|
||||||
|
|
||||||
|
#define MASTER_CAMNOC_HF0_UNCOMP 0
|
||||||
|
#define MASTER_CAMNOC_HF1_UNCOMP 1
|
||||||
|
#define MASTER_CAMNOC_SF_UNCOMP 2
|
||||||
|
#define SLAVE_CAMNOC_UNCOMP 3
|
||||||
|
|
||||||
|
#define MASTER_NPU 0
|
||||||
|
#define SLAVE_CDSP_MEM_NOC 1
|
||||||
|
|
||||||
|
#define SNOC_CNOC_MAS 0
|
||||||
|
#define SLAVE_A1NOC_CFG 1
|
||||||
|
#define SLAVE_A2NOC_CFG 2
|
||||||
|
#define SLAVE_AHB2PHY_CENTER 3
|
||||||
|
#define SLAVE_AHB2PHY_EAST 4
|
||||||
|
#define SLAVE_AHB2PHY_WEST 5
|
||||||
|
#define SLAVE_AHB2PHY_SOUTH 6
|
||||||
|
#define SLAVE_AOP 7
|
||||||
|
#define SLAVE_AOSS 8
|
||||||
|
#define SLAVE_CAMERA_CFG 9
|
||||||
|
#define SLAVE_CLK_CTL 10
|
||||||
|
#define SLAVE_CDSP_CFG 11
|
||||||
|
#define SLAVE_RBCPR_CX_CFG 12
|
||||||
|
#define SLAVE_RBCPR_MMCX_CFG 13
|
||||||
|
#define SLAVE_RBCPR_MX_CFG 14
|
||||||
|
#define SLAVE_CRYPTO_0_CFG 15
|
||||||
|
#define SLAVE_CNOC_DDRSS 16
|
||||||
|
#define SLAVE_DISPLAY_CFG 17
|
||||||
|
#define SLAVE_EMAC_CFG 18
|
||||||
|
#define SLAVE_GLM 19
|
||||||
|
#define SLAVE_GRAPHICS_3D_CFG 20
|
||||||
|
#define SLAVE_IMEM_CFG 21
|
||||||
|
#define SLAVE_IPA_CFG 22
|
||||||
|
#define SLAVE_CNOC_MNOC_CFG 23
|
||||||
|
#define SLAVE_NPU_CFG 24
|
||||||
|
#define SLAVE_PCIE_0_CFG 25
|
||||||
|
#define SLAVE_PCIE_1_CFG 26
|
||||||
|
#define SLAVE_PCIE_2_CFG 27
|
||||||
|
#define SLAVE_PCIE_3_CFG 28
|
||||||
|
#define SLAVE_PDM 29
|
||||||
|
#define SLAVE_PIMEM_CFG 30
|
||||||
|
#define SLAVE_PRNG 31
|
||||||
|
#define SLAVE_QDSS_CFG 32
|
||||||
|
#define SLAVE_QSPI_0 33
|
||||||
|
#define SLAVE_QSPI_1 34
|
||||||
|
#define SLAVE_QUP_1 35
|
||||||
|
#define SLAVE_QUP_2 36
|
||||||
|
#define SLAVE_QUP_0 37
|
||||||
|
#define SLAVE_SDCC_2 38
|
||||||
|
#define SLAVE_SDCC_4 39
|
||||||
|
#define SLAVE_SECURITY 40
|
||||||
|
#define SLAVE_SNOC_CFG 41
|
||||||
|
#define SLAVE_SPSS_CFG 42
|
||||||
|
#define SLAVE_TCSR 43
|
||||||
|
#define SLAVE_TLMM_EAST 44
|
||||||
|
#define SLAVE_TLMM_SOUTH 45
|
||||||
|
#define SLAVE_TLMM_WEST 46
|
||||||
|
#define SLAVE_TSIF 47
|
||||||
|
#define SLAVE_UFS_CARD_CFG 48
|
||||||
|
#define SLAVE_UFS_MEM_0_CFG 49
|
||||||
|
#define SLAVE_UFS_MEM_1_CFG 50
|
||||||
|
#define SLAVE_USB3 51
|
||||||
|
#define SLAVE_USB3_1 52
|
||||||
|
#define SLAVE_USB3_2 53
|
||||||
|
#define SLAVE_VENUS_CFG 54
|
||||||
|
#define SLAVE_VSENSE_CTRL_CFG 55
|
||||||
|
#define SLAVE_SERVICE_CNOC 56
|
||||||
|
|
||||||
|
#define MASTER_CNOC_DC_NOC 0
|
||||||
|
#define SLAVE_GEM_NOC_CFG 1
|
||||||
|
#define SLAVE_LLCC_CFG 2
|
||||||
|
|
||||||
|
#define MASTER_AMPSS_M0 0
|
||||||
|
#define MASTER_GPU_TCU 1
|
||||||
|
#define MASTER_SYS_TCU 2
|
||||||
|
#define MASTER_GEM_NOC_CFG 3
|
||||||
|
#define MASTER_COMPUTE_NOC 4
|
||||||
|
#define MASTER_GRAPHICS_3D 5
|
||||||
|
#define MASTER_MNOC_HF_MEM_NOC 6
|
||||||
|
#define MASTER_MNOC_SF_MEM_NOC 7
|
||||||
|
#define MASTER_GEM_NOC_PCIE_SNOC 8
|
||||||
|
#define MASTER_SNOC_GC_MEM_NOC 9
|
||||||
|
#define MASTER_SNOC_SF_MEM_NOC 10
|
||||||
|
#define MASTER_ECC 11
|
||||||
|
#define SLAVE_MSS_PROC_MS_MPU_CFG 12
|
||||||
|
#define SLAVE_ECC 13
|
||||||
|
#define SLAVE_GEM_NOC_SNOC 14
|
||||||
|
#define SLAVE_LLCC 15
|
||||||
|
#define SLAVE_SERVICE_GEM_NOC 16
|
||||||
|
#define SLAVE_SERVICE_GEM_NOC_1 17
|
||||||
|
|
||||||
|
#define MASTER_IPA_CORE 0
|
||||||
|
#define SLAVE_IPA_CORE 1
|
||||||
|
|
||||||
|
#define MASTER_LLCC 0
|
||||||
|
#define SLAVE_EBI_CH0 1
|
||||||
|
|
||||||
|
#define MASTER_CNOC_MNOC_CFG 0
|
||||||
|
#define MASTER_CAMNOC_HF0 1
|
||||||
|
#define MASTER_CAMNOC_HF1 2
|
||||||
|
#define MASTER_CAMNOC_SF 3
|
||||||
|
#define MASTER_MDP_PORT0 4
|
||||||
|
#define MASTER_MDP_PORT1 5
|
||||||
|
#define MASTER_ROTATOR 6
|
||||||
|
#define MASTER_VIDEO_P0 7
|
||||||
|
#define MASTER_VIDEO_P1 8
|
||||||
|
#define MASTER_VIDEO_PROC 9
|
||||||
|
#define SLAVE_MNOC_SF_MEM_NOC 10
|
||||||
|
#define SLAVE_MNOC_HF_MEM_NOC 11
|
||||||
|
#define SLAVE_SERVICE_MNOC 12
|
||||||
|
|
||||||
|
#define MASTER_SNOC_CFG 0
|
||||||
|
#define A1NOC_SNOC_MAS 1
|
||||||
|
#define A2NOC_SNOC_MAS 2
|
||||||
|
#define MASTER_GEM_NOC_SNOC 3
|
||||||
|
#define MASTER_PIMEM 4
|
||||||
|
#define MASTER_GIC 5
|
||||||
|
#define SLAVE_APPSS 6
|
||||||
|
#define SNOC_CNOC_SLV 7
|
||||||
|
#define SLAVE_SNOC_GEM_NOC_GC 8
|
||||||
|
#define SLAVE_SNOC_GEM_NOC_SF 9
|
||||||
|
#define SLAVE_OCIMEM 10
|
||||||
|
#define SLAVE_PIMEM 11
|
||||||
|
#define SLAVE_SERVICE_SNOC 12
|
||||||
|
#define SLAVE_PCIE_0 13
|
||||||
|
#define SLAVE_PCIE_1 14
|
||||||
|
#define SLAVE_PCIE_2 15
|
||||||
|
#define SLAVE_PCIE_3 16
|
||||||
|
#define SLAVE_QDSS_STM 17
|
||||||
|
#define SLAVE_TCU 18
|
||||||
|
|
||||||
|
#define MASTER_MNOC_HF_MEM_NOC_DISPLAY 0
|
||||||
|
#define MASTER_MNOC_SF_MEM_NOC_DISPLAY 1
|
||||||
|
#define SLAVE_LLCC_DISPLAY 2
|
||||||
|
|
||||||
|
#define MASTER_LLCC_DISPLAY 0
|
||||||
|
#define SLAVE_EBI_CH0_DISPLAY 1
|
||||||
|
|
||||||
|
#define MASTER_MDP_PORT0_DISPLAY 0
|
||||||
|
#define MASTER_MDP_PORT1_DISPLAY 1
|
||||||
|
#define MASTER_ROTATOR_DISPLAY 2
|
||||||
|
#define SLAVE_MNOC_SF_MEM_NOC_DISPLAY 3
|
||||||
|
#define SLAVE_MNOC_HF_MEM_NOC_DISPLAY 4
|
||||||
|
|
||||||
|
#endif
|
Loading…
Reference in New Issue
Block a user