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Pull more irqchip fixes for 6.0 from Marc Zyngier:
- A couple of configuration fixes for the recently merged Loongarch drivers - A fix to avoid dynamic allocation of a cpumask which was causing issues with PREEMPT_RT and the GICv3 ITS - A tightening of an error check in the stm32 exti driver -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmM0DBMACgkQEsHwGGHe VUpyQRAAldHdGN7/Gb1KwPmZ9lHXU+pt9VRm2CsC2EnBH4XclQHNIYXVHJvhHZ8H K/QfdYRBdWCJsGh+tU+swIgizsmDfZ38dpqtbY6zcZbbh8JabI7LVYRUJ+AKUtCu fIcInQ/GLwa4HmAH17BDeXLqm3xL9PzIteB1BddUbiBgSOxkUGu4q64zPdmlkXuS l5fmqD8UBK8rG5RO4ZPY6olX0oKkBAJbwDj079cRDU1COx8zUXE3bq3aTQi4j2t4 ZqAdagmVGJHjIY9Oro7su/Mxo1kdSh+i5AIQ9PvQWQM+z2/jos9DMIJyDsqSiXXG /N7ieSeTpdf5Dxfi5XxnR8m5WnTznX2M4vBSpA++5diZ5lSu9kHJIM9mL8QttPXQ +BM7Mw0PI8+HQVbhbtFUg/RG5kQYI5q8oxHFzOx4haHd275HH57prfn1FBDdrzBX uD/Suyrj5AovazT/GkS/EVGY6O+YhSCa8atlL8xRSAcHd4xoCAmBUFfRHfbIxst+ jp7hVgnevaEiWbSx46p6E4wXtQmKR79Cg/KT69FIQhOiX8RlwyaXuqnMjKcRz8np KNgOSZ8ggUfLx4hog0N8lK/0+QJLQB1sWe03X3NhqBaD5EITya0xinF2tYRix7PT 6qpY+OOdCmTbBwo5bYHS5XU5Zmv1jLN2oQNu1ja0H2K+90th2HU= =uGHJ -----END PGP SIGNATURE----- Merge tag 'irq_urgent_for_v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull more irqchip fixes from Borislav Petkov: "More irqchip fixes for 6.0 from Marc Zyngier. Stuff got left hanging due to the whole Plumbers and vacations commotion. - A couple of configuration fixes for the recently merged Loongarch drivers - A fix to avoid dynamic allocation of a cpumask which was causing issues with PREEMPT_RT and the GICv3 ITS - A tightening of an error check in the stm32 exti driver" * tag 'irq_urgent_for_v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/loongson-pch-lpc: Add dependence on LoongArch irqchip: Select downstream irqchip drivers for LoongArch CPU irqchip/gic-v3-its: Remove cpumask_var_t allocation irqchip/stm32-exti: Remove check on always false condition
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commit
c3e0e1e23c
drivers/irqchip
@ -561,6 +561,11 @@ config IRQ_LOONGARCH_CPU
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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select LOONGSON_LIOINTC
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select LOONGSON_EIOINTC
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select LOONGSON_PCH_PIC
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select LOONGSON_PCH_MSI
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select LOONGSON_PCH_LPC
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help
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Support for the LoongArch CPU Interrupt Controller. For details of
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irq chip hierarchy on LoongArch platforms please read the document
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@ -623,8 +628,9 @@ config LOONGSON_PCH_MSI
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config LOONGSON_PCH_LPC
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bool "Loongson PCH LPC Controller"
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depends on LOONGARCH
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depends on MACH_LOONGSON64
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default (MACH_LOONGSON64 && LOONGARCH)
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default MACH_LOONGSON64
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select IRQ_DOMAIN_HIERARCHY
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help
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Support for the Loongson PCH LPC Controller.
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@ -1574,13 +1574,15 @@ static int its_select_cpu(struct irq_data *d,
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const struct cpumask *aff_mask)
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{
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struct its_device *its_dev = irq_data_get_irq_chip_data(d);
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cpumask_var_t tmpmask;
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static DEFINE_RAW_SPINLOCK(tmpmask_lock);
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static struct cpumask __tmpmask;
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struct cpumask *tmpmask;
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unsigned long flags;
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int cpu, node;
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if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC))
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return -ENOMEM;
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node = its_dev->its->numa_node;
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tmpmask = &__tmpmask;
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raw_spin_lock_irqsave(&tmpmask_lock, flags);
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if (!irqd_affinity_is_managed(d)) {
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/* First try the NUMA node */
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@ -1634,7 +1636,7 @@ static int its_select_cpu(struct irq_data *d,
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cpu = cpumask_pick_least_loaded(d, tmpmask);
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}
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out:
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free_cpumask_var(tmpmask);
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raw_spin_unlock_irqrestore(&tmpmask_lock, flags);
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pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
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return cpu;
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@ -716,7 +716,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
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irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
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if (!host_data->drv_data || !host_data->drv_data->desc_irqs)
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if (!host_data->drv_data->desc_irqs)
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return -EINVAL;
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desc_irq = host_data->drv_data->desc_irqs[hwirq];
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