mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-17 17:53:56 +08:00
Merge branch 'for-chris-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/fdmanana/linux into for-linus-4.7
Signed-off-by: Chris Mason <clm@fb.com>
This commit is contained in:
commit
c315ef8d9d
5
.mailmap
5
.mailmap
@ -48,6 +48,9 @@ Felix Kuhling <fxkuehl@gmx.de>
|
||||
Felix Moeller <felix@derklecks.de>
|
||||
Filipe Lautert <filipe@icewall.org>
|
||||
Franck Bui-Huu <vagabon.xyz@gmail.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com>
|
||||
Frank Zago <fzago@systemfabricworks.com>
|
||||
Greg Kroah-Hartman <greg@echidna.(none)>
|
||||
Greg Kroah-Hartman <gregkh@suse.de>
|
||||
@ -66,6 +69,7 @@ Jean Tourrilhes <jt@hpl.hp.com>
|
||||
Jeff Garzik <jgarzik@pretzel.yyz.us>
|
||||
Jens Axboe <axboe@suse.de>
|
||||
Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
|
||||
John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
|
||||
John Stultz <johnstul@us.ibm.com>
|
||||
<josh@joshtriplett.org> <josh@freedesktop.org>
|
||||
<josh@joshtriplett.org> <josh@kernel.org>
|
||||
@ -79,6 +83,7 @@ Kay Sievers <kay.sievers@vrfy.org>
|
||||
Kenneth W Chen <kenneth.w.chen@intel.com>
|
||||
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
|
||||
Koushik <raghavendra.koushik@neterion.com>
|
||||
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
|
||||
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
Leonid I Ananiev <leonid.i.ananiev@intel.com>
|
||||
Linas Vepstas <linas@austin.ibm.com>
|
||||
|
@ -2,7 +2,7 @@
|
||||
|
||||
The ARC HS can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to upto 32 counters.
|
||||
are 100+ hardware conditions dynamically mapped to up to 32 counters.
|
||||
It also supports overflow interrupts.
|
||||
|
||||
Required properties:
|
||||
|
@ -2,7 +2,7 @@
|
||||
|
||||
The ARC700 can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to upto 32 counters
|
||||
are 100+ hardware conditions dynamically mapped to up to 32 counters
|
||||
|
||||
Note that:
|
||||
* The ARC 700 PCT does not support interrupts; although HW events may be
|
||||
|
@ -192,7 +192,6 @@ nodes to be present and contain the properties described below.
|
||||
can be one of:
|
||||
"allwinner,sun6i-a31"
|
||||
"allwinner,sun8i-a23"
|
||||
"arm,psci"
|
||||
"arm,realview-smp"
|
||||
"brcm,bcm-nsp-smp"
|
||||
"brcm,brahma-b15"
|
||||
|
@ -32,6 +32,10 @@ Optional properties:
|
||||
- target-supply : regulator for SATA target power
|
||||
- phys : reference to the SATA PHY node
|
||||
- phy-names : must be "sata-phy"
|
||||
- ports-implemented : Mask that indicates which ports that the HBA supports
|
||||
are available for software to use. Useful if PORTS_IMPL
|
||||
is not programmed by the BIOS, which is true with
|
||||
some embedded SOC's.
|
||||
|
||||
Required properties when using sub-nodes:
|
||||
- #address-cells : number of cells to encode an address
|
||||
|
@ -6,8 +6,8 @@ RK3xxx SoCs.
|
||||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or
|
||||
"rockchip,rk3288-i2c".
|
||||
- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c",
|
||||
"rockchip,rk3228-i2c" or "rockchip,rk3288-i2c".
|
||||
- interrupts : interrupt number
|
||||
- clocks : parent clock
|
||||
|
||||
|
@ -45,13 +45,13 @@ Required properties:
|
||||
Optional properties:
|
||||
- dual_emac_res_vlan : Specifies VID to be used to segregate the ports
|
||||
- mac-address : See ethernet.txt file in the same directory
|
||||
- phy_id : Specifies slave phy id
|
||||
- phy_id : Specifies slave phy id (deprecated, use phy-handle)
|
||||
- phy-handle : See ethernet.txt file in the same directory
|
||||
|
||||
Slave sub-nodes:
|
||||
- fixed-link : See fixed-link.txt file in the same directory
|
||||
Either the property phy_id, or the sub-node
|
||||
fixed-link can be specified
|
||||
|
||||
Note: Exactly one of phy_id, phy-handle, or fixed-link must be specified.
|
||||
|
||||
Note: "ti,hwmods" field is used to fetch the base address and irq
|
||||
resources from TI, omap hwmod data base during device registration.
|
||||
|
@ -6,7 +6,7 @@ This is the driver for the Altera Triple-Speed Ethernet (TSE) controllers
|
||||
using the SGDMA and MSGDMA soft DMA IP components. The driver uses the
|
||||
platform bus to obtain component resources. The designs used to test this
|
||||
driver were built for a Cyclone(R) V SOC FPGA board, a Cyclone(R) V FPGA board,
|
||||
and tested with ARM and NIOS processor hosts seperately. The anticipated use
|
||||
and tested with ARM and NIOS processor hosts separately. The anticipated use
|
||||
cases are simple communications between an embedded system and an external peer
|
||||
for status and simple configuration of the embedded system.
|
||||
|
||||
@ -65,14 +65,14 @@ Driver parameters can be also passed in command line by using:
|
||||
4.1) Transmit process
|
||||
When the driver's transmit routine is called by the kernel, it sets up a
|
||||
transmit descriptor by calling the underlying DMA transmit routine (SGDMA or
|
||||
MSGDMA), and initites a transmit operation. Once the transmit is complete, an
|
||||
MSGDMA), and initiates a transmit operation. Once the transmit is complete, an
|
||||
interrupt is driven by the transmit DMA logic. The driver handles the transmit
|
||||
completion in the context of the interrupt handling chain by recycling
|
||||
resource required to send and track the requested transmit operation.
|
||||
|
||||
4.2) Receive process
|
||||
The driver will post receive buffers to the receive DMA logic during driver
|
||||
intialization. Receive buffers may or may not be queued depending upon the
|
||||
initialization. Receive buffers may or may not be queued depending upon the
|
||||
underlying DMA logic (MSGDMA is able queue receive buffers, SGDMA is not able
|
||||
to queue receive buffers to the SGDMA receive logic). When a packet is
|
||||
received, the DMA logic generates an interrupt. The driver handles a receive
|
||||
|
@ -8,7 +8,7 @@ Initial Release:
|
||||
This is conceptually very similar to the macvlan driver with one major
|
||||
exception of using L3 for mux-ing /demux-ing among slaves. This property makes
|
||||
the master device share the L2 with it's slave devices. I have developed this
|
||||
driver in conjuntion with network namespaces and not sure if there is use case
|
||||
driver in conjunction with network namespaces and not sure if there is use case
|
||||
outside of it.
|
||||
|
||||
|
||||
@ -42,7 +42,7 @@ out. In this mode the slaves will RX/TX multicast and broadcast (if applicable)
|
||||
as well.
|
||||
|
||||
4.2 L3 mode:
|
||||
In this mode TX processing upto L3 happens on the stack instance attached
|
||||
In this mode TX processing up to L3 happens on the stack instance attached
|
||||
to the slave device and packets are switched to the stack instance of the
|
||||
master device for the L2 processing and routing from that instance will be
|
||||
used before packets are queued on the outbound device. In this mode the slaves
|
||||
@ -56,7 +56,7 @@ situations defines your use case then you can choose to use ipvlan -
|
||||
(a) The Linux host that is connected to the external switch / router has
|
||||
policy configured that allows only one mac per port.
|
||||
(b) No of virtual devices created on a master exceed the mac capacity and
|
||||
puts the NIC in promiscous mode and degraded performance is a concern.
|
||||
puts the NIC in promiscuous mode and degraded performance is a concern.
|
||||
(c) If the slave device is to be put into the hostile / untrusted network
|
||||
namespace where L2 on the slave could be changed / misused.
|
||||
|
||||
|
@ -67,12 +67,12 @@ The two basic thread commands are:
|
||||
* add_device DEVICE@NAME -- adds a single device
|
||||
* rem_device_all -- remove all associated devices
|
||||
|
||||
When adding a device to a thread, a corrosponding procfile is created
|
||||
When adding a device to a thread, a corresponding procfile is created
|
||||
which is used for configuring this device. Thus, device names need to
|
||||
be unique.
|
||||
|
||||
To support adding the same device to multiple threads, which is useful
|
||||
with multi queue NICs, a the device naming scheme is extended with "@":
|
||||
with multi queue NICs, the device naming scheme is extended with "@":
|
||||
device@something
|
||||
|
||||
The part after "@" can be anything, but it is custom to use the thread
|
||||
@ -221,7 +221,7 @@ Sample scripts
|
||||
|
||||
A collection of tutorial scripts and helpers for pktgen is in the
|
||||
samples/pktgen directory. The helper parameters.sh file support easy
|
||||
and consistant parameter parsing across the sample scripts.
|
||||
and consistent parameter parsing across the sample scripts.
|
||||
|
||||
Usage example and help:
|
||||
./pktgen_sample01_simple.sh -i eth4 -m 00:1B:21:3C:9D:F8 -d 192.168.8.2
|
||||
|
@ -41,7 +41,7 @@ using an rx_handler which gives the impression that packets flow through
|
||||
the VRF device. Similarly on egress routing rules are used to send packets
|
||||
to the VRF device driver before getting sent out the actual interface. This
|
||||
allows tcpdump on a VRF device to capture all packets into and out of the
|
||||
VRF as a whole.[1] Similiarly, netfilter [2] and tc rules can be applied
|
||||
VRF as a whole.[1] Similarly, netfilter [2] and tc rules can be applied
|
||||
using the VRF device to specify rules that apply to the VRF domain as a whole.
|
||||
|
||||
[1] Packets in the forwarded state do not flow through the device, so those
|
||||
|
@ -4,7 +4,7 @@ Krisztian <hidden@balabit.hu> and others and additional patches
|
||||
from Jamal <hadi@cyberus.ca>.
|
||||
|
||||
The end goal for syncing is to be able to insert attributes + generate
|
||||
events so that the an SA can be safely moved from one machine to another
|
||||
events so that the SA can be safely moved from one machine to another
|
||||
for HA purposes.
|
||||
The idea is to synchronize the SA so that the takeover machine can do
|
||||
the processing of the SA as accurate as possible if it has access to it.
|
||||
@ -13,7 +13,7 @@ We already have the ability to generate SA add/del/upd events.
|
||||
These patches add ability to sync and have accurate lifetime byte (to
|
||||
ensure proper decay of SAs) and replay counters to avoid replay attacks
|
||||
with as minimal loss at failover time.
|
||||
This way a backup stays as closely uptodate as an active member.
|
||||
This way a backup stays as closely up-to-date as an active member.
|
||||
|
||||
Because the above items change for every packet the SA receives,
|
||||
it is possible for a lot of the events to be generated.
|
||||
@ -163,7 +163,7 @@ If you have an SA that is getting hit by traffic in bursts such that
|
||||
there is a period where the timer threshold expires with no packets
|
||||
seen, then an odd behavior is seen as follows:
|
||||
The first packet arrival after a timer expiry will trigger a timeout
|
||||
aevent; i.e we dont wait for a timeout period or a packet threshold
|
||||
event; i.e we don't wait for a timeout period or a packet threshold
|
||||
to be reached. This is done for simplicity and efficiency reasons.
|
||||
|
||||
-JHS
|
||||
|
@ -581,15 +581,16 @@ Specify "[Nn]ode" for node order
|
||||
"Zone Order" orders the zonelists by zone type, then by node within each
|
||||
zone. Specify "[Zz]one" for zone order.
|
||||
|
||||
Specify "[Dd]efault" to request automatic configuration. Autoconfiguration
|
||||
will select "node" order in following case.
|
||||
(1) if the DMA zone does not exist or
|
||||
(2) if the DMA zone comprises greater than 50% of the available memory or
|
||||
(3) if any node's DMA zone comprises greater than 70% of its local memory and
|
||||
the amount of local memory is big enough.
|
||||
Specify "[Dd]efault" to request automatic configuration.
|
||||
|
||||
Otherwise, "zone" order will be selected. Default order is recommended unless
|
||||
this is causing problems for your system/application.
|
||||
On 32-bit, the Normal zone needs to be preserved for allocations accessible
|
||||
by the kernel, so "zone" order will be selected.
|
||||
|
||||
On 64-bit, devices that require DMA32/DMA are relatively rare, so "node"
|
||||
order will be selected.
|
||||
|
||||
Default order is recommended unless this is causing problems for your
|
||||
system/application.
|
||||
|
||||
==============================================================
|
||||
|
||||
|
76
MAINTAINERS
76
MAINTAINERS
@ -872,9 +872,9 @@ F: drivers/perf/arm_pmu.c
|
||||
F: include/linux/perf/arm_pmu.h
|
||||
|
||||
ARM PORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/
|
||||
|
||||
@ -886,35 +886,35 @@ F: arch/arm/plat-*/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
|
||||
|
||||
ARM PRIMECELL AACI PL041 DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: sound/arm/aaci.*
|
||||
|
||||
ARM PRIMECELL CLCD PL110 DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/video/fbdev/amba-clcd.*
|
||||
|
||||
ARM PRIMECELL KMI PL050 DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/input/serio/ambakmi.*
|
||||
F: include/linux/amba/kmi.h
|
||||
|
||||
ARM PRIMECELL MMCI PL180/1 DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/mmc/host/mmci.*
|
||||
F: include/linux/amba/mmci.h
|
||||
|
||||
ARM PRIMECELL UART PL010 AND PL011 DRIVERS
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/tty/serial/amba-pl01*.c
|
||||
F: include/linux/amba/serial.h
|
||||
|
||||
ARM PRIMECELL BUS SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/amba/
|
||||
F: include/linux/amba/bus.h
|
||||
@ -1036,7 +1036,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
||||
ARM/CLKDEV SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/include/asm/clkdev.h
|
||||
@ -1093,9 +1093,9 @@ F: arch/arm/boot/dts/cx92755*
|
||||
N: digicolor
|
||||
|
||||
ARM/EBSA110 MACHINE SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/mach-ebsa110/
|
||||
F: drivers/net/ethernet/amd/am79c961a.*
|
||||
@ -1124,9 +1124,9 @@ T: git git://git.berlios.de/gemini-board
|
||||
F: arch/arm/mm/*-fa*
|
||||
|
||||
ARM/FOOTBRIDGE ARCHITECTURE
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/include/asm/hardware/dec21285.h
|
||||
F: arch/arm/mach-footbridge/
|
||||
@ -1457,7 +1457,7 @@ S: Maintained
|
||||
ARM/PT DIGITAL BOARD PORT
|
||||
M: Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
|
||||
ARM/QUALCOMM SUPPORT
|
||||
@ -1493,9 +1493,9 @@ S: Supported
|
||||
F: arch/arm64/boot/dts/renesas/
|
||||
|
||||
ARM/RISCPC ARCHITECTURE
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/include/asm/hardware/entry-macro-iomd.S
|
||||
F: arch/arm/include/asm/hardware/ioc.h
|
||||
@ -1773,9 +1773,9 @@ F: drivers/clk/versatile/clk-vexpress-osc.c
|
||||
F: drivers/clocksource/versatile.c
|
||||
|
||||
ARM/VFP SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/vfp/
|
||||
|
||||
@ -2921,7 +2921,7 @@ F: mm/cleancache.c
|
||||
F: include/linux/cleancache.h
|
||||
|
||||
CLK API
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-clk@vger.kernel.org
|
||||
S: Maintained
|
||||
F: include/linux/clk.h
|
||||
@ -3354,9 +3354,9 @@ S: Supported
|
||||
F: drivers/net/ethernet/stmicro/stmmac/
|
||||
|
||||
CYBERPRO FB DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: drivers/video/fbdev/cyber2000fb.*
|
||||
|
||||
@ -3881,7 +3881,7 @@ F: Documentation/devicetree/bindings/display/st,stih4xx.txt
|
||||
|
||||
DRM DRIVERS FOR VIVANTE GPU IP
|
||||
M: Lucas Stach <l.stach@pengutronix.de>
|
||||
R: Russell King <linux+etnaviv@arm.linux.org.uk>
|
||||
R: Russell King <linux+etnaviv@armlinux.org.uk>
|
||||
R: Christian Gmeiner <christian.gmeiner@gmail.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
@ -4223,8 +4223,8 @@ F: Documentation/efi-stub.txt
|
||||
F: arch/ia64/kernel/efi.c
|
||||
F: arch/x86/boot/compressed/eboot.[ch]
|
||||
F: arch/x86/include/asm/efi.h
|
||||
F: arch/x86/platform/efi/*
|
||||
F: drivers/firmware/efi/*
|
||||
F: arch/x86/platform/efi/
|
||||
F: drivers/firmware/efi/
|
||||
F: include/linux/efi*.h
|
||||
|
||||
EFI VARIABLE FILESYSTEM
|
||||
@ -4744,7 +4744,7 @@ F: drivers/platform/x86/fujitsu-tablet.c
|
||||
|
||||
FUSE: FILESYSTEM IN USERSPACE
|
||||
M: Miklos Szeredi <miklos@szeredi.hu>
|
||||
L: fuse-devel@lists.sourceforge.net
|
||||
L: linux-fsdevel@vger.kernel.org
|
||||
W: http://fuse.sourceforge.net/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git
|
||||
S: Maintained
|
||||
@ -4903,7 +4903,7 @@ F: net/ipv4/gre_offload.c
|
||||
F: include/net/gre.h
|
||||
|
||||
GRETH 10/100/1G Ethernet MAC device driver
|
||||
M: Kristoffer Glembo <kristoffer@gaisler.com>
|
||||
M: Andreas Larsson <andreas@gaisler.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/aeroflex/
|
||||
@ -6027,7 +6027,7 @@ F: include/scsi/*iscsi*
|
||||
|
||||
ISCSI EXTENSIONS FOR RDMA (ISER) INITIATOR
|
||||
M: Or Gerlitz <ogerlitz@mellanox.com>
|
||||
M: Sagi Grimberg <sagig@mellanox.com>
|
||||
M: Sagi Grimberg <sagi@grimberg.me>
|
||||
M: Roi Dayan <roid@mellanox.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
@ -6037,7 +6037,7 @@ Q: http://patchwork.kernel.org/project/linux-rdma/list/
|
||||
F: drivers/infiniband/ulp/iser/
|
||||
|
||||
ISCSI EXTENSIONS FOR RDMA (ISER) TARGET
|
||||
M: Sagi Grimberg <sagig@mellanox.com>
|
||||
M: Sagi Grimberg <sagi@grimberg.me>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending.git master
|
||||
L: linux-rdma@vger.kernel.org
|
||||
L: target-devel@vger.kernel.org
|
||||
@ -6400,7 +6400,7 @@ F: mm/kmemleak.c
|
||||
F: mm/kmemleak-test.c
|
||||
|
||||
KPROBES
|
||||
M: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
|
||||
M: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com>
|
||||
M: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
|
||||
M: "David S. Miller" <davem@davemloft.net>
|
||||
M: Masami Hiramatsu <mhiramat@kernel.org>
|
||||
@ -6905,7 +6905,7 @@ L: linux-man@vger.kernel.org
|
||||
S: Maintained
|
||||
|
||||
MARVELL ARMADA DRM SUPPORT
|
||||
M: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
M: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/armada/
|
||||
|
||||
@ -7905,7 +7905,7 @@ S: Supported
|
||||
F: drivers/nfc/nxp-nci
|
||||
|
||||
NXP TDA998X DRM DRIVER
|
||||
M: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
M: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/i2c/tda998x_drv.c
|
||||
F: include/drm/i2c/tda998x.h
|
||||
@ -7978,7 +7978,7 @@ F: arch/arm/*omap*/*pm*
|
||||
F: drivers/cpufreq/omap-cpufreq.c
|
||||
|
||||
OMAP POWERDOMAIN SOC ADAPTATION LAYER SUPPORT
|
||||
M: Rajendra Nayak <rnayak@ti.com>
|
||||
M: Rajendra Nayak <rnayak@codeaurora.org>
|
||||
M: Paul Walmsley <paul@pwsan.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -10014,7 +10014,8 @@ F: drivers/infiniband/hw/ocrdma/
|
||||
|
||||
SFC NETWORK DRIVER
|
||||
M: Solarflare linux maintainers <linux-net-drivers@solarflare.com>
|
||||
M: Shradha Shah <sshah@solarflare.com>
|
||||
M: Edward Cree <ecree@solarflare.com>
|
||||
M: Bert Kenward <bkenward@solarflare.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/net/ethernet/sfc/
|
||||
@ -11071,6 +11072,15 @@ S: Maintained
|
||||
F: drivers/clk/ti/
|
||||
F: include/linux/clk/ti.h
|
||||
|
||||
TI ETHERNET SWITCH DRIVER (CPSW)
|
||||
M: Mugunthan V N <mugunthanvnm@ti.com>
|
||||
R: Grygorii Strashko <grygorii.strashko@ti.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/ti/cpsw*
|
||||
F: drivers/net/ethernet/ti/davinci*
|
||||
|
||||
TI FLASH MEDIA INTERFACE DRIVER
|
||||
M: Alex Dubov <oakad@yahoo.com>
|
||||
S: Maintained
|
||||
|
4
Makefile
4
Makefile
@ -1,8 +1,8 @@
|
||||
VERSION = 4
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Blurry Fish Butt
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Charred Weasel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
# To see a list of typical targets execute "make help"
|
||||
|
@ -35,8 +35,10 @@ config ARC
|
||||
select NO_BOOTMEM
|
||||
select OF
|
||||
select OF_EARLY_FLATTREE
|
||||
select OF_RESERVED_MEM
|
||||
select PERF_USE_VMALLOC
|
||||
select HAVE_DEBUG_STACKOVERFLOW
|
||||
select HAVE_GENERIC_DMA_COHERENT
|
||||
|
||||
config MIGHT_HAVE_PCI
|
||||
bool
|
||||
@ -56,6 +58,9 @@ config GENERIC_CSUM
|
||||
config RWSEM_GENERIC_SPINLOCK
|
||||
def_bool y
|
||||
|
||||
config ARCH_DISCONTIGMEM_ENABLE
|
||||
def_bool y
|
||||
|
||||
config ARCH_FLATMEM_ENABLE
|
||||
def_bool y
|
||||
|
||||
@ -345,6 +350,15 @@ config ARC_HUGEPAGE_16M
|
||||
|
||||
endchoice
|
||||
|
||||
config NODES_SHIFT
|
||||
int "Maximum NUMA Nodes (as a power of 2)"
|
||||
default "1" if !DISCONTIGMEM
|
||||
default "2" if DISCONTIGMEM
|
||||
depends on NEED_MULTIPLE_NODES
|
||||
---help---
|
||||
Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
|
||||
zones.
|
||||
|
||||
if ISA_ARCOMPACT
|
||||
|
||||
config ARC_COMPACT_IRQ_LEVELS
|
||||
@ -453,6 +467,7 @@ config LINUX_LINK_BASE
|
||||
|
||||
config HIGHMEM
|
||||
bool "High Memory Support"
|
||||
select DISCONTIGMEM
|
||||
help
|
||||
With ARC 2G:2G address split, only upper 2G is directly addressable by
|
||||
kernel. Enable this to potentially allow access to rest of 2G and PAE
|
||||
|
@ -13,6 +13,15 @@
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
#include <asm/barrier.h>
|
||||
#define __iormb() rmb()
|
||||
#define __iowmb() wmb()
|
||||
#else
|
||||
#define __iormb() do { } while (0)
|
||||
#define __iowmb() do { } while (0)
|
||||
#endif
|
||||
|
||||
extern void __iomem *ioremap(phys_addr_t paddr, unsigned long size);
|
||||
extern void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
|
||||
unsigned long flags);
|
||||
@ -31,6 +40,15 @@ extern void iounmap(const void __iomem *addr);
|
||||
#define ioremap_wc(phy, sz) ioremap(phy, sz)
|
||||
#define ioremap_wt(phy, sz) ioremap(phy, sz)
|
||||
|
||||
/*
|
||||
* io{read,write}{16,32}be() macros
|
||||
*/
|
||||
#define ioread16be(p) ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
|
||||
#define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
|
||||
|
||||
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
|
||||
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
|
||||
|
||||
/* Change struct page to physical address */
|
||||
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
|
||||
|
||||
@ -108,15 +126,6 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr)
|
||||
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
#include <asm/barrier.h>
|
||||
#define __iormb() rmb()
|
||||
#define __iowmb() wmb()
|
||||
#else
|
||||
#define __iormb() do { } while (0)
|
||||
#define __iowmb() do { } while (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MMIO can also get buffered/optimized in micro-arch, so barriers needed
|
||||
* Based on ARM model for the typical use case
|
||||
|
@ -18,6 +18,12 @@
|
||||
#define STATUS_AD_MASK (1<<STATUS_AD_BIT)
|
||||
#define STATUS_IE_MASK (1<<STATUS_IE_BIT)
|
||||
|
||||
/* status32 Bits as encoded/expected by CLRI/SETI */
|
||||
#define CLRI_STATUS_IE_BIT 4
|
||||
|
||||
#define CLRI_STATUS_E_MASK 0xF
|
||||
#define CLRI_STATUS_IE_MASK (1 << CLRI_STATUS_IE_BIT)
|
||||
|
||||
#define AUX_USER_SP 0x00D
|
||||
#define AUX_IRQ_CTRL 0x00E
|
||||
#define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */
|
||||
@ -100,6 +106,13 @@ static inline long arch_local_save_flags(void)
|
||||
:
|
||||
: "memory");
|
||||
|
||||
/* To be compatible with irq_save()/irq_restore()
|
||||
* encode the irq bits as expected by CLRI/SETI
|
||||
* (this was needed to make CONFIG_TRACE_IRQFLAGS work)
|
||||
*/
|
||||
temp = (1 << 5) |
|
||||
((!!(temp & STATUS_IE_MASK)) << CLRI_STATUS_IE_BIT) |
|
||||
(temp & CLRI_STATUS_E_MASK);
|
||||
return temp;
|
||||
}
|
||||
|
||||
@ -108,7 +121,7 @@ static inline long arch_local_save_flags(void)
|
||||
*/
|
||||
static inline int arch_irqs_disabled_flags(unsigned long flags)
|
||||
{
|
||||
return !(flags & (STATUS_IE_MASK));
|
||||
return !(flags & CLRI_STATUS_IE_MASK);
|
||||
}
|
||||
|
||||
static inline int arch_irqs_disabled(void)
|
||||
@ -128,11 +141,32 @@ static inline void arc_softirq_clear(int irq)
|
||||
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
|
||||
.macro TRACE_ASM_IRQ_DISABLE
|
||||
bl trace_hardirqs_off
|
||||
.endm
|
||||
|
||||
.macro TRACE_ASM_IRQ_ENABLE
|
||||
bl trace_hardirqs_on
|
||||
.endm
|
||||
|
||||
#else
|
||||
|
||||
.macro TRACE_ASM_IRQ_DISABLE
|
||||
.endm
|
||||
|
||||
.macro TRACE_ASM_IRQ_ENABLE
|
||||
.endm
|
||||
|
||||
#endif
|
||||
.macro IRQ_DISABLE scratch
|
||||
clri
|
||||
TRACE_ASM_IRQ_DISABLE
|
||||
.endm
|
||||
|
||||
.macro IRQ_ENABLE scratch
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
seti
|
||||
.endm
|
||||
|
||||
|
43
arch/arc/include/asm/mmzone.h
Normal file
43
arch/arc/include/asm/mmzone.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARC_MMZONE_H
|
||||
#define _ASM_ARC_MMZONE_H
|
||||
|
||||
#ifdef CONFIG_DISCONTIGMEM
|
||||
|
||||
extern struct pglist_data node_data[];
|
||||
#define NODE_DATA(nid) (&node_data[nid])
|
||||
|
||||
static inline int pfn_to_nid(unsigned long pfn)
|
||||
{
|
||||
int is_end_low = 1;
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_PAE40))
|
||||
is_end_low = pfn <= virt_to_pfn(0xFFFFFFFFUL);
|
||||
|
||||
/*
|
||||
* node 0: lowmem: 0x8000_0000 to 0xFFFF_FFFF
|
||||
* node 1: HIGHMEM w/o PAE40: 0x0 to 0x7FFF_FFFF
|
||||
* HIGHMEM with PAE40: 0x1_0000_0000 to ...
|
||||
*/
|
||||
if (pfn >= ARCH_PFN_OFFSET && is_end_low)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline int pfn_valid(unsigned long pfn)
|
||||
{
|
||||
int nid = pfn_to_nid(pfn);
|
||||
|
||||
return (pfn <= node_end_pfn(nid));
|
||||
}
|
||||
#endif /* CONFIG_DISCONTIGMEM */
|
||||
|
||||
#endif
|
@ -72,11 +72,20 @@ typedef unsigned long pgprot_t;
|
||||
|
||||
typedef pte_t * pgtable_t;
|
||||
|
||||
/*
|
||||
* Use virt_to_pfn with caution:
|
||||
* If used in pte or paddr related macros, it could cause truncation
|
||||
* in PAE40 builds
|
||||
* As a rule of thumb, only use it in helpers starting with virt_
|
||||
* You have been warned !
|
||||
*/
|
||||
#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
|
||||
|
||||
#define ARCH_PFN_OFFSET virt_to_pfn(CONFIG_LINUX_LINK_BASE)
|
||||
|
||||
#ifdef CONFIG_FLATMEM
|
||||
#define pfn_valid(pfn) (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* __pa, __va, virt_to_page (ALERT: deprecated, don't use them)
|
||||
@ -85,12 +94,10 @@ typedef pte_t * pgtable_t;
|
||||
* virt here means link-address/program-address as embedded in object code.
|
||||
* And for ARC, link-addr = physical address
|
||||
*/
|
||||
#define __pa(vaddr) ((unsigned long)vaddr)
|
||||
#define __pa(vaddr) ((unsigned long)(vaddr))
|
||||
#define __va(paddr) ((void *)((unsigned long)(paddr)))
|
||||
|
||||
#define virt_to_page(kaddr) \
|
||||
(mem_map + virt_to_pfn((kaddr) - CONFIG_LINUX_LINK_BASE))
|
||||
|
||||
#define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr))
|
||||
#define virt_addr_valid(kaddr) pfn_valid(virt_to_pfn(kaddr))
|
||||
|
||||
/* Default Permissions for stack/heaps pages (Non Executable) */
|
||||
|
@ -278,14 +278,13 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
|
||||
#define pmd_present(x) (pmd_val(x))
|
||||
#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
|
||||
|
||||
#define pte_page(pte) \
|
||||
(mem_map + virt_to_pfn(pte_val(pte) - CONFIG_LINUX_LINK_BASE))
|
||||
|
||||
#define pte_page(pte) pfn_to_page(pte_pfn(pte))
|
||||
#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
|
||||
#define pte_pfn(pte) virt_to_pfn(pte_val(pte))
|
||||
#define pfn_pte(pfn, prot) (__pte(((pte_t)(pfn) << PAGE_SHIFT) | \
|
||||
pgprot_val(prot)))
|
||||
#define __pte_index(addr) (virt_to_pfn(addr) & (PTRS_PER_PTE - 1))
|
||||
#define pfn_pte(pfn, prot) (__pte(((pte_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
|
||||
|
||||
/* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/
|
||||
#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
|
||||
#define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
|
||||
|
||||
/*
|
||||
* pte_offset gets a @ptr to PMD entry (PGD in our 2-tier paging system)
|
||||
|
@ -69,8 +69,11 @@ ENTRY(handle_interrupt)
|
||||
|
||||
clri ; To make status32.IE agree with CPU internal state
|
||||
|
||||
lr r0, [ICAUSE]
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
TRACE_ASM_IRQ_DISABLE
|
||||
#endif
|
||||
|
||||
lr r0, [ICAUSE]
|
||||
mov blink, ret_from_exception
|
||||
|
||||
b.d arch_do_IRQ
|
||||
@ -169,6 +172,11 @@ END(EV_TLBProtV)
|
||||
|
||||
.Lrestore_regs:
|
||||
|
||||
# Interrpts are actually disabled from this point on, but will get
|
||||
# reenabled after we return from interrupt/exception.
|
||||
# But irq tracer needs to be told now...
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
|
||||
ld r0, [sp, PT_status32] ; U/K mode at time of entry
|
||||
lr r10, [AUX_IRQ_ACT]
|
||||
|
||||
|
@ -341,6 +341,9 @@ END(call_do_page_fault)
|
||||
|
||||
.Lrestore_regs:
|
||||
|
||||
# Interrpts are actually disabled from this point on, but will get
|
||||
# reenabled after we return from interrupt/exception.
|
||||
# But irq tracer needs to be told now...
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
|
||||
lr r10, [status32]
|
||||
|
@ -13,6 +13,7 @@
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
#include <linux/initrd.h>
|
||||
#endif
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/highmem.h>
|
||||
@ -29,11 +30,16 @@ static const unsigned long low_mem_start = CONFIG_LINUX_LINK_BASE;
|
||||
static unsigned long low_mem_sz;
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
static unsigned long min_high_pfn;
|
||||
static unsigned long min_high_pfn, max_high_pfn;
|
||||
static u64 high_mem_start;
|
||||
static u64 high_mem_sz;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DISCONTIGMEM
|
||||
struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
|
||||
EXPORT_SYMBOL(node_data);
|
||||
#endif
|
||||
|
||||
/* User can over-ride above with "mem=nnn[KkMm]" in cmdline */
|
||||
static int __init setup_mem_sz(char *str)
|
||||
{
|
||||
@ -108,13 +114,11 @@ void __init setup_arch_memory(void)
|
||||
/* Last usable page of low mem */
|
||||
max_low_pfn = max_pfn = PFN_DOWN(low_mem_start + low_mem_sz);
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
min_high_pfn = PFN_DOWN(high_mem_start);
|
||||
max_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
|
||||
#ifdef CONFIG_FLATMEM
|
||||
/* pfn_valid() uses this */
|
||||
max_mapnr = max_low_pfn - min_low_pfn;
|
||||
#endif
|
||||
|
||||
max_mapnr = max_pfn - min_low_pfn;
|
||||
|
||||
/*------------- bootmem allocator setup -----------------------*/
|
||||
|
||||
/*
|
||||
@ -128,7 +132,7 @@ void __init setup_arch_memory(void)
|
||||
* the crash
|
||||
*/
|
||||
|
||||
memblock_add(low_mem_start, low_mem_sz);
|
||||
memblock_add_node(low_mem_start, low_mem_sz, 0);
|
||||
memblock_reserve(low_mem_start, __pa(_end) - low_mem_start);
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
@ -136,6 +140,9 @@ void __init setup_arch_memory(void)
|
||||
memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
|
||||
#endif
|
||||
|
||||
early_init_fdt_reserve_self();
|
||||
early_init_fdt_scan_reserved_mem();
|
||||
|
||||
memblock_dump_all();
|
||||
|
||||
/*----------------- node/zones setup --------------------------*/
|
||||
@ -145,13 +152,6 @@ void __init setup_arch_memory(void)
|
||||
zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
|
||||
zones_holes[ZONE_NORMAL] = 0;
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
zones_size[ZONE_HIGHMEM] = max_pfn - max_low_pfn;
|
||||
|
||||
/* This handles the peripheral address space hole */
|
||||
zones_holes[ZONE_HIGHMEM] = min_high_pfn - max_low_pfn;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We can't use the helper free_area_init(zones[]) because it uses
|
||||
* PAGE_OFFSET to compute the @min_low_pfn which would be wrong
|
||||
@ -164,6 +164,34 @@ void __init setup_arch_memory(void)
|
||||
zones_holes); /* holes */
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
/*
|
||||
* Populate a new node with highmem
|
||||
*
|
||||
* On ARC (w/o PAE) HIGHMEM addresses are actually smaller (0 based)
|
||||
* than addresses in normal ala low memory (0x8000_0000 based).
|
||||
* Even with PAE, the huge peripheral space hole would waste a lot of
|
||||
* mem with single mem_map[]. This warrants a mem_map per region design.
|
||||
* Thus HIGHMEM on ARC is imlemented with DISCONTIGMEM.
|
||||
*
|
||||
* DISCONTIGMEM in turns requires multiple nodes. node 0 above is
|
||||
* populated with normal memory zone while node 1 only has highmem
|
||||
*/
|
||||
node_set_online(1);
|
||||
|
||||
min_high_pfn = PFN_DOWN(high_mem_start);
|
||||
max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
|
||||
|
||||
zones_size[ZONE_NORMAL] = 0;
|
||||
zones_holes[ZONE_NORMAL] = 0;
|
||||
|
||||
zones_size[ZONE_HIGHMEM] = max_high_pfn - min_high_pfn;
|
||||
zones_holes[ZONE_HIGHMEM] = 0;
|
||||
|
||||
free_area_init_node(1, /* node-id */
|
||||
zones_size, /* num pages per zone */
|
||||
min_high_pfn, /* first pfn of node */
|
||||
zones_holes); /* holes */
|
||||
|
||||
high_memory = (void *)(min_high_pfn << PAGE_SHIFT);
|
||||
kmap_init();
|
||||
#endif
|
||||
@ -181,7 +209,7 @@ void __init mem_init(void)
|
||||
unsigned long tmp;
|
||||
|
||||
reset_all_zones_managed_pages();
|
||||
for (tmp = min_high_pfn; tmp < max_pfn; tmp++)
|
||||
for (tmp = min_high_pfn; tmp < max_high_pfn; tmp++)
|
||||
free_highmem_page(pfn_to_page(tmp));
|
||||
#endif
|
||||
|
||||
|
@ -860,7 +860,7 @@
|
||||
ti,no-idle-on-init;
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <100>;
|
||||
dmas = <&edma 52>;
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
|
@ -884,7 +884,7 @@
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
dmas = <&edma 52>;
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
clocks = <&l3s_gclk>;
|
||||
clock-names = "fck";
|
||||
|
@ -99,13 +99,6 @@
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
extcon_usb1: extcon_usb1 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&extcon_usb1_pins>;
|
||||
};
|
||||
|
||||
hdmi0: connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
@ -349,12 +342,6 @@
|
||||
>;
|
||||
};
|
||||
|
||||
extcon_usb1_pins: extcon_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
|
||||
>;
|
||||
};
|
||||
|
||||
tpd12s015_pins: pinmux_tpd12s015_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
|
||||
@ -706,10 +693,6 @@
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
@ -4,6 +4,157 @@
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&pllss {
|
||||
/*
|
||||
* See TRM "2.6.10 Connected outputso DPLLS" and
|
||||
* "2.6.11 Connected Outputs of DPLLJ". Only clkout is
|
||||
* connected except for hdmi and usb.
|
||||
*/
|
||||
adpll_mpu_ck: adpll@40 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-s-clock";
|
||||
reg = <0x40 0x40>;
|
||||
clocks = <&devosc_ck &devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow", "clkinphif";
|
||||
clock-output-names = "481c5040.adpll.dcoclkldo",
|
||||
"481c5040.adpll.clkout",
|
||||
"481c5040.adpll.clkoutx2",
|
||||
"481c5040.adpll.clkouthif";
|
||||
};
|
||||
|
||||
adpll_dsp_ck: adpll@80 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x80 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5080.adpll.dcoclkldo",
|
||||
"481c5080.adpll.clkout",
|
||||
"481c5080.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_sgx_ck: adpll@b0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0xb0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c50b0.adpll.dcoclkldo",
|
||||
"481c50b0.adpll.clkout",
|
||||
"481c50b0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_hdvic_ck: adpll@e0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0xe0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c50e0.adpll.dcoclkldo",
|
||||
"481c50e0.adpll.clkout",
|
||||
"481c50e0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_l3_ck: adpll@110 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x110 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5110.adpll.dcoclkldo",
|
||||
"481c5110.adpll.clkout",
|
||||
"481c5110.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_isp_ck: adpll@140 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x140 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5140.adpll.dcoclkldo",
|
||||
"481c5140.adpll.clkout",
|
||||
"481c5140.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_dss_ck: adpll@170 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x170 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5170.adpll.dcoclkldo",
|
||||
"481c5170.adpll.clkout",
|
||||
"481c5170.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_video0_ck: adpll@1a0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x1a0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c51a0.adpll.dcoclkldo",
|
||||
"481c51a0.adpll.clkout",
|
||||
"481c51a0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_video1_ck: adpll@1d0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x1d0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c51d0.adpll.dcoclkldo",
|
||||
"481c51d0.adpll.clkout",
|
||||
"481c51d0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_hdmi_ck: adpll@200 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x200 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5200.adpll.dcoclkldo",
|
||||
"481c5200.adpll.clkout",
|
||||
"481c5200.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_audio_ck: adpll@230 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x230 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5230.adpll.dcoclkldo",
|
||||
"481c5230.adpll.clkout",
|
||||
"481c5230.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_usb_ck: adpll@260 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x260 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5260.adpll.dcoclkldo",
|
||||
"481c5260.adpll.clkout",
|
||||
"481c5260.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_ddr_ck: adpll@290 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x290 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5290.adpll.dcoclkldo",
|
||||
"481c5290.adpll.clkout",
|
||||
"481c5290.adpll.clkoutldo";
|
||||
};
|
||||
};
|
||||
|
||||
&pllss_clocks {
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
@ -23,6 +174,24 @@
|
||||
reg = <0x2e0>;
|
||||
};
|
||||
|
||||
/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&adpll_video0_ck 1
|
||||
&adpll_video1_ck 1
|
||||
&adpll_audio_ck 1>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x2e8>;
|
||||
};
|
||||
|
||||
/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
sysclk18_ck: sysclk18_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
@ -79,37 +248,6 @@
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
sysclk4_ck: sysclk4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <222000000>;
|
||||
};
|
||||
|
||||
sysclk6_ck: sysclk6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
sysclk10_ck: sysclk10_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&prcm_clocks {
|
||||
@ -138,6 +276,49 @@
|
||||
clock-div = <78125>;
|
||||
};
|
||||
|
||||
/* L4_HS 220 MHz*/
|
||||
sysclk4_ck: sysclk4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <1>;
|
||||
};
|
||||
|
||||
/* L4_FWCFG */
|
||||
sysclk5_ck: sysclk5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <2>;
|
||||
};
|
||||
|
||||
/* L4_LS 110 MHz */
|
||||
sysclk6_ck: sysclk6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <2>;
|
||||
};
|
||||
|
||||
sysclk8_ck: sysclk8_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_usb_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <1>;
|
||||
};
|
||||
|
||||
sysclk10_ck: sysclk10_ck {
|
||||
compatible = "ti,divider-clock";
|
||||
reg = <0x324>;
|
||||
ti,max-div = <7>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&adpll_usb_ck 1>;
|
||||
};
|
||||
|
||||
aud_clkin0_ck: aud_clkin0_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
@ -6,6 +6,32 @@
|
||||
|
||||
#include "dm814x-clocks.dtsi"
|
||||
|
||||
/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
|
||||
&adpll_hdvic_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&adpll_l3_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&adpll_dss_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
|
||||
&sysclk4_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
&sysclk5_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
&sysclk6_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Compared to dm814x, dra62x has different shifts and more mux options.
|
||||
* Please add the extra options for ysclk_14 and 16 if really needed.
|
||||
|
@ -98,12 +98,20 @@
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sys_32k_ck: sys_32k_ck {
|
||||
sys_clk32_crystal_ck: sys_clk32_crystal_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin1>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <610>;
|
||||
};
|
||||
|
||||
virt_12000000_ck: virt_12000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
@ -2170,4 +2178,12 @@
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
|
||||
sys_32k_ck: sys_32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x6c4>;
|
||||
};
|
||||
};
|
||||
|
@ -329,6 +329,7 @@
|
||||
regulator-name = "V28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
regulator-always-on; /* due to battery cover sensor */
|
||||
};
|
||||
|
||||
@ -336,30 +337,35 @@
|
||||
regulator-name = "VCSI";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vaux3 {
|
||||
regulator-name = "VMMC2_30";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vaux4 {
|
||||
regulator-name = "VCAM_ANA_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vmmc1 {
|
||||
regulator-name = "VMMC1";
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vmmc2 {
|
||||
regulator-name = "V28_A";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
regulator-always-on; /* due VIO leak to AIC34 VDDs */
|
||||
};
|
||||
|
||||
@ -367,6 +373,7 @@
|
||||
regulator-name = "VPLL";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
@ -374,6 +381,7 @@
|
||||
regulator-name = "VSDI_CSI";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
@ -381,6 +389,7 @@
|
||||
regulator-name = "VMMC2_IO_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vio {
|
||||
|
@ -46,7 +46,7 @@
|
||||
0x480bd800 0x017c>;
|
||||
interrupts = <24>;
|
||||
iommus = <&mmu_isp>;
|
||||
syscon = <&scm_conf 0xdc>;
|
||||
syscon = <&scm_conf 0x6c>;
|
||||
ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
|
||||
#clock-cells = <1>;
|
||||
ports {
|
||||
|
@ -472,7 +472,7 @@
|
||||
ldo1_reg: ldo1 {
|
||||
/* VDDAPHY_CAM: vdda_csiport */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
@ -498,7 +498,7 @@
|
||||
ldo4_reg: ldo4 {
|
||||
/* VDDAPHY_DISP: vdda_dsiport/hdmi */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
|
@ -513,7 +513,7 @@
|
||||
ldo1_reg: ldo1 {
|
||||
/* VDDAPHY_CAM: vdda_csiport */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
@ -537,7 +537,7 @@
|
||||
ldo4_reg: ldo4 {
|
||||
/* VDDAPHY_DISP: vdda_dsiport/hdmi */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
|
@ -269,7 +269,7 @@
|
||||
omap5_pmx_wkup: pinmux@c840 {
|
||||
compatible = "ti,omap5-padconf",
|
||||
"pinctrl-single";
|
||||
reg = <0xc840 0x0038>;
|
||||
reg = <0xc840 0x003c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
|
@ -666,7 +666,7 @@
|
||||
};
|
||||
|
||||
sata0: sata@29000000 {
|
||||
compatible = "generic-ahci";
|
||||
compatible = "qcom,apq8064-ahci", "generic-ahci";
|
||||
status = "disabled";
|
||||
reg = <0x29000000 0x180>;
|
||||
interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
|
||||
@ -688,6 +688,7 @@
|
||||
|
||||
phys = <&sata_phy0>;
|
||||
phy-names = "sata-phy";
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
|
||||
/* Temporary fixed regulator */
|
||||
|
@ -1,6 +1,6 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
@ -460,8 +460,6 @@
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
spmi_bus: spmi@fc4cf000 {
|
||||
@ -479,16 +477,6 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
};
|
||||
|
||||
blsp2_dma: dma-controller@f9944000 {
|
||||
compatible = "qcom,bam-v1.4.0";
|
||||
reg = <0xf9944000 0x19000>;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
smd {
|
||||
|
@ -661,6 +661,7 @@
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -143,19 +143,11 @@
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif0_pins: serial0 {
|
||||
renesas,groups = "scif0_data_d";
|
||||
renesas,function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
@ -229,11 +221,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
@ -414,6 +401,7 @@
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -1083,9 +1083,8 @@
|
||||
pcie_bus_clk: pcie_bus_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "pcie_bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
@ -1094,7 +1093,6 @@
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
@ -1112,7 +1110,6 @@
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "can_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
|
@ -125,8 +125,6 @@
|
||||
};
|
||||
|
||||
®_dc1sw {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc-lcd";
|
||||
};
|
||||
|
||||
|
@ -84,6 +84,7 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_CPU_CP15_MMU
|
||||
static inline unsigned int get_domain(void)
|
||||
{
|
||||
unsigned int domain;
|
||||
@ -103,6 +104,16 @@ static inline void set_domain(unsigned val)
|
||||
: : "r" (val) : "memory");
|
||||
isb();
|
||||
}
|
||||
#else
|
||||
static inline unsigned int get_domain(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void set_domain(unsigned val)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
#define modify_domain(dom,type) \
|
||||
|
@ -236,7 +236,7 @@ ENTRY(__setup_mpu)
|
||||
mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE
|
||||
ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
|
||||
/* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
|
||||
mov r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
|
||||
mov r6, #(((2 * PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
|
||||
|
||||
setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled
|
||||
beq 3f @ Memory-map not unified
|
||||
|
@ -1004,7 +1004,7 @@ static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap)
|
||||
kvm_pfn_t pfn = *pfnp;
|
||||
gfn_t gfn = *ipap >> PAGE_SHIFT;
|
||||
|
||||
if (PageTransCompound(pfn_to_page(pfn))) {
|
||||
if (PageTransCompoundMap(pfn_to_page(pfn))) {
|
||||
unsigned long mask;
|
||||
/*
|
||||
* The address we faulted on is backed by a transparent huge
|
||||
|
@ -121,6 +121,11 @@ static void read_factory_config(struct nvmem_device *nvmem, void *context)
|
||||
const char *partnum = NULL;
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
|
||||
if (!IS_BUILTIN(CONFIG_NVMEM)) {
|
||||
pr_warn("Factory Config not available without CONFIG_NVMEM\n");
|
||||
goto bad_config;
|
||||
}
|
||||
|
||||
ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
|
||||
&factory_config);
|
||||
if (ret != sizeof(struct factory_config)) {
|
||||
|
@ -33,6 +33,11 @@ void davinci_get_mac_addr(struct nvmem_device *nvmem, void *context)
|
||||
char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
|
||||
off_t offset = (off_t)context;
|
||||
|
||||
if (!IS_BUILTIN(CONFIG_NVMEM)) {
|
||||
pr_warn("Cannot read MAC addr from EEPROM without CONFIG_NVMEM\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Read MAC addr from EEPROM */
|
||||
if (nvmem_device_read(nvmem, offset, ETH_ALEN, mac_addr) == ETH_ALEN)
|
||||
pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
|
||||
|
@ -92,7 +92,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
|
||||
if (IS_ERR(pd->clk[i]))
|
||||
break;
|
||||
|
||||
if (IS_ERR(pd->clk[i]))
|
||||
if (IS_ERR(pd->pclk[i]))
|
||||
continue; /* Skip on first power up */
|
||||
if (clk_set_parent(pd->clk[i], pd->pclk[i]))
|
||||
pr_err("%s: error setting parent to clock%d\n",
|
||||
|
@ -71,6 +71,7 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx(
|
||||
if (!pdata)
|
||||
pdata = &default_esdhc_pdata;
|
||||
|
||||
return imx_add_platform_device(data->devid, data->id, res,
|
||||
ARRAY_SIZE(res), pdata, sizeof(*pdata));
|
||||
return imx_add_platform_device_dmamask(data->devid, data->id, res,
|
||||
ARRAY_SIZE(res), pdata, sizeof(*pdata),
|
||||
DMA_BIT_MASK(32));
|
||||
}
|
||||
|
@ -461,7 +461,7 @@ static struct clockdomain ipu_7xx_clkdm = {
|
||||
.cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
|
||||
.clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
|
||||
.dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain mpu1_7xx_clkdm = {
|
||||
|
@ -737,7 +737,8 @@ void __init omap5_init_late(void)
|
||||
#ifdef CONFIG_SOC_DRA7XX
|
||||
void __init dra7xx_init_early(void)
|
||||
{
|
||||
omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
|
||||
omap2_set_globals_tap(DRA7XX_CLASS,
|
||||
OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
|
||||
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
|
||||
omap2_control_base_init();
|
||||
omap4_pm_init_early();
|
||||
|
@ -274,6 +274,10 @@ static inline void omap5_irq_save_context(void)
|
||||
*/
|
||||
static void irq_save_context(void)
|
||||
{
|
||||
/* DRA7 has no SAR to save */
|
||||
if (soc_is_dra7xx())
|
||||
return;
|
||||
|
||||
if (!sar_base)
|
||||
sar_base = omap4_get_sar_ram_base();
|
||||
|
||||
@ -290,6 +294,9 @@ static void irq_sar_clear(void)
|
||||
{
|
||||
u32 val;
|
||||
u32 offset = SAR_BACKUP_STATUS_OFFSET;
|
||||
/* DRA7 has no SAR to save */
|
||||
if (soc_is_dra7xx())
|
||||
return;
|
||||
|
||||
if (soc_is_omap54xx())
|
||||
offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
|
||||
|
@ -198,7 +198,6 @@ void omap_sram_idle(void)
|
||||
int per_next_state = PWRDM_POWER_ON;
|
||||
int core_next_state = PWRDM_POWER_ON;
|
||||
int per_going_off;
|
||||
int core_prev_state;
|
||||
u32 sdrc_pwr = 0;
|
||||
|
||||
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
|
||||
@ -278,16 +277,20 @@ void omap_sram_idle(void)
|
||||
sdrc_write_reg(sdrc_pwr, SDRC_POWER);
|
||||
|
||||
/* CORE */
|
||||
if (core_next_state < PWRDM_POWER_ON) {
|
||||
core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
|
||||
if (core_prev_state == PWRDM_POWER_OFF) {
|
||||
omap3_core_restore_context();
|
||||
omap3_cm_restore_context();
|
||||
omap3_sram_restore_context();
|
||||
omap2_sms_restore_context();
|
||||
}
|
||||
if (core_next_state < PWRDM_POWER_ON &&
|
||||
pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
|
||||
omap3_core_restore_context();
|
||||
omap3_cm_restore_context();
|
||||
omap3_sram_restore_context();
|
||||
omap2_sms_restore_context();
|
||||
} else {
|
||||
/*
|
||||
* In off-mode resume path above, omap3_core_restore_context
|
||||
* also handles the INTC autoidle restore done here so limit
|
||||
* this to non-off mode resume paths so we don't do it twice.
|
||||
*/
|
||||
omap3_intc_resume_idle();
|
||||
}
|
||||
omap3_intc_resume_idle();
|
||||
|
||||
pwrdm_post_transition(NULL);
|
||||
|
||||
|
@ -40,8 +40,7 @@ static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
|
||||
void __init shmobile_init_delay(void)
|
||||
{
|
||||
struct device_node *np, *cpus;
|
||||
bool is_a7_a8_a9 = false;
|
||||
bool is_a15 = false;
|
||||
unsigned int div = 0;
|
||||
bool has_arch_timer = false;
|
||||
u32 max_freq = 0;
|
||||
|
||||
@ -55,27 +54,22 @@ void __init shmobile_init_delay(void)
|
||||
if (!of_property_read_u32(np, "clock-frequency", &freq))
|
||||
max_freq = max(max_freq, freq);
|
||||
|
||||
if (of_device_is_compatible(np, "arm,cortex-a8") ||
|
||||
of_device_is_compatible(np, "arm,cortex-a9")) {
|
||||
is_a7_a8_a9 = true;
|
||||
} else if (of_device_is_compatible(np, "arm,cortex-a7")) {
|
||||
is_a7_a8_a9 = true;
|
||||
has_arch_timer = true;
|
||||
} else if (of_device_is_compatible(np, "arm,cortex-a15")) {
|
||||
is_a15 = true;
|
||||
if (of_device_is_compatible(np, "arm,cortex-a8")) {
|
||||
div = 2;
|
||||
} else if (of_device_is_compatible(np, "arm,cortex-a9")) {
|
||||
div = 1;
|
||||
} else if (of_device_is_compatible(np, "arm,cortex-a7") ||
|
||||
of_device_is_compatible(np, "arm,cortex-a15")) {
|
||||
div = 1;
|
||||
has_arch_timer = true;
|
||||
}
|
||||
}
|
||||
|
||||
of_node_put(cpus);
|
||||
|
||||
if (!max_freq)
|
||||
if (!max_freq || !div)
|
||||
return;
|
||||
|
||||
if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
|
||||
if (is_a7_a8_a9)
|
||||
shmobile_setup_delay_hz(max_freq, 1, 3);
|
||||
else if (is_a15)
|
||||
shmobile_setup_delay_hz(max_freq, 2, 4);
|
||||
}
|
||||
if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
|
||||
shmobile_setup_delay_hz(max_freq, 1, div);
|
||||
}
|
||||
|
@ -13,6 +13,7 @@
|
||||
#include <asm/assembler.h>
|
||||
|
||||
.arch armv7-a
|
||||
.arm
|
||||
|
||||
ENTRY(secondary_trampoline)
|
||||
/* CPU1 will always fetch from 0x0 when it is brought out of reset.
|
||||
|
@ -87,7 +87,6 @@ static unsigned long irbar_read(void)
|
||||
/* MPU initialisation functions */
|
||||
void __init sanity_check_meminfo_mpu(void)
|
||||
{
|
||||
int i;
|
||||
phys_addr_t phys_offset = PHYS_OFFSET;
|
||||
phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
|
||||
struct memblock_region *reg;
|
||||
@ -110,11 +109,13 @@ void __init sanity_check_meminfo_mpu(void)
|
||||
} else {
|
||||
/*
|
||||
* memblock auto merges contiguous blocks, remove
|
||||
* all blocks afterwards
|
||||
* all blocks afterwards in one go (we can't remove
|
||||
* blocks separately while iterating)
|
||||
*/
|
||||
pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
|
||||
&mem_start, ®->base);
|
||||
memblock_remove(reg->base, reg->size);
|
||||
&mem_end, ®->base);
|
||||
memblock_remove(reg->base, 0 - reg->base);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -144,7 +145,7 @@ void __init sanity_check_meminfo_mpu(void)
|
||||
pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
|
||||
&specified_mem_size, &aligned_region_size);
|
||||
memblock_remove(mem_start + aligned_region_size,
|
||||
specified_mem_size - aligned_round_size);
|
||||
specified_mem_size - aligned_region_size);
|
||||
|
||||
mem_end = mem_start + aligned_region_size;
|
||||
}
|
||||
@ -261,7 +262,7 @@ void __init mpu_setup(void)
|
||||
return;
|
||||
|
||||
region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
|
||||
ilog2(meminfo.bank[0].size),
|
||||
ilog2(memblock.memory.regions[0].size),
|
||||
MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
|
||||
if (region_err) {
|
||||
panic("MPU region initialization failure! %d", region_err);
|
||||
@ -285,7 +286,7 @@ void __init arm_mm_memblock_reserve(void)
|
||||
* some architectures which the DRAM is the exception vector to trap,
|
||||
* alloc_page breaks with error, although it is not NULL, but "0."
|
||||
*/
|
||||
memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
|
||||
memblock_reserve(CONFIG_VECTORS_BASE, 2 * PAGE_SIZE);
|
||||
#else /* ifndef CONFIG_CPU_V7M */
|
||||
/*
|
||||
* There is no dedicated vector page on V7-M. So nothing needs to be
|
||||
|
@ -120,7 +120,6 @@
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc {
|
||||
|
@ -70,7 +70,6 @@
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -201,15 +201,12 @@
|
||||
|
||||
i2c2: i2c@58782000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58783000 {
|
||||
@ -227,12 +224,15 @@
|
||||
|
||||
i2c4: i2c@58784000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58784000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 45 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c5: i2c@58785000 {
|
||||
@ -245,16 +245,6 @@
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
system_bus: system-bus@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
status = "disabled";
|
||||
|
@ -68,7 +68,7 @@ void *memset(void *s, int c, size_t count)
|
||||
"=r" (charcnt), /* %1 Output */
|
||||
"=r" (dwordcnt), /* %2 Output */
|
||||
"=r" (fill8reg), /* %3 Output */
|
||||
"=r" (wrkrega) /* %4 Output */
|
||||
"=&r" (wrkrega) /* %4 Output only */
|
||||
: "r" (c), /* %5 Input */
|
||||
"0" (s), /* %0 Input/Output */
|
||||
"1" (count) /* %1 Input/Output */
|
||||
|
@ -344,7 +344,7 @@ tracesys_next:
|
||||
#endif
|
||||
|
||||
cmpib,COND(=),n -1,%r20,tracesys_exit /* seccomp may have returned -1 */
|
||||
comiclr,>>= __NR_Linux_syscalls, %r20, %r0
|
||||
comiclr,>> __NR_Linux_syscalls, %r20, %r0
|
||||
b,n .Ltracesys_nosys
|
||||
|
||||
LDREGX %r20(%r19), %r19
|
||||
|
@ -384,3 +384,5 @@ SYSCALL(ni_syscall)
|
||||
SYSCALL(ni_syscall)
|
||||
SYSCALL(mlock2)
|
||||
SYSCALL(copy_file_range)
|
||||
COMPAT_SYS_SPU(preadv2)
|
||||
COMPAT_SYS_SPU(pwritev2)
|
||||
|
@ -12,7 +12,7 @@
|
||||
#include <uapi/asm/unistd.h>
|
||||
|
||||
|
||||
#define NR_syscalls 380
|
||||
#define NR_syscalls 382
|
||||
|
||||
#define __NR__exit __NR_exit
|
||||
|
||||
|
@ -82,7 +82,7 @@ static inline unsigned long create_zero_mask(unsigned long bits)
|
||||
"andc %1,%1,%2\n\t"
|
||||
"popcntd %0,%1"
|
||||
: "=r" (leading_zero_bits), "=&r" (trailing_zero_bit_mask)
|
||||
: "r" (bits));
|
||||
: "b" (bits));
|
||||
|
||||
return leading_zero_bits;
|
||||
}
|
||||
|
@ -390,5 +390,7 @@
|
||||
#define __NR_membarrier 365
|
||||
#define __NR_mlock2 378
|
||||
#define __NR_copy_file_range 379
|
||||
#define __NR_preadv2 380
|
||||
#define __NR_pwritev2 381
|
||||
|
||||
#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
|
||||
|
@ -11,7 +11,7 @@ typedef struct {
|
||||
spinlock_t list_lock;
|
||||
struct list_head pgtable_list;
|
||||
struct list_head gmap_list;
|
||||
unsigned long asce_bits;
|
||||
unsigned long asce;
|
||||
unsigned long asce_limit;
|
||||
unsigned long vdso_base;
|
||||
/* The mmu context allocates 4K page tables. */
|
||||
|
@ -26,12 +26,28 @@ static inline int init_new_context(struct task_struct *tsk,
|
||||
mm->context.has_pgste = 0;
|
||||
mm->context.use_skey = 0;
|
||||
#endif
|
||||
if (mm->context.asce_limit == 0) {
|
||||
switch (mm->context.asce_limit) {
|
||||
case 1UL << 42:
|
||||
/*
|
||||
* forked 3-level task, fall through to set new asce with new
|
||||
* mm->pgd
|
||||
*/
|
||||
case 0:
|
||||
/* context created by exec, set asce limit to 4TB */
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_REGION3;
|
||||
mm->context.asce_limit = STACK_TOP_MAX;
|
||||
} else if (mm->context.asce_limit == (1UL << 31)) {
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_REGION3;
|
||||
break;
|
||||
case 1UL << 53:
|
||||
/* forked 4-level task, set new asce with new mm->pgd */
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_REGION2;
|
||||
break;
|
||||
case 1UL << 31:
|
||||
/* forked 2-level compat task, set new asce with new mm->pgd */
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
|
||||
/* pgd_alloc() did not increase mm->nr_pmds */
|
||||
mm_inc_nr_pmds(mm);
|
||||
}
|
||||
crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
|
||||
@ -42,7 +58,7 @@ static inline int init_new_context(struct task_struct *tsk,
|
||||
|
||||
static inline void set_user_asce(struct mm_struct *mm)
|
||||
{
|
||||
S390_lowcore.user_asce = mm->context.asce_bits | __pa(mm->pgd);
|
||||
S390_lowcore.user_asce = mm->context.asce;
|
||||
if (current->thread.mm_segment.ar4)
|
||||
__ctl_load(S390_lowcore.user_asce, 7, 7);
|
||||
set_cpu_flag(CIF_ASCE);
|
||||
@ -71,7 +87,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
S390_lowcore.user_asce = next->context.asce_bits | __pa(next->pgd);
|
||||
S390_lowcore.user_asce = next->context.asce;
|
||||
if (prev == next)
|
||||
return;
|
||||
if (MACHINE_HAS_TLB_LC)
|
||||
|
@ -52,8 +52,8 @@ static inline unsigned long pgd_entry_type(struct mm_struct *mm)
|
||||
return _REGION2_ENTRY_EMPTY;
|
||||
}
|
||||
|
||||
int crst_table_upgrade(struct mm_struct *, unsigned long limit);
|
||||
void crst_table_downgrade(struct mm_struct *, unsigned long limit);
|
||||
int crst_table_upgrade(struct mm_struct *);
|
||||
void crst_table_downgrade(struct mm_struct *);
|
||||
|
||||
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
|
||||
{
|
||||
|
@ -175,7 +175,7 @@ extern __vector128 init_task_fpu_regs[__NUM_VXRS];
|
||||
regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
|
||||
regs->psw.addr = new_psw; \
|
||||
regs->gprs[15] = new_stackp; \
|
||||
crst_table_downgrade(current->mm, 1UL << 31); \
|
||||
crst_table_downgrade(current->mm); \
|
||||
execve_tail(); \
|
||||
} while (0)
|
||||
|
||||
|
@ -110,8 +110,7 @@ static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
|
||||
static inline void __tlb_flush_kernel(void)
|
||||
{
|
||||
if (MACHINE_HAS_IDTE)
|
||||
__tlb_flush_idte((unsigned long) init_mm.pgd |
|
||||
init_mm.context.asce_bits);
|
||||
__tlb_flush_idte(init_mm.context.asce);
|
||||
else
|
||||
__tlb_flush_global();
|
||||
}
|
||||
@ -133,8 +132,7 @@ static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
|
||||
static inline void __tlb_flush_kernel(void)
|
||||
{
|
||||
if (MACHINE_HAS_TLB_LC)
|
||||
__tlb_flush_idte_local((unsigned long) init_mm.pgd |
|
||||
init_mm.context.asce_bits);
|
||||
__tlb_flush_idte_local(init_mm.context.asce);
|
||||
else
|
||||
__tlb_flush_local();
|
||||
}
|
||||
@ -148,8 +146,7 @@ static inline void __tlb_flush_mm(struct mm_struct * mm)
|
||||
* only ran on the local cpu.
|
||||
*/
|
||||
if (MACHINE_HAS_IDTE && list_empty(&mm->context.gmap_list))
|
||||
__tlb_flush_asce(mm, (unsigned long) mm->pgd |
|
||||
mm->context.asce_bits);
|
||||
__tlb_flush_asce(mm, mm->context.asce);
|
||||
else
|
||||
__tlb_flush_full(mm);
|
||||
}
|
||||
|
@ -89,7 +89,8 @@ void __init paging_init(void)
|
||||
asce_bits = _ASCE_TYPE_REGION3 | _ASCE_TABLE_LENGTH;
|
||||
pgd_type = _REGION3_ENTRY_EMPTY;
|
||||
}
|
||||
S390_lowcore.kernel_asce = (__pa(init_mm.pgd) & PAGE_MASK) | asce_bits;
|
||||
init_mm.context.asce = (__pa(init_mm.pgd) & PAGE_MASK) | asce_bits;
|
||||
S390_lowcore.kernel_asce = init_mm.context.asce;
|
||||
clear_table((unsigned long *) init_mm.pgd, pgd_type,
|
||||
sizeof(unsigned long)*2048);
|
||||
vmem_map_init();
|
||||
|
@ -174,7 +174,7 @@ int s390_mmap_check(unsigned long addr, unsigned long len, unsigned long flags)
|
||||
if (!(flags & MAP_FIXED))
|
||||
addr = 0;
|
||||
if ((addr + len) >= TASK_SIZE)
|
||||
return crst_table_upgrade(current->mm, TASK_MAX_SIZE);
|
||||
return crst_table_upgrade(current->mm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -191,7 +191,7 @@ s390_get_unmapped_area(struct file *filp, unsigned long addr,
|
||||
return area;
|
||||
if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < TASK_MAX_SIZE) {
|
||||
/* Upgrade the page table to 4 levels and retry. */
|
||||
rc = crst_table_upgrade(mm, TASK_MAX_SIZE);
|
||||
rc = crst_table_upgrade(mm);
|
||||
if (rc)
|
||||
return (unsigned long) rc;
|
||||
area = arch_get_unmapped_area(filp, addr, len, pgoff, flags);
|
||||
@ -213,7 +213,7 @@ s390_get_unmapped_area_topdown(struct file *filp, const unsigned long addr,
|
||||
return area;
|
||||
if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < TASK_MAX_SIZE) {
|
||||
/* Upgrade the page table to 4 levels and retry. */
|
||||
rc = crst_table_upgrade(mm, TASK_MAX_SIZE);
|
||||
rc = crst_table_upgrade(mm);
|
||||
if (rc)
|
||||
return (unsigned long) rc;
|
||||
area = arch_get_unmapped_area_topdown(filp, addr, len,
|
||||
|
@ -76,81 +76,52 @@ static void __crst_table_upgrade(void *arg)
|
||||
__tlb_flush_local();
|
||||
}
|
||||
|
||||
int crst_table_upgrade(struct mm_struct *mm, unsigned long limit)
|
||||
int crst_table_upgrade(struct mm_struct *mm)
|
||||
{
|
||||
unsigned long *table, *pgd;
|
||||
unsigned long entry;
|
||||
int flush;
|
||||
|
||||
BUG_ON(limit > TASK_MAX_SIZE);
|
||||
flush = 0;
|
||||
repeat:
|
||||
/* upgrade should only happen from 3 to 4 levels */
|
||||
BUG_ON(mm->context.asce_limit != (1UL << 42));
|
||||
|
||||
table = crst_table_alloc(mm);
|
||||
if (!table)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_bh(&mm->page_table_lock);
|
||||
if (mm->context.asce_limit < limit) {
|
||||
pgd = (unsigned long *) mm->pgd;
|
||||
if (mm->context.asce_limit <= (1UL << 31)) {
|
||||
entry = _REGION3_ENTRY_EMPTY;
|
||||
mm->context.asce_limit = 1UL << 42;
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS |
|
||||
_ASCE_TYPE_REGION3;
|
||||
} else {
|
||||
entry = _REGION2_ENTRY_EMPTY;
|
||||
mm->context.asce_limit = 1UL << 53;
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS |
|
||||
_ASCE_TYPE_REGION2;
|
||||
}
|
||||
crst_table_init(table, entry);
|
||||
pgd_populate(mm, (pgd_t *) table, (pud_t *) pgd);
|
||||
mm->pgd = (pgd_t *) table;
|
||||
mm->task_size = mm->context.asce_limit;
|
||||
table = NULL;
|
||||
flush = 1;
|
||||
}
|
||||
pgd = (unsigned long *) mm->pgd;
|
||||
crst_table_init(table, _REGION2_ENTRY_EMPTY);
|
||||
pgd_populate(mm, (pgd_t *) table, (pud_t *) pgd);
|
||||
mm->pgd = (pgd_t *) table;
|
||||
mm->context.asce_limit = 1UL << 53;
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_REGION2;
|
||||
mm->task_size = mm->context.asce_limit;
|
||||
spin_unlock_bh(&mm->page_table_lock);
|
||||
if (table)
|
||||
crst_table_free(mm, table);
|
||||
if (mm->context.asce_limit < limit)
|
||||
goto repeat;
|
||||
if (flush)
|
||||
on_each_cpu(__crst_table_upgrade, mm, 0);
|
||||
|
||||
on_each_cpu(__crst_table_upgrade, mm, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void crst_table_downgrade(struct mm_struct *mm, unsigned long limit)
|
||||
void crst_table_downgrade(struct mm_struct *mm)
|
||||
{
|
||||
pgd_t *pgd;
|
||||
|
||||
/* downgrade should only happen from 3 to 2 levels (compat only) */
|
||||
BUG_ON(mm->context.asce_limit != (1UL << 42));
|
||||
|
||||
if (current->active_mm == mm) {
|
||||
clear_user_asce();
|
||||
__tlb_flush_mm(mm);
|
||||
}
|
||||
while (mm->context.asce_limit > limit) {
|
||||
pgd = mm->pgd;
|
||||
switch (pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) {
|
||||
case _REGION_ENTRY_TYPE_R2:
|
||||
mm->context.asce_limit = 1UL << 42;
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS |
|
||||
_ASCE_TYPE_REGION3;
|
||||
break;
|
||||
case _REGION_ENTRY_TYPE_R3:
|
||||
mm->context.asce_limit = 1UL << 31;
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS |
|
||||
_ASCE_TYPE_SEGMENT;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
mm->pgd = (pgd_t *) (pgd_val(*pgd) & _REGION_ENTRY_ORIGIN);
|
||||
mm->task_size = mm->context.asce_limit;
|
||||
crst_table_free(mm, (unsigned long *) pgd);
|
||||
}
|
||||
|
||||
pgd = mm->pgd;
|
||||
mm->pgd = (pgd_t *) (pgd_val(*pgd) & _REGION_ENTRY_ORIGIN);
|
||||
mm->context.asce_limit = 1UL << 31;
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
|
||||
mm->task_size = mm->context.asce_limit;
|
||||
crst_table_free(mm, (unsigned long *) pgd);
|
||||
|
||||
if (current->active_mm == mm)
|
||||
set_user_asce(mm);
|
||||
}
|
||||
|
@ -457,7 +457,7 @@ int zpci_dma_init_device(struct zpci_dev *zdev)
|
||||
zdev->dma_table = dma_alloc_cpu_table();
|
||||
if (!zdev->dma_table) {
|
||||
rc = -ENOMEM;
|
||||
goto out_clean;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -477,18 +477,22 @@ int zpci_dma_init_device(struct zpci_dev *zdev)
|
||||
zdev->iommu_bitmap = vzalloc(zdev->iommu_pages / 8);
|
||||
if (!zdev->iommu_bitmap) {
|
||||
rc = -ENOMEM;
|
||||
goto out_reg;
|
||||
goto free_dma_table;
|
||||
}
|
||||
|
||||
rc = zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma,
|
||||
(u64) zdev->dma_table);
|
||||
if (rc)
|
||||
goto out_reg;
|
||||
return 0;
|
||||
goto free_bitmap;
|
||||
|
||||
out_reg:
|
||||
return 0;
|
||||
free_bitmap:
|
||||
vfree(zdev->iommu_bitmap);
|
||||
zdev->iommu_bitmap = NULL;
|
||||
free_dma_table:
|
||||
dma_free_cpu_table(zdev->dma_table);
|
||||
out_clean:
|
||||
zdev->dma_table = NULL;
|
||||
out:
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
@ -24,7 +24,6 @@ CONFIG_INET_AH=y
|
||||
CONFIG_INET_ESP=y
|
||||
CONFIG_INET_IPCOMP=y
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
|
@ -48,7 +48,6 @@ CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=y
|
||||
CONFIG_INET_ESP=y
|
||||
CONFIG_INET_IPCOMP=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
|
@ -48,6 +48,7 @@
|
||||
#define SUN4V_CHIP_SPARC_M6 0x06
|
||||
#define SUN4V_CHIP_SPARC_M7 0x07
|
||||
#define SUN4V_CHIP_SPARC64X 0x8a
|
||||
#define SUN4V_CHIP_SPARC_SN 0x8b
|
||||
#define SUN4V_CHIP_UNKNOWN 0xff
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
@ -423,8 +423,10 @@
|
||||
#define __NR_setsockopt 355
|
||||
#define __NR_mlock2 356
|
||||
#define __NR_copy_file_range 357
|
||||
#define __NR_preadv2 358
|
||||
#define __NR_pwritev2 359
|
||||
|
||||
#define NR_syscalls 358
|
||||
#define NR_syscalls 360
|
||||
|
||||
/* Bitmask values returned from kern_features system call. */
|
||||
#define KERN_FEATURE_MIXED_MODE_STACK 0x00000001
|
||||
|
@ -214,8 +214,7 @@ do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
|
||||
subcc %g1, %g2, %g1 ! Next cacheline
|
||||
bge,pt %icc, 1b
|
||||
nop
|
||||
ba,pt %xcc, dcpe_icpe_tl1_common
|
||||
nop
|
||||
ba,a,pt %xcc, dcpe_icpe_tl1_common
|
||||
|
||||
do_dcpe_tl1_fatal:
|
||||
sethi %hi(1f), %g7
|
||||
@ -224,8 +223,7 @@ do_dcpe_tl1_fatal:
|
||||
mov 0x2, %o0
|
||||
call cheetah_plus_parity_error
|
||||
add %sp, PTREGS_OFF, %o1
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size do_dcpe_tl1,.-do_dcpe_tl1
|
||||
|
||||
.globl do_icpe_tl1
|
||||
@ -259,8 +257,7 @@ do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
|
||||
subcc %g1, %g2, %g1
|
||||
bge,pt %icc, 1b
|
||||
nop
|
||||
ba,pt %xcc, dcpe_icpe_tl1_common
|
||||
nop
|
||||
ba,a,pt %xcc, dcpe_icpe_tl1_common
|
||||
|
||||
do_icpe_tl1_fatal:
|
||||
sethi %hi(1f), %g7
|
||||
@ -269,8 +266,7 @@ do_icpe_tl1_fatal:
|
||||
mov 0x3, %o0
|
||||
call cheetah_plus_parity_error
|
||||
add %sp, PTREGS_OFF, %o1
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size do_icpe_tl1,.-do_icpe_tl1
|
||||
|
||||
.type dcpe_icpe_tl1_common,#function
|
||||
@ -456,7 +452,7 @@ __cheetah_log_error:
|
||||
cmp %g2, 0x63
|
||||
be c_cee
|
||||
nop
|
||||
ba,pt %xcc, c_deferred
|
||||
ba,a,pt %xcc, c_deferred
|
||||
.size __cheetah_log_error,.-__cheetah_log_error
|
||||
|
||||
/* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
|
||||
|
@ -506,6 +506,12 @@ static void __init sun4v_cpu_probe(void)
|
||||
sparc_pmu_type = "sparc-m7";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_SPARC_SN:
|
||||
sparc_cpu_type = "SPARC-SN";
|
||||
sparc_fpu_type = "SPARC-SN integrated FPU";
|
||||
sparc_pmu_type = "sparc-sn";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_SPARC64X:
|
||||
sparc_cpu_type = "SPARC64-X";
|
||||
sparc_fpu_type = "SPARC64-X integrated FPU";
|
||||
|
@ -328,6 +328,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
|
||||
case SUN4V_CHIP_NIAGARA5:
|
||||
case SUN4V_CHIP_SPARC_M6:
|
||||
case SUN4V_CHIP_SPARC_M7:
|
||||
case SUN4V_CHIP_SPARC_SN:
|
||||
case SUN4V_CHIP_SPARC64X:
|
||||
rover_inc_table = niagara_iterate_method;
|
||||
break;
|
||||
|
@ -100,8 +100,8 @@ do_fpdis:
|
||||
fmuld %f0, %f2, %f26
|
||||
faddd %f0, %f2, %f28
|
||||
fmuld %f0, %f2, %f30
|
||||
b,pt %xcc, fpdis_exit
|
||||
nop
|
||||
ba,a,pt %xcc, fpdis_exit
|
||||
|
||||
2: andcc %g5, FPRS_DU, %g0
|
||||
bne,pt %icc, 3f
|
||||
fzero %f32
|
||||
@ -144,8 +144,8 @@ do_fpdis:
|
||||
fmuld %f32, %f34, %f58
|
||||
faddd %f32, %f34, %f60
|
||||
fmuld %f32, %f34, %f62
|
||||
ba,pt %xcc, fpdis_exit
|
||||
nop
|
||||
ba,a,pt %xcc, fpdis_exit
|
||||
|
||||
3: mov SECONDARY_CONTEXT, %g3
|
||||
add %g6, TI_FPREGS, %g1
|
||||
|
||||
@ -197,8 +197,7 @@ fpdis_exit2:
|
||||
fp_other_bounce:
|
||||
call do_fpother
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size fp_other_bounce,.-fp_other_bounce
|
||||
|
||||
.align 32
|
||||
|
@ -414,6 +414,8 @@ sun4v_chip_type:
|
||||
cmp %g2, 'T'
|
||||
be,pt %xcc, 70f
|
||||
cmp %g2, 'M'
|
||||
be,pt %xcc, 70f
|
||||
cmp %g2, 'S'
|
||||
bne,pn %xcc, 49f
|
||||
nop
|
||||
|
||||
@ -433,6 +435,9 @@ sun4v_chip_type:
|
||||
cmp %g2, '7'
|
||||
be,pt %xcc, 5f
|
||||
mov SUN4V_CHIP_SPARC_M7, %g4
|
||||
cmp %g2, 'N'
|
||||
be,pt %xcc, 5f
|
||||
mov SUN4V_CHIP_SPARC_SN, %g4
|
||||
ba,pt %xcc, 49f
|
||||
nop
|
||||
|
||||
@ -461,9 +466,8 @@ sun4v_chip_type:
|
||||
subcc %g3, 1, %g3
|
||||
bne,pt %xcc, 41b
|
||||
add %g1, 1, %g1
|
||||
mov SUN4V_CHIP_SPARC64X, %g4
|
||||
ba,pt %xcc, 5f
|
||||
nop
|
||||
mov SUN4V_CHIP_SPARC64X, %g4
|
||||
|
||||
49:
|
||||
mov SUN4V_CHIP_UNKNOWN, %g4
|
||||
@ -548,8 +552,7 @@ sun4u_init:
|
||||
stxa %g0, [%g7] ASI_DMMU
|
||||
membar #Sync
|
||||
|
||||
ba,pt %xcc, sun4u_continue
|
||||
nop
|
||||
ba,a,pt %xcc, sun4u_continue
|
||||
|
||||
sun4v_init:
|
||||
/* Set ctx 0 */
|
||||
@ -560,14 +563,12 @@ sun4v_init:
|
||||
mov SECONDARY_CONTEXT, %g7
|
||||
stxa %g0, [%g7] ASI_MMU
|
||||
membar #Sync
|
||||
ba,pt %xcc, niagara_tlb_fixup
|
||||
nop
|
||||
ba,a,pt %xcc, niagara_tlb_fixup
|
||||
|
||||
sun4u_continue:
|
||||
BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
|
||||
|
||||
ba,pt %xcc, spitfire_tlb_fixup
|
||||
nop
|
||||
ba,a,pt %xcc, spitfire_tlb_fixup
|
||||
|
||||
niagara_tlb_fixup:
|
||||
mov 3, %g2 /* Set TLB type to hypervisor. */
|
||||
@ -595,6 +596,9 @@ niagara_tlb_fixup:
|
||||
be,pt %xcc, niagara4_patch
|
||||
nop
|
||||
cmp %g1, SUN4V_CHIP_SPARC_M7
|
||||
be,pt %xcc, niagara4_patch
|
||||
nop
|
||||
cmp %g1, SUN4V_CHIP_SPARC_SN
|
||||
be,pt %xcc, niagara4_patch
|
||||
nop
|
||||
|
||||
@ -639,8 +643,7 @@ niagara_patch:
|
||||
call hypervisor_patch_cachetlbops
|
||||
nop
|
||||
|
||||
ba,pt %xcc, tlb_fixup_done
|
||||
nop
|
||||
ba,a,pt %xcc, tlb_fixup_done
|
||||
|
||||
cheetah_tlb_fixup:
|
||||
mov 2, %g2 /* Set TLB type to cheetah+. */
|
||||
@ -659,8 +662,7 @@ cheetah_tlb_fixup:
|
||||
call cheetah_patch_cachetlbops
|
||||
nop
|
||||
|
||||
ba,pt %xcc, tlb_fixup_done
|
||||
nop
|
||||
ba,a,pt %xcc, tlb_fixup_done
|
||||
|
||||
spitfire_tlb_fixup:
|
||||
/* Set TLB type to spitfire. */
|
||||
@ -774,8 +776,7 @@ setup_trap_table:
|
||||
call %o1
|
||||
add %sp, (2047 + 128), %o0
|
||||
|
||||
ba,pt %xcc, 2f
|
||||
nop
|
||||
ba,a,pt %xcc, 2f
|
||||
|
||||
1: sethi %hi(sparc64_ttable_tl0), %o0
|
||||
set prom_set_trap_table_name, %g2
|
||||
@ -814,8 +815,7 @@ setup_trap_table:
|
||||
|
||||
BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
|
||||
|
||||
ba,pt %xcc, 2f
|
||||
nop
|
||||
ba,a,pt %xcc, 2f
|
||||
|
||||
/* Disable STICK_INT interrupts. */
|
||||
1:
|
||||
|
@ -18,8 +18,7 @@ __do_privact:
|
||||
109: or %g7, %lo(109b), %g7
|
||||
call do_privact
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size __do_privact,.-__do_privact
|
||||
|
||||
.type do_mna,#function
|
||||
@ -46,8 +45,7 @@ do_mna:
|
||||
mov %l5, %o2
|
||||
call mem_address_unaligned
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size do_mna,.-do_mna
|
||||
|
||||
.type do_lddfmna,#function
|
||||
@ -65,8 +63,7 @@ do_lddfmna:
|
||||
mov %l5, %o2
|
||||
call handle_lddfmna
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size do_lddfmna,.-do_lddfmna
|
||||
|
||||
.type do_stdfmna,#function
|
||||
@ -84,8 +81,7 @@ do_stdfmna:
|
||||
mov %l5, %o2
|
||||
call handle_stdfmna
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size do_stdfmna,.-do_stdfmna
|
||||
|
||||
.type breakpoint_trap,#function
|
||||
|
@ -245,6 +245,18 @@ static void pci_parse_of_addrs(struct platform_device *op,
|
||||
}
|
||||
}
|
||||
|
||||
static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
|
||||
void *stc, void *host_controller,
|
||||
struct platform_device *op,
|
||||
int numa_node)
|
||||
{
|
||||
sd->iommu = iommu;
|
||||
sd->stc = stc;
|
||||
sd->host_controller = host_controller;
|
||||
sd->op = op;
|
||||
sd->numa_node = numa_node;
|
||||
}
|
||||
|
||||
static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
|
||||
struct device_node *node,
|
||||
struct pci_bus *bus, int devfn)
|
||||
@ -259,13 +271,10 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
|
||||
if (!dev)
|
||||
return NULL;
|
||||
|
||||
op = of_find_device_by_node(node);
|
||||
sd = &dev->dev.archdata;
|
||||
sd->iommu = pbm->iommu;
|
||||
sd->stc = &pbm->stc;
|
||||
sd->host_controller = pbm;
|
||||
sd->op = op = of_find_device_by_node(node);
|
||||
sd->numa_node = pbm->numa_node;
|
||||
|
||||
pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
|
||||
pbm->numa_node);
|
||||
sd = &op->dev.archdata;
|
||||
sd->iommu = pbm->iommu;
|
||||
sd->stc = &pbm->stc;
|
||||
@ -994,6 +1003,27 @@ void pcibios_set_master(struct pci_dev *dev)
|
||||
/* No special bus mastering setup handling */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
int pcibios_add_device(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_dev *pdev;
|
||||
|
||||
/* Add sriov arch specific initialization here.
|
||||
* Copy dev_archdata from PF to VF
|
||||
*/
|
||||
if (dev->is_virtfn) {
|
||||
struct dev_archdata *psd;
|
||||
|
||||
pdev = dev->physfn;
|
||||
psd = &pdev->dev.archdata;
|
||||
pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
|
||||
psd->stc, psd->host_controller, NULL,
|
||||
psd->numa_node);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PCI_IOV */
|
||||
|
||||
static int __init pcibios_init(void)
|
||||
{
|
||||
pci_dfl_cache_line_size = 64 >> 2;
|
||||
|
@ -285,7 +285,8 @@ static void __init sun4v_patch(void)
|
||||
|
||||
sun4v_patch_2insn_range(&__sun4v_2insn_patch,
|
||||
&__sun4v_2insn_patch_end);
|
||||
if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7)
|
||||
if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN)
|
||||
sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
|
||||
&__sun_m7_2insn_patch_end);
|
||||
|
||||
@ -524,6 +525,7 @@ static void __init init_sparc64_elf_hwcap(void)
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
||||
cap |= HWCAP_SPARC_BLKINIT;
|
||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
||||
@ -532,6 +534,7 @@ static void __init init_sparc64_elf_hwcap(void)
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
||||
cap |= HWCAP_SPARC_N2;
|
||||
}
|
||||
@ -561,6 +564,7 @@ static void __init init_sparc64_elf_hwcap(void)
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
||||
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
|
||||
AV_SPARC_ASI_BLK_INIT |
|
||||
@ -570,6 +574,7 @@ static void __init init_sparc64_elf_hwcap(void)
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
|
||||
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
||||
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
|
||||
AV_SPARC_FMAF);
|
||||
|
@ -85,8 +85,7 @@ __spitfire_cee_trap_continue:
|
||||
ba,pt %xcc, etraptl1
|
||||
rd %pc, %g7
|
||||
|
||||
ba,pt %xcc, 2f
|
||||
nop
|
||||
ba,a,pt %xcc, 2f
|
||||
|
||||
1: ba,pt %xcc, etrap_irq
|
||||
rd %pc, %g7
|
||||
@ -100,8 +99,7 @@ __spitfire_cee_trap_continue:
|
||||
mov %l5, %o2
|
||||
call spitfire_access_error
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size __spitfire_access_error,.-__spitfire_access_error
|
||||
|
||||
/* This is the trap handler entry point for ECC correctable
|
||||
@ -179,8 +177,7 @@ __spitfire_data_access_exception_tl1:
|
||||
mov %l5, %o2
|
||||
call spitfire_data_access_exception_tl1
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size __spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1
|
||||
|
||||
.type __spitfire_data_access_exception,#function
|
||||
@ -200,8 +197,7 @@ __spitfire_data_access_exception:
|
||||
mov %l5, %o2
|
||||
call spitfire_data_access_exception
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size __spitfire_data_access_exception,.-__spitfire_data_access_exception
|
||||
|
||||
.type __spitfire_insn_access_exception_tl1,#function
|
||||
@ -220,8 +216,7 @@ __spitfire_insn_access_exception_tl1:
|
||||
mov %l5, %o2
|
||||
call spitfire_insn_access_exception_tl1
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size __spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1
|
||||
|
||||
.type __spitfire_insn_access_exception,#function
|
||||
@ -240,6 +235,5 @@ __spitfire_insn_access_exception:
|
||||
mov %l5, %o2
|
||||
call spitfire_insn_access_exception
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
.size __spitfire_insn_access_exception,.-__spitfire_insn_access_exception
|
||||
|
@ -88,4 +88,4 @@ sys_call_table:
|
||||
/*340*/ .long sys_ni_syscall, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
|
||||
/*345*/ .long sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
|
||||
/*350*/ .long sys_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen
|
||||
/*355*/ .long sys_setsockopt, sys_mlock2, sys_copy_file_range
|
||||
/*355*/ .long sys_setsockopt, sys_mlock2, sys_copy_file_range, sys_preadv2, sys_pwritev2
|
||||
|
@ -89,7 +89,7 @@ sys_call_table32:
|
||||
/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
|
||||
.word sys32_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
|
||||
/*350*/ .word sys32_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen
|
||||
.word compat_sys_setsockopt, sys_mlock2, sys_copy_file_range
|
||||
.word compat_sys_setsockopt, sys_mlock2, sys_copy_file_range, compat_sys_preadv2, compat_sys_pwritev2
|
||||
|
||||
#endif /* CONFIG_COMPAT */
|
||||
|
||||
@ -170,4 +170,4 @@ sys_call_table:
|
||||
/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
|
||||
.word sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
|
||||
/*350*/ .word sys64_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen
|
||||
.word sys_setsockopt, sys_mlock2, sys_copy_file_range
|
||||
.word sys_setsockopt, sys_mlock2, sys_copy_file_range, sys_preadv2, sys_pwritev2
|
||||
|
@ -11,8 +11,7 @@ utrap_trap: /* %g3=handler,%g4=level */
|
||||
mov %l4, %o1
|
||||
call bad_trap
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
|
||||
invoke_utrap:
|
||||
sllx %g3, 3, %g3
|
||||
|
@ -45,6 +45,14 @@ static const struct vio_device_id *vio_match_device(
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int vio_hotplug(struct device *dev, struct kobj_uevent_env *env)
|
||||
{
|
||||
const struct vio_dev *vio_dev = to_vio_dev(dev);
|
||||
|
||||
add_uevent_var(env, "MODALIAS=vio:T%sS%s", vio_dev->type, vio_dev->compat);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vio_bus_match(struct device *dev, struct device_driver *drv)
|
||||
{
|
||||
struct vio_dev *vio_dev = to_vio_dev(dev);
|
||||
@ -105,15 +113,25 @@ static ssize_t type_show(struct device *dev,
|
||||
return sprintf(buf, "%s\n", vdev->type);
|
||||
}
|
||||
|
||||
static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
const struct vio_dev *vdev = to_vio_dev(dev);
|
||||
|
||||
return sprintf(buf, "vio:T%sS%s\n", vdev->type, vdev->compat);
|
||||
}
|
||||
|
||||
static struct device_attribute vio_dev_attrs[] = {
|
||||
__ATTR_RO(devspec),
|
||||
__ATTR_RO(type),
|
||||
__ATTR_RO(modalias),
|
||||
__ATTR_NULL
|
||||
};
|
||||
|
||||
static struct bus_type vio_bus_type = {
|
||||
.name = "vio",
|
||||
.dev_attrs = vio_dev_attrs,
|
||||
.uevent = vio_hotplug,
|
||||
.match = vio_bus_match,
|
||||
.probe = vio_device_probe,
|
||||
.remove = vio_device_remove,
|
||||
|
@ -33,6 +33,10 @@ ENTRY(_start)
|
||||
jiffies = jiffies_64;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPARC64
|
||||
ASSERT((swapper_tsb == 0x0000000000408000), "Error: sparc64 early assembler too large")
|
||||
#endif
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
#ifdef CONFIG_SPARC64
|
||||
|
@ -32,8 +32,7 @@ fill_fixup:
|
||||
rd %pc, %g7
|
||||
call do_sparc64_fault
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
ba,pt %xcc, rtrap
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap
|
||||
|
||||
/* Be very careful about usage of the trap globals here.
|
||||
* You cannot touch %g5 as that has the fault information.
|
||||
|
@ -1769,6 +1769,7 @@ static void __init setup_page_offset(void)
|
||||
max_phys_bits = 47;
|
||||
break;
|
||||
case SUN4V_CHIP_SPARC_M7:
|
||||
case SUN4V_CHIP_SPARC_SN:
|
||||
default:
|
||||
/* M7 and later support 52-bit virtual addresses. */
|
||||
sparc64_va_hole_top = 0xfff8000000000000UL;
|
||||
@ -1986,6 +1987,7 @@ static void __init sun4v_linear_pte_xor_finalize(void)
|
||||
*/
|
||||
switch (sun4v_chip_type) {
|
||||
case SUN4V_CHIP_SPARC_M7:
|
||||
case SUN4V_CHIP_SPARC_SN:
|
||||
pagecv_flag = 0x00;
|
||||
break;
|
||||
default:
|
||||
@ -2138,6 +2140,7 @@ void __init paging_init(void)
|
||||
*/
|
||||
switch (sun4v_chip_type) {
|
||||
case SUN4V_CHIP_SPARC_M7:
|
||||
case SUN4V_CHIP_SPARC_SN:
|
||||
page_cache4v_flag = _PAGE_CP_4V;
|
||||
break;
|
||||
default:
|
||||
|
@ -115,7 +115,7 @@ static __initconst const u64 amd_hw_cache_event_ids
|
||||
/*
|
||||
* AMD Performance Monitor K7 and later.
|
||||
*/
|
||||
static const u64 amd_perfmon_event_map[] =
|
||||
static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
|
||||
{
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
|
||||
|
@ -474,6 +474,7 @@ static __init int _init_perf_amd_iommu(
|
||||
|
||||
static struct perf_amd_iommu __perf_iommu = {
|
||||
.pmu = {
|
||||
.task_ctx_nr = perf_invalid_context,
|
||||
.event_init = perf_iommu_event_init,
|
||||
.add = perf_iommu_add,
|
||||
.del = perf_iommu_del,
|
||||
|
@ -3637,8 +3637,11 @@ __init int intel_pmu_init(void)
|
||||
pr_cont("Knights Landing events, ");
|
||||
break;
|
||||
|
||||
case 142: /* 14nm Kabylake Mobile */
|
||||
case 158: /* 14nm Kabylake Desktop */
|
||||
case 78: /* 14nm Skylake Mobile */
|
||||
case 94: /* 14nm Skylake Desktop */
|
||||
case 85: /* 14nm Skylake Server */
|
||||
x86_pmu.late_ack = true;
|
||||
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
|
||||
memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
|
||||
|
@ -63,7 +63,7 @@ static enum {
|
||||
|
||||
#define LBR_PLM (LBR_KERNEL | LBR_USER)
|
||||
|
||||
#define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
|
||||
#define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */
|
||||
#define LBR_NOT_SUPP -1 /* LBR filter not supported */
|
||||
#define LBR_IGN 0 /* ignored */
|
||||
|
||||
@ -610,8 +610,10 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
|
||||
* The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
|
||||
* in suppress mode. So LBR_SELECT should be set to
|
||||
* (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
|
||||
* But the 10th bit LBR_CALL_STACK does not operate
|
||||
* in suppress mode.
|
||||
*/
|
||||
reg->config = mask ^ x86_pmu.lbr_sel_mask;
|
||||
reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
|
||||
|
||||
if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
|
||||
(br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
|
||||
|
@ -136,9 +136,21 @@ static int __init pt_pmu_hw_init(void)
|
||||
struct dev_ext_attribute *de_attrs;
|
||||
struct attribute **attrs;
|
||||
size_t size;
|
||||
u64 reg;
|
||||
int ret;
|
||||
long i;
|
||||
|
||||
if (boot_cpu_has(X86_FEATURE_VMX)) {
|
||||
/*
|
||||
* Intel SDM, 36.5 "Tracing post-VMXON" says that
|
||||
* "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
|
||||
* post-VMXON.
|
||||
*/
|
||||
rdmsrl(MSR_IA32_VMX_MISC, reg);
|
||||
if (reg & BIT(14))
|
||||
pt_pmu.vmx = true;
|
||||
}
|
||||
|
||||
attrs = NULL;
|
||||
|
||||
for (i = 0; i < PT_CPUID_LEAVES; i++) {
|
||||
@ -269,20 +281,23 @@ static void pt_config(struct perf_event *event)
|
||||
|
||||
reg |= (event->attr.config & PT_CONFIG_MASK);
|
||||
|
||||
event->hw.config = reg;
|
||||
wrmsrl(MSR_IA32_RTIT_CTL, reg);
|
||||
}
|
||||
|
||||
static void pt_config_start(bool start)
|
||||
static void pt_config_stop(struct perf_event *event)
|
||||
{
|
||||
u64 ctl;
|
||||
u64 ctl = READ_ONCE(event->hw.config);
|
||||
|
||||
rdmsrl(MSR_IA32_RTIT_CTL, ctl);
|
||||
if (start)
|
||||
ctl |= RTIT_CTL_TRACEEN;
|
||||
else
|
||||
ctl &= ~RTIT_CTL_TRACEEN;
|
||||
/* may be already stopped by a PMI */
|
||||
if (!(ctl & RTIT_CTL_TRACEEN))
|
||||
return;
|
||||
|
||||
ctl &= ~RTIT_CTL_TRACEEN;
|
||||
wrmsrl(MSR_IA32_RTIT_CTL, ctl);
|
||||
|
||||
WRITE_ONCE(event->hw.config, ctl);
|
||||
|
||||
/*
|
||||
* A wrmsr that disables trace generation serializes other PT
|
||||
* registers and causes all data packets to be written to memory,
|
||||
@ -291,8 +306,7 @@ static void pt_config_start(bool start)
|
||||
* The below WMB, separating data store and aux_head store matches
|
||||
* the consumer's RMB that separates aux_head load and data load.
|
||||
*/
|
||||
if (!start)
|
||||
wmb();
|
||||
wmb();
|
||||
}
|
||||
|
||||
static void pt_config_buffer(void *buf, unsigned int topa_idx,
|
||||
@ -942,11 +956,17 @@ void intel_pt_interrupt(void)
|
||||
if (!ACCESS_ONCE(pt->handle_nmi))
|
||||
return;
|
||||
|
||||
pt_config_start(false);
|
||||
/*
|
||||
* If VMX is on and PT does not support it, don't touch anything.
|
||||
*/
|
||||
if (READ_ONCE(pt->vmx_on))
|
||||
return;
|
||||
|
||||
if (!event)
|
||||
return;
|
||||
|
||||
pt_config_stop(event);
|
||||
|
||||
buf = perf_get_aux(&pt->handle);
|
||||
if (!buf)
|
||||
return;
|
||||
@ -983,6 +1003,35 @@ void intel_pt_interrupt(void)
|
||||
}
|
||||
}
|
||||
|
||||
void intel_pt_handle_vmx(int on)
|
||||
{
|
||||
struct pt *pt = this_cpu_ptr(&pt_ctx);
|
||||
struct perf_event *event;
|
||||
unsigned long flags;
|
||||
|
||||
/* PT plays nice with VMX, do nothing */
|
||||
if (pt_pmu.vmx)
|
||||
return;
|
||||
|
||||
/*
|
||||
* VMXON will clear RTIT_CTL.TraceEn; we need to make
|
||||
* sure to not try to set it while VMX is on. Disable
|
||||
* interrupts to avoid racing with pmu callbacks;
|
||||
* concurrent PMI should be handled fine.
|
||||
*/
|
||||
local_irq_save(flags);
|
||||
WRITE_ONCE(pt->vmx_on, on);
|
||||
|
||||
if (on) {
|
||||
/* prevent pt_config_stop() from writing RTIT_CTL */
|
||||
event = pt->handle.event;
|
||||
if (event)
|
||||
event->hw.config = 0;
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(intel_pt_handle_vmx);
|
||||
|
||||
/*
|
||||
* PMU callbacks
|
||||
*/
|
||||
@ -992,6 +1041,9 @@ static void pt_event_start(struct perf_event *event, int mode)
|
||||
struct pt *pt = this_cpu_ptr(&pt_ctx);
|
||||
struct pt_buffer *buf = perf_get_aux(&pt->handle);
|
||||
|
||||
if (READ_ONCE(pt->vmx_on))
|
||||
return;
|
||||
|
||||
if (!buf || pt_buffer_is_full(buf, pt)) {
|
||||
event->hw.state = PERF_HES_STOPPED;
|
||||
return;
|
||||
@ -1014,7 +1066,8 @@ static void pt_event_stop(struct perf_event *event, int mode)
|
||||
* see comment in intel_pt_interrupt().
|
||||
*/
|
||||
ACCESS_ONCE(pt->handle_nmi) = 0;
|
||||
pt_config_start(false);
|
||||
|
||||
pt_config_stop(event);
|
||||
|
||||
if (event->hw.state == PERF_HES_STOPPED)
|
||||
return;
|
||||
|
@ -65,6 +65,7 @@ enum pt_capabilities {
|
||||
struct pt_pmu {
|
||||
struct pmu pmu;
|
||||
u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
|
||||
bool vmx;
|
||||
};
|
||||
|
||||
/**
|
||||
@ -107,10 +108,12 @@ struct pt_buffer {
|
||||
* struct pt - per-cpu pt context
|
||||
* @handle: perf output handle
|
||||
* @handle_nmi: do handle PT PMI on this cpu, there's an active event
|
||||
* @vmx_on: 1 if VMX is ON on this cpu
|
||||
*/
|
||||
struct pt {
|
||||
struct perf_output_handle handle;
|
||||
int handle_nmi;
|
||||
int vmx_on;
|
||||
};
|
||||
|
||||
#endif /* __INTEL_PT_H__ */
|
||||
|
@ -718,6 +718,7 @@ static int __init rapl_pmu_init(void)
|
||||
break;
|
||||
case 60: /* Haswell */
|
||||
case 69: /* Haswell-Celeron */
|
||||
case 70: /* Haswell GT3e */
|
||||
case 61: /* Broadwell */
|
||||
case 71: /* Broadwell-H */
|
||||
rapl_cntr_mask = RAPL_IDX_HSW;
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user