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https://github.com/edk2-porting/linux-next.git
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watchdog: stm32: add pclk feature for stm32mp1
This patch adds compatible data to manage pclk clock by compatible. Adds stm32mp1 support which requires pclk clock. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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@ -11,12 +11,13 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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@ -54,11 +55,15 @@
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#define TIMEOUT_US 100000
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#define SLEEP_US 1000
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#define HAS_PCLK true
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struct stm32_iwdg {
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struct watchdog_device wdd;
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void __iomem *regs;
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struct clk *clk;
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struct clk *clk_lsi;
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struct clk *clk_pclk;
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unsigned int rate;
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bool has_pclk;
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};
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static inline u32 reg_read(void __iomem *base, u32 reg)
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@ -133,6 +138,44 @@ static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
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return 0;
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}
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static int stm32_iwdg_clk_init(struct platform_device *pdev,
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struct stm32_iwdg *wdt)
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{
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u32 ret;
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wdt->clk_lsi = devm_clk_get(&pdev->dev, "lsi");
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if (IS_ERR(wdt->clk_lsi)) {
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dev_err(&pdev->dev, "Unable to get lsi clock\n");
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return PTR_ERR(wdt->clk_lsi);
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}
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/* optional peripheral clock */
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if (wdt->has_pclk) {
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wdt->clk_pclk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(wdt->clk_pclk)) {
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dev_err(&pdev->dev, "Unable to get pclk clock\n");
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return PTR_ERR(wdt->clk_pclk);
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}
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ret = clk_prepare_enable(wdt->clk_pclk);
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if (ret) {
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dev_err(&pdev->dev, "Unable to prepare pclk clock\n");
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return ret;
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}
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}
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ret = clk_prepare_enable(wdt->clk_lsi);
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if (ret) {
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dev_err(&pdev->dev, "Unable to prepare lsi clock\n");
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clk_disable_unprepare(wdt->clk_pclk);
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return ret;
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}
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wdt->rate = clk_get_rate(wdt->clk_lsi);
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return 0;
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}
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static const struct watchdog_info stm32_iwdg_info = {
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.options = WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE |
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@ -147,49 +190,42 @@ static const struct watchdog_ops stm32_iwdg_ops = {
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.set_timeout = stm32_iwdg_set_timeout,
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};
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static const struct of_device_id stm32_iwdg_of_match[] = {
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{ .compatible = "st,stm32-iwdg", .data = (void *)!HAS_PCLK },
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{ .compatible = "st,stm32mp1-iwdg", .data = (void *)HAS_PCLK },
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{ /* end node */ }
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};
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MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
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static int stm32_iwdg_probe(struct platform_device *pdev)
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{
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struct watchdog_device *wdd;
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const struct of_device_id *match;
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struct stm32_iwdg *wdt;
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struct resource *res;
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void __iomem *regs;
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struct clk *clk;
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int ret;
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match = of_match_device(stm32_iwdg_of_match, &pdev->dev);
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if (!match)
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return -ENODEV;
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->has_pclk = match->data;
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/* This is the timer base. */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(regs)) {
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wdt->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(wdt->regs)) {
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dev_err(&pdev->dev, "Could not get resource\n");
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return PTR_ERR(regs);
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return PTR_ERR(wdt->regs);
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}
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "Unable to get clock\n");
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(&pdev->dev, "Unable to prepare clock %p\n", clk);
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ret = stm32_iwdg_clk_init(pdev, wdt);
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if (ret)
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return ret;
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}
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/*
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* Allocate our watchdog driver data, which has the
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* struct watchdog_device nested within it.
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*/
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt) {
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ret = -ENOMEM;
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goto err;
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}
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/* Initialize struct stm32_iwdg. */
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wdt->regs = regs;
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wdt->clk = clk;
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wdt->rate = clk_get_rate(clk);
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/* Initialize struct watchdog_device. */
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wdd = &wdt->wdd;
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@ -217,7 +253,8 @@ static int stm32_iwdg_probe(struct platform_device *pdev)
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return 0;
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err:
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clk_disable_unprepare(clk);
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clk_disable_unprepare(wdt->clk_lsi);
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clk_disable_unprepare(wdt->clk_pclk);
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return ret;
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}
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@ -227,23 +264,18 @@ static int stm32_iwdg_remove(struct platform_device *pdev)
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struct stm32_iwdg *wdt = platform_get_drvdata(pdev);
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watchdog_unregister_device(&wdt->wdd);
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clk_disable_unprepare(wdt->clk);
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clk_disable_unprepare(wdt->clk_lsi);
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clk_disable_unprepare(wdt->clk_pclk);
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return 0;
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}
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static const struct of_device_id stm32_iwdg_of_match[] = {
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{ .compatible = "st,stm32-iwdg" },
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{ /* end node */ }
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};
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MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
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static struct platform_driver stm32_iwdg_driver = {
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.probe = stm32_iwdg_probe,
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.remove = stm32_iwdg_remove,
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.driver = {
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.name = "iwdg",
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.of_match_table = stm32_iwdg_of_match,
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.of_match_table = of_match_ptr(stm32_iwdg_of_match),
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},
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};
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module_platform_driver(stm32_iwdg_driver);
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