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ARM: imx6q-clk: parent lvds_gate from lvds_sel
Allows fror proper refcounting of the parent clocks when enabling the clock output on CLK1/2 pads. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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@ -208,8 +208,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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* the "output_enable" bit as a gate, even though it's really just
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* enabling clock output.
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*/
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clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
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clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
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clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
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clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
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/* name parent_name reg idx */
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clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
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