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MIPS: Handle OCTEON BBIT instructions in FPU emulator.
The branch emulation needs to handle the OCTEON BBIT instructions, otherwise we get SIGILL instead of emulation. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -803,6 +803,32 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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dec_insn.next_pc_inc;
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dec_insn.next_pc_inc;
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return 1;
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return 1;
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break;
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break;
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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case lwc2_op: /* This is bbit0 on Octeon */
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if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
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*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
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else
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*contpc = regs->cp0_epc + 8;
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return 1;
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case ldc2_op: /* This is bbit032 on Octeon */
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if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
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*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
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else
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*contpc = regs->cp0_epc + 8;
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return 1;
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case swc2_op: /* This is bbit1 on Octeon */
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if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
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*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
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else
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*contpc = regs->cp0_epc + 8;
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return 1;
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case sdc2_op: /* This is bbit132 on Octeon */
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if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
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*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
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else
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*contpc = regs->cp0_epc + 8;
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return 1;
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#endif
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case cop0_op:
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case cop0_op:
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case cop1_op:
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case cop1_op:
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case cop2_op:
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case cop2_op:
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