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https://github.com/edk2-porting/linux-next.git
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arm64: tegra: Add display nodes on Tegra186
Adds the device tree nodes for the display hub and display controllers as well as the DPAUX, DSI and SOR controllers. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
b30a8e610b
commit
c2599da792
@ -546,6 +546,129 @@
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#size-cells = <1>;
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ranges = <0x15000000 0x0 0x15000000 0x01000000>;
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iommus = <&smmu TEGRA186_SID_HOST1X>;
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dpaux1: dpaux@15040000 {
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compatible = "nvidia,tegra186-dpaux";
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reg = <0x15040000 0x10000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
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<&bpmp TEGRA186_CLK_PLLDP>;
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clock-names = "dpaux", "parent";
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resets = <&bpmp TEGRA186_RESET_DPAUX1>;
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reset-names = "dpaux";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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state_dpaux1_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux1_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux1_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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display-hub@15200000 {
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compatible = "nvidia,tegra186-display", "simple-bus";
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resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
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reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
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"wgrp3", "wgrp4", "wgrp5";
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clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
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<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
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<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
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clock-names = "disp", "dsc", "hub";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x15200000 0x15200000 0x40000>;
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display@15200000 {
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compatible = "nvidia,tegra186-dc";
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reg = <0x15200000 0x10000>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
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clock-names = "dc";
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resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
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reset-names = "dc";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
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nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
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nvidia,head = <0>;
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};
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display@15210000 {
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compatible = "nvidia,tegra186-dc";
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reg = <0x15210000 0x10000>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
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clock-names = "dc";
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resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
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reset-names = "dc";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
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iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
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nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
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nvidia,head = <1>;
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};
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display@15220000 {
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compatible = "nvidia,tegra186-dc";
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reg = <0x15220000 0x10000>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
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clock-names = "dc";
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resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
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reset-names = "dc";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
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iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
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nvidia,outputs = <&sor0 &sor1>;
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nvidia,head = <2>;
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};
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};
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dsia: dsi@15300000 {
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compatible = "nvidia,tegra186-dsi";
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reg = <0x15300000 0x10000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_DSI>,
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<&bpmp TEGRA186_CLK_DSIA_LP>,
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<&bpmp TEGRA186_CLK_PLLD>;
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clock-names = "dsi", "lp", "parent";
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resets = <&bpmp TEGRA186_RESET_DSI>;
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reset-names = "dsi";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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};
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vic@15340000 {
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compatible = "nvidia,tegra186-vic";
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@ -558,6 +681,141 @@
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
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};
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dsib: dsi@15400000 {
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compatible = "nvidia,tegra186-dsi";
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reg = <0x15400000 0x10000>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_DSIB>,
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<&bpmp TEGRA186_CLK_DSIB_LP>,
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<&bpmp TEGRA186_CLK_PLLD>;
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clock-names = "dsi", "lp", "parent";
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resets = <&bpmp TEGRA186_RESET_DSIB>;
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reset-names = "dsi";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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};
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sor0: sor@15540000 {
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compatible = "nvidia,tegra186-sor";
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reg = <0x15540000 0x10000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SOR0>,
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<&bpmp TEGRA186_CLK_SOR0_OUT>,
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<&bpmp TEGRA186_CLK_PLLD2>,
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<&bpmp TEGRA186_CLK_PLLDP>,
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<&bpmp TEGRA186_CLK_SOR_SAFE>,
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<&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
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clock-names = "sor", "out", "parent", "dp", "safe",
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"pad";
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resets = <&bpmp TEGRA186_RESET_SOR0>;
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reset-names = "sor";
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pinctrl-0 = <&state_dpaux_aux>;
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pinctrl-1 = <&state_dpaux_i2c>;
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pinctrl-2 = <&state_dpaux_off>;
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pinctrl-names = "aux", "i2c", "off";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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nvidia,interface = <0>;
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};
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sor1: sor@15580000 {
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compatible = "nvidia,tegra186-sor1";
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reg = <0x15580000 0x10000>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SOR1>,
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<&bpmp TEGRA186_CLK_SOR1_OUT>,
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<&bpmp TEGRA186_CLK_PLLD3>,
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<&bpmp TEGRA186_CLK_PLLDP>,
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<&bpmp TEGRA186_CLK_SOR_SAFE>,
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<&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
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clock-names = "sor", "out", "parent", "dp", "safe",
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"pad";
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resets = <&bpmp TEGRA186_RESET_SOR1>;
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reset-names = "sor";
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pinctrl-0 = <&state_dpaux1_aux>;
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pinctrl-1 = <&state_dpaux1_i2c>;
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pinctrl-2 = <&state_dpaux1_off>;
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pinctrl-names = "aux", "i2c", "off";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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nvidia,interface = <1>;
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};
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dpaux: dpaux@155c0000 {
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compatible = "nvidia,tegra186-dpaux";
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reg = <0x155c0000 0x10000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_DPAUX>,
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<&bpmp TEGRA186_CLK_PLLDP>;
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clock-names = "dpaux", "parent";
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resets = <&bpmp TEGRA186_RESET_DPAUX>;
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reset-names = "dpaux";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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state_dpaux_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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padctl@15880000 {
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compatible = "nvidia,tegra186-dsi-padctl";
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reg = <0x15880000 0x10000>;
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resets = <&bpmp TEGRA186_RESET_DSI>;
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reset-names = "dsi";
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status = "disabled";
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};
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dsic: dsi@15900000 {
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compatible = "nvidia,tegra186-dsi";
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reg = <0x15900000 0x10000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_DSIC>,
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<&bpmp TEGRA186_CLK_DSIC_LP>,
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<&bpmp TEGRA186_CLK_PLLD>;
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clock-names = "dsi", "lp", "parent";
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resets = <&bpmp TEGRA186_RESET_DSIC>;
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reset-names = "dsi";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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};
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dsid: dsi@15940000 {
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compatible = "nvidia,tegra186-dsi";
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reg = <0x15940000 0x10000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_DSID>,
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<&bpmp TEGRA186_CLK_DSID_LP>,
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<&bpmp TEGRA186_CLK_PLLD>;
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clock-names = "dsi", "lp", "parent";
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resets = <&bpmp TEGRA186_RESET_DSID>;
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reset-names = "dsi";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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};
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};
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gpu@17000000 {
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