mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 06:34:11 +08:00
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes
Fix some pageflip, oopses and some better clock support for some chipsets * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nv50/disp: min/max are reversed in nv50_crtc_gamma_set() drm/nouveau/sw: fix oops if gpu has its display block disabled drm/nouveau: unreference fence after syncing drm/nouveau/kms: send timestamp data for correct head in flip completion events drm/nouveau/clk: Add support for NVAA/NVAC drm/nouveau/fifo: Hook up pause and resume for NV50 and NV84+ drm/nv10/plane: some chipsets don't support NV12 drm/nv10/plane: add downscaling restrictions drm/nv10/plane: fix format computation drm/nv04-nv30/clk: provide an empty domain list
This commit is contained in:
Dave Airlie
commit
c17f5bb529
@ -59,6 +59,7 @@ nouveau-y += core/subdev/clock/nv40.o
|
||||
nouveau-y += core/subdev/clock/nv50.o
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||||
nouveau-y += core/subdev/clock/nv84.o
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nouveau-y += core/subdev/clock/nva3.o
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||||
nouveau-y += core/subdev/clock/nvaa.o
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nouveau-y += core/subdev/clock/nvc0.o
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nouveau-y += core/subdev/clock/nve0.o
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nouveau-y += core/subdev/clock/pllnv04.o
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@ -283,7 +283,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
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device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
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device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
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device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
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device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
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@ -311,7 +311,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
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device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
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device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
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device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
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device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
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@ -33,6 +33,7 @@
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#include <engine/dmaobj.h>
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#include <engine/fifo.h>
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#include "nv04.h"
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#include "nv50.h"
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/*******************************************************************************
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@ -460,6 +461,8 @@ nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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nv_subdev(priv)->intr = nv04_fifo_intr;
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nv_engine(priv)->cclass = &nv50_fifo_cclass;
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nv_engine(priv)->sclass = nv50_fifo_sclass;
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priv->base.pause = nv04_fifo_pause;
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priv->base.start = nv04_fifo_start;
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return 0;
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}
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@ -35,6 +35,7 @@
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#include <engine/dmaobj.h>
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#include <engine/fifo.h>
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#include "nv04.h"
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#include "nv50.h"
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/*******************************************************************************
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@ -432,6 +433,8 @@ nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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nv_subdev(priv)->intr = nv04_fifo_intr;
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nv_engine(priv)->cclass = &nv84_fifo_cclass;
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nv_engine(priv)->sclass = nv84_fifo_sclass;
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priv->base.pause = nv04_fifo_pause;
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priv->base.start = nv04_fifo_start;
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return 0;
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}
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@ -176,7 +176,7 @@ nv50_software_context_ctor(struct nouveau_object *parent,
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if (ret)
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return ret;
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chan->vblank.nr_event = pdisp->vblank->index_nr;
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chan->vblank.nr_event = pdisp ? pdisp->vblank->index_nr : 0;
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chan->vblank.event = kzalloc(chan->vblank.nr_event *
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sizeof(*chan->vblank.event), GFP_KERNEL);
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if (!chan->vblank.event)
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@ -14,6 +14,9 @@ enum nv_clk_src {
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nv_clk_src_hclk,
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nv_clk_src_hclkm3,
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nv_clk_src_hclkm3d2,
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nv_clk_src_hclkm2d3, /* NVAA */
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nv_clk_src_hclkm4, /* NVAA */
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nv_clk_src_cclk, /* NVAA */
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nv_clk_src_host,
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@ -127,6 +130,7 @@ extern struct nouveau_oclass nv04_clock_oclass;
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extern struct nouveau_oclass nv40_clock_oclass;
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extern struct nouveau_oclass *nv50_clock_oclass;
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extern struct nouveau_oclass *nv84_clock_oclass;
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extern struct nouveau_oclass *nvaa_clock_oclass;
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extern struct nouveau_oclass nva3_clock_oclass;
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extern struct nouveau_oclass nvc0_clock_oclass;
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extern struct nouveau_oclass nve0_clock_oclass;
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@ -69,6 +69,11 @@ nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
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return 0;
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}
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static struct nouveau_clocks
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nv04_domain[] = {
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{ nv_clk_src_max }
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};
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static int
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nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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@ -77,7 +82,7 @@ nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nv04_clock_priv *priv;
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int ret;
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ret = nouveau_clock_create(parent, engine, oclass, NULL, &priv);
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ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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445
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
Normal file
445
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
Normal file
@ -0,0 +1,445 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <engine/fifo.h>
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#include <subdev/bios.h>
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#include <subdev/bios/pll.h>
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#include <subdev/timer.h>
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#include <subdev/clock.h>
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#include "pll.h"
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struct nvaa_clock_priv {
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struct nouveau_clock base;
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enum nv_clk_src csrc, ssrc, vsrc;
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u32 cctrl, sctrl;
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u32 ccoef, scoef;
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u32 cpost, spost;
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u32 vdiv;
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};
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static u32
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read_div(struct nouveau_clock *clk)
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{
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return nv_rd32(clk, 0x004600);
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}
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static u32
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read_pll(struct nouveau_clock *clk, u32 base)
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{
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u32 ctrl = nv_rd32(clk, base + 0);
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u32 coef = nv_rd32(clk, base + 4);
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u32 ref = clk->read(clk, nv_clk_src_href);
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u32 post_div = 0;
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u32 clock = 0;
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int N1, M1;
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switch (base){
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case 0x4020:
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post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16);
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break;
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case 0x4028:
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post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16;
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break;
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default:
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break;
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}
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N1 = (coef & 0x0000ff00) >> 8;
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M1 = (coef & 0x000000ff);
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if ((ctrl & 0x80000000) && M1) {
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clock = ref * N1 / M1;
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clock = clock / post_div;
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}
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return clock;
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}
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static int
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nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
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{
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struct nvaa_clock_priv *priv = (void *)clk;
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u32 mast = nv_rd32(clk, 0x00c054);
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u32 P = 0;
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switch (src) {
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case nv_clk_src_crystal:
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return nv_device(priv)->crystal;
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case nv_clk_src_href:
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return 100000; /* PCIE reference clock */
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case nv_clk_src_hclkm4:
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return clk->read(clk, nv_clk_src_href) * 4;
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case nv_clk_src_hclkm2d3:
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return clk->read(clk, nv_clk_src_href) * 2 / 3;
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case nv_clk_src_host:
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switch (mast & 0x000c0000) {
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case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3);
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case 0x00040000: break;
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case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4);
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case 0x000c0000: return clk->read(clk, nv_clk_src_cclk);
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}
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break;
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case nv_clk_src_core:
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P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16;
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switch (mast & 0x00000003) {
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case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P;
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case 0x00000001: return 0;
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case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P;
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case 0x00000003: return read_pll(clk, 0x004028) >> P;
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}
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break;
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case nv_clk_src_cclk:
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if ((mast & 0x03000000) != 0x03000000)
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return clk->read(clk, nv_clk_src_core);
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if ((mast & 0x00000200) == 0x00000000)
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return clk->read(clk, nv_clk_src_core);
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switch (mast & 0x00000c00) {
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case 0x00000000: return clk->read(clk, nv_clk_src_href);
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case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4);
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case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3);
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default: return 0;
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}
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case nv_clk_src_shader:
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P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16;
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switch (mast & 0x00000030) {
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case 0x00000000:
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if (mast & 0x00000040)
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return clk->read(clk, nv_clk_src_href) >> P;
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return clk->read(clk, nv_clk_src_crystal) >> P;
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case 0x00000010: break;
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case 0x00000020: return read_pll(clk, 0x004028) >> P;
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case 0x00000030: return read_pll(clk, 0x004020) >> P;
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}
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break;
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case nv_clk_src_mem:
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return 0;
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break;
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case nv_clk_src_vdec:
|
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P = (read_div(clk) & 0x00000700) >> 8;
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switch (mast & 0x00400000) {
|
||||
case 0x00400000:
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||||
return clk->read(clk, nv_clk_src_core) >> P;
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||||
break;
|
||||
default:
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||||
return 500000 >> P;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
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||||
nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
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||||
return 0;
|
||||
}
|
||||
|
||||
static u32
|
||||
calc_pll(struct nvaa_clock_priv *priv, u32 reg,
|
||||
u32 clock, int *N, int *M, int *P)
|
||||
{
|
||||
struct nouveau_bios *bios = nouveau_bios(priv);
|
||||
struct nvbios_pll pll;
|
||||
struct nouveau_clock *clk = &priv->base;
|
||||
int ret;
|
||||
|
||||
ret = nvbios_pll_parse(bios, reg, &pll);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
pll.vco2.max_freq = 0;
|
||||
pll.refclk = clk->read(clk, nv_clk_src_href);
|
||||
if (!pll.refclk)
|
||||
return 0;
|
||||
|
||||
return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
|
||||
}
|
||||
|
||||
static inline u32
|
||||
calc_P(u32 src, u32 target, int *div)
|
||||
{
|
||||
u32 clk0 = src, clk1 = src;
|
||||
for (*div = 0; *div <= 7; (*div)++) {
|
||||
if (clk0 <= target) {
|
||||
clk1 = clk0 << (*div ? 1 : 0);
|
||||
break;
|
||||
}
|
||||
clk0 >>= 1;
|
||||
}
|
||||
|
||||
if (target - clk0 <= clk1 - target)
|
||||
return clk0;
|
||||
(*div)--;
|
||||
return clk1;
|
||||
}
|
||||
|
||||
static int
|
||||
nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
|
||||
{
|
||||
struct nvaa_clock_priv *priv = (void *)clk;
|
||||
const int shader = cstate->domain[nv_clk_src_shader];
|
||||
const int core = cstate->domain[nv_clk_src_core];
|
||||
const int vdec = cstate->domain[nv_clk_src_vdec];
|
||||
u32 out = 0, clock = 0;
|
||||
int N, M, P1, P2 = 0;
|
||||
int divs = 0;
|
||||
|
||||
/* cclk: find suitable source, disable PLL if we can */
|
||||
if (core < clk->read(clk, nv_clk_src_hclkm4))
|
||||
out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs);
|
||||
|
||||
/* Calculate clock * 2, so shader clock can use it too */
|
||||
clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1);
|
||||
|
||||
if (abs(core - out) <=
|
||||
abs(core - (clock >> 1))) {
|
||||
priv->csrc = nv_clk_src_hclkm4;
|
||||
priv->cctrl = divs << 16;
|
||||
} else {
|
||||
/* NVCTRL is actually used _after_ NVPOST, and after what we
|
||||
* call NVPLL. To make matters worse, NVPOST is an integer
|
||||
* divider instead of a right-shift number. */
|
||||
if(P1 > 2) {
|
||||
P2 = P1 - 2;
|
||||
P1 = 2;
|
||||
}
|
||||
|
||||
priv->csrc = nv_clk_src_core;
|
||||
priv->ccoef = (N << 8) | M;
|
||||
|
||||
priv->cctrl = (P2 + 1) << 16;
|
||||
priv->cpost = (1 << P1) << 16;
|
||||
}
|
||||
|
||||
/* sclk: nvpll + divisor, href or spll */
|
||||
out = 0;
|
||||
if (shader == clk->read(clk, nv_clk_src_href)) {
|
||||
priv->ssrc = nv_clk_src_href;
|
||||
} else {
|
||||
clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
|
||||
if (priv->csrc == nv_clk_src_core) {
|
||||
out = calc_P((core << 1), shader, &divs);
|
||||
}
|
||||
|
||||
if (abs(shader - out) <=
|
||||
abs(shader - clock) &&
|
||||
(divs + P2) <= 7) {
|
||||
priv->ssrc = nv_clk_src_core;
|
||||
priv->sctrl = (divs + P2) << 16;
|
||||
} else {
|
||||
priv->ssrc = nv_clk_src_shader;
|
||||
priv->scoef = (N << 8) | M;
|
||||
priv->sctrl = P1 << 16;
|
||||
}
|
||||
}
|
||||
|
||||
/* vclk */
|
||||
out = calc_P(core, vdec, &divs);
|
||||
clock = calc_P(500000, vdec, &P1);
|
||||
if(abs(vdec - out) <=
|
||||
abs(vdec - clock)) {
|
||||
priv->vsrc = nv_clk_src_cclk;
|
||||
priv->vdiv = divs << 16;
|
||||
} else {
|
||||
priv->vsrc = nv_clk_src_vdec;
|
||||
priv->vdiv = P1 << 16;
|
||||
}
|
||||
|
||||
/* Print strategy! */
|
||||
nv_debug(priv, "nvpll: %08x %08x %08x\n",
|
||||
priv->ccoef, priv->cpost, priv->cctrl);
|
||||
nv_debug(priv, " spll: %08x %08x %08x\n",
|
||||
priv->scoef, priv->spost, priv->sctrl);
|
||||
nv_debug(priv, " vdiv: %08x\n", priv->vdiv);
|
||||
if (priv->csrc == nv_clk_src_hclkm4)
|
||||
nv_debug(priv, "core: hrefm4\n");
|
||||
else
|
||||
nv_debug(priv, "core: nvpll\n");
|
||||
|
||||
if (priv->ssrc == nv_clk_src_hclkm4)
|
||||
nv_debug(priv, "shader: hrefm4\n");
|
||||
else if (priv->ssrc == nv_clk_src_core)
|
||||
nv_debug(priv, "shader: nvpll\n");
|
||||
else
|
||||
nv_debug(priv, "shader: spll\n");
|
||||
|
||||
if (priv->vsrc == nv_clk_src_hclkm4)
|
||||
nv_debug(priv, "vdec: 500MHz\n");
|
||||
else
|
||||
nv_debug(priv, "vdec: core\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nvaa_clock_prog(struct nouveau_clock *clk)
|
||||
{
|
||||
struct nvaa_clock_priv *priv = (void *)clk;
|
||||
struct nouveau_fifo *pfifo = nouveau_fifo(clk);
|
||||
unsigned long flags;
|
||||
u32 pllmask = 0, mast, ptherm_gate;
|
||||
int ret = -EBUSY;
|
||||
|
||||
/* halt and idle execution engines */
|
||||
ptherm_gate = nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
|
||||
nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
|
||||
/* Wait until the interrupt handler is finished */
|
||||
if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
|
||||
goto resume;
|
||||
|
||||
if (pfifo)
|
||||
pfifo->pause(pfifo, &flags);
|
||||
|
||||
if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
|
||||
goto resume;
|
||||
if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
|
||||
goto resume;
|
||||
|
||||
/* First switch to safe clocks: href */
|
||||
mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640);
|
||||
mast &= ~0x00400e73;
|
||||
mast |= 0x03000000;
|
||||
|
||||
switch (priv->csrc) {
|
||||
case nv_clk_src_hclkm4:
|
||||
nv_mask(clk, 0x4028, 0x00070000, priv->cctrl);
|
||||
mast |= 0x00000002;
|
||||
break;
|
||||
case nv_clk_src_core:
|
||||
nv_wr32(clk, 0x402c, priv->ccoef);
|
||||
nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl);
|
||||
nv_wr32(clk, 0x4040, priv->cpost);
|
||||
pllmask |= (0x3 << 8);
|
||||
mast |= 0x00000003;
|
||||
break;
|
||||
default:
|
||||
nv_warn(priv,"Reclocking failed: unknown core clock\n");
|
||||
goto resume;
|
||||
}
|
||||
|
||||
switch (priv->ssrc) {
|
||||
case nv_clk_src_href:
|
||||
nv_mask(clk, 0x4020, 0x00070000, 0x00000000);
|
||||
/* mast |= 0x00000000; */
|
||||
break;
|
||||
case nv_clk_src_core:
|
||||
nv_mask(clk, 0x4020, 0x00070000, priv->sctrl);
|
||||
mast |= 0x00000020;
|
||||
break;
|
||||
case nv_clk_src_shader:
|
||||
nv_wr32(clk, 0x4024, priv->scoef);
|
||||
nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl);
|
||||
nv_wr32(clk, 0x4070, priv->spost);
|
||||
pllmask |= (0x3 << 12);
|
||||
mast |= 0x00000030;
|
||||
break;
|
||||
default:
|
||||
nv_warn(priv,"Reclocking failed: unknown sclk clock\n");
|
||||
goto resume;
|
||||
}
|
||||
|
||||
if (!nv_wait(clk, 0x004080, pllmask, pllmask)) {
|
||||
nv_warn(priv,"Reclocking failed: unstable PLLs\n");
|
||||
goto resume;
|
||||
}
|
||||
|
||||
switch (priv->vsrc) {
|
||||
case nv_clk_src_cclk:
|
||||
mast |= 0x00400000;
|
||||
default:
|
||||
nv_wr32(clk, 0x4600, priv->vdiv);
|
||||
}
|
||||
|
||||
nv_wr32(clk, 0xc054, mast);
|
||||
ret = 0;
|
||||
|
||||
resume:
|
||||
if (pfifo)
|
||||
pfifo->start(pfifo, &flags);
|
||||
|
||||
nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
|
||||
nv_wr32(clk, 0x020060, ptherm_gate);
|
||||
|
||||
/* Disable some PLLs and dividers when unused */
|
||||
if (priv->csrc != nv_clk_src_core) {
|
||||
nv_wr32(clk, 0x4040, 0x00000000);
|
||||
nv_mask(clk, 0x4028, 0x80000000, 0x00000000);
|
||||
}
|
||||
|
||||
if (priv->ssrc != nv_clk_src_shader) {
|
||||
nv_wr32(clk, 0x4070, 0x00000000);
|
||||
nv_mask(clk, 0x4020, 0x80000000, 0x00000000);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
nvaa_clock_tidy(struct nouveau_clock *clk)
|
||||
{
|
||||
}
|
||||
|
||||
static struct nouveau_clocks
|
||||
nvaa_domains[] = {
|
||||
{ nv_clk_src_crystal, 0xff },
|
||||
{ nv_clk_src_href , 0xff },
|
||||
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
|
||||
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
|
||||
{ nv_clk_src_vdec , 0xff, 0, "vdec", 1000 },
|
||||
{ nv_clk_src_max }
|
||||
};
|
||||
|
||||
static int
|
||||
nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, void *data, u32 size,
|
||||
struct nouveau_object **pobject)
|
||||
{
|
||||
struct nvaa_clock_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->base.read = nvaa_clock_read;
|
||||
priv->base.calc = nvaa_clock_calc;
|
||||
priv->base.prog = nvaa_clock_prog;
|
||||
priv->base.tidy = nvaa_clock_tidy;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nouveau_oclass *
|
||||
nvaa_clock_oclass = &(struct nouveau_oclass) {
|
||||
.handle = NV_SUBDEV(CLOCK, 0xaa),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = nvaa_clock_ctor,
|
||||
.dtor = _nouveau_clock_dtor,
|
||||
.init = _nouveau_clock_init,
|
||||
.fini = _nouveau_clock_fini,
|
||||
},
|
||||
};
|
||||
@ -58,8 +58,8 @@ struct nouveau_plane {
|
||||
};
|
||||
|
||||
static uint32_t formats[] = {
|
||||
DRM_FORMAT_NV12,
|
||||
DRM_FORMAT_UYVY,
|
||||
DRM_FORMAT_NV12,
|
||||
};
|
||||
|
||||
/* Sine can be approximated with
|
||||
@ -99,13 +99,28 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
|
||||
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
||||
struct nouveau_bo *cur = nv_plane->cur;
|
||||
bool flip = nv_plane->flip;
|
||||
int format = ALIGN(src_w * 4, 0x100);
|
||||
int soff = NV_PCRTC0_SIZE * nv_crtc->index;
|
||||
int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index;
|
||||
int ret;
|
||||
int format, ret;
|
||||
|
||||
/* Source parameters given in 16.16 fixed point, ignore fractional. */
|
||||
src_x >>= 16;
|
||||
src_y >>= 16;
|
||||
src_w >>= 16;
|
||||
src_h >>= 16;
|
||||
|
||||
format = ALIGN(src_w * 4, 0x100);
|
||||
|
||||
if (format > 0xffff)
|
||||
return -EINVAL;
|
||||
return -ERANGE;
|
||||
|
||||
if (dev->chipset >= 0x30) {
|
||||
if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1))
|
||||
return -ERANGE;
|
||||
} else {
|
||||
if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3))
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM);
|
||||
if (ret)
|
||||
@ -113,12 +128,6 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
|
||||
|
||||
nv_plane->cur = nv_fb->nvbo;
|
||||
|
||||
/* Source parameters given in 16.16 fixed point, ignore fractional. */
|
||||
src_x = src_x >> 16;
|
||||
src_y = src_y >> 16;
|
||||
src_w = src_w >> 16;
|
||||
src_h = src_h >> 16;
|
||||
|
||||
nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY);
|
||||
nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);
|
||||
|
||||
@ -245,14 +254,25 @@ nv10_overlay_init(struct drm_device *device)
|
||||
{
|
||||
struct nouveau_device *dev = nouveau_dev(device);
|
||||
struct nouveau_plane *plane = kzalloc(sizeof(struct nouveau_plane), GFP_KERNEL);
|
||||
int num_formats = ARRAY_SIZE(formats);
|
||||
int ret;
|
||||
|
||||
if (!plane)
|
||||
return;
|
||||
|
||||
switch (dev->chipset) {
|
||||
case 0x10:
|
||||
case 0x11:
|
||||
case 0x15:
|
||||
case 0x1a:
|
||||
case 0x20:
|
||||
num_formats = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = drm_plane_init(device, &plane->base, 3 /* both crtc's */,
|
||||
&nv10_plane_funcs,
|
||||
formats, ARRAY_SIZE(formats), false);
|
||||
formats, num_formats, false);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
|
||||
@ -608,6 +608,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
|
||||
fence = nouveau_fence_ref(new_bo->bo.sync_obj);
|
||||
spin_unlock(&new_bo->bo.bdev->fence_lock);
|
||||
ret = nouveau_fence_sync(fence, chan);
|
||||
nouveau_fence_unref(&fence);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -701,7 +702,7 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
|
||||
|
||||
s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head);
|
||||
if (s->event)
|
||||
drm_send_vblank_event(dev, -1, s->event);
|
||||
drm_send_vblank_event(dev, s->crtc, s->event);
|
||||
|
||||
list_del(&s->head);
|
||||
if (ps)
|
||||
|
||||
@ -1265,7 +1265,7 @@ nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
|
||||
uint32_t start, uint32_t size)
|
||||
{
|
||||
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
||||
u32 end = max(start + size, (u32)256);
|
||||
u32 end = min_t(u32, start + size, 256);
|
||||
u32 i;
|
||||
|
||||
for (i = start; i < end; i++) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user